JP5033101B2 - D / A converter - Google Patents

Description

  The present invention relates to a D / A converter, and more particularly to a D / A converter suitable for audio equipment.

  Generally, a DAC (Digital to Analog Converter: hereinafter referred to as a D / A converter) needs to perform a filtering process in accordance with a sampling frequency corresponding to recording of an audio signal to be reproduced. For this reason, the D / A converter includes a digital filter having a band corresponding to digital signals having different data rates in one device. The conventional digital filter includes a plurality of digital filters that are increased in multiple stages by interpolating the data rate of the digital signal to be reproduced.

  FIG. 6 is a diagram exemplifying a D / A converter 5 having a plurality of digital filters, and shows a D / A converter capable of supporting digital signals with data rates of standard speed, double speed, and quadruple speed. . The standard speed is a digital signal having a sampling frequency of 1 fs of 30 to 54 kHz, the double speed is a digital signal of 1 fs of 54 to 108 kHz, and the quadruple speed is a digital signal of 1 fs of 108 to 216 kHz.

In the configuration shown in the figure, the D / A converter 5 has three FIR (Finite Impulse Response) filters 1 to 3, each of which doubles the data rate of the input digital signal. As a result, all the signals output from the D / A converter 5 are multiplied by 8 regardless of the sampling frequency.
The output digital signal can be increased in data rate at a magnification according to the sampling frequency in the S & H (Sample & Hold) circuit 4 in the subsequent stage. And it inputs into the amplifier which is not illustrated through the delta-sigma modulator 6 and an analog filter. Table 1 shows changes in the frequency of digital signals in the prior art.

As a conventional technique of such a D / A converter, for example, there is Patent Document 1.
Japanese Patent No. 3095395

Prior art all multiply digital signals by 8 regardless of their data rates. For this reason, a digital signal having a high data rate cannot be multiplied by eight at a stretch, and the three FIR filters 1 to 3 are provided to gradually increase the data rate. However, such a configuration has a drawback in that the calculation control in each FIR filter is complicated, and further, the control of the operation timing between the three FIR filters is complicated, and therefore the design man-hour is large. For this reason, a D / A converter with simpler control has been desired in the industry.
The present invention has been made in view of the above points, and can deal with digital signals having a plurality of types of sampling frequencies by using a single digital filter. Therefore, control and design are simple, and a plurality of types are possible. An object of the present invention is to provide a D / A converter that is advantageous in reducing the size of an element because a single memory that stores the filter coefficients can be used.

  In order to solve the above problems, a D / A converter according to claim 1 of the present invention inputs a digital input signal classified into one of a plurality of modes according to a data rate, and A D / A converter having a digital filter for sequentially multiplying an input signal by a plurality of filter coefficients, wherein the digital filter stores a plurality of the filter coefficients, and mode detection for detecting a mode of the digital input signal Means, a reading means for reading out the filter coefficient from the storage device according to the mode detected by the mode detecting means, and the filter coefficient and the digital input signal read out by the reading means. Calculation means for performing a convolution calculation at a constant operation speed regardless of the mode, and the storage device includes a plurality of the modes. The filter coefficient necessary for the mode in which the digital input signal is multiplied by the largest number of filter coefficients is stored, and the reading means is used for the convolution operation from the filter coefficients stored in the storage device. The filter coefficient is read according to the mode of the digital input signal.

According to a second aspect of the present invention, in the D / A converter according to the first aspect of the present invention, the storage device stores the filter coefficient at an address corresponding to the order of multiplication with the digital input signal, and the reading means is constant. The filter coefficients are read out at a predetermined interval by reading out the filter coefficients at the addresses.
The D / A converter according to claim 3 is the D / A converter according to claim 1 or 2, wherein the plurality of modes are a standard speed mode having a predetermined data rate, and a data rate is the standard speed mode. And when the digital detection signal is detected to be in the n-times speed mode by the mode detection means, the calculation means is 1 / n times that in the standard speed mode. It is characterized in that the digital input signal is made to have a constant data rate regardless of the mode by performing a convolution operation on the digital input signal at a rate of.
D / A converter according to claim 4, in any one of claims 1 to 3, comprising a sample-and-hold circuit in the subsequent stage of the digital filter, the sample-and-hold circuit, regardless of the mode The data rate of the digital input signal is increased by a predetermined magnification.

  According to the first aspect of the present invention, the arithmetic means performs a convolution operation at a constant operation speed regardless of the mode of the digital input signal, so that a plurality of types having different data rates by one digital filter can be obtained. It can handle digital input signals. For this reason, it is possible to configure a D / A converter that is easier to control than to control while adjusting a plurality of digital filters. Further, since the control is simplified, the number of design steps for the digital filter can be reduced.

  Further, the filter coefficient necessary for the mode in which the digital input signal is multiplied by the largest number of filter coefficients is stored in the storage device, and the reading means reads the necessary filter coefficient in accordance with the mode of the digital input signal. it can. For this reason, a minimum filter coefficient can be stored in one storage device, and a plurality of modes can be supported. A memory capacity and an area occupied by elements are reduced, and a D / A converter suitable for downsizing can be obtained. Can be provided.

According to the second aspect of the invention, the reading means can cope with a plurality of modes by reading out the filter coefficients by thinning them out at a constant interval. For this reason, the reading operation is simplified and the control is further simplified.
According to the third aspect of the present invention, the calculation means can perform the convolution calculation at a constant operation speed regardless of the data rate of the digital input signal. For this reason, the calculation means can perform a convolution calculation by performing a constant operation regardless of the mode of the digital input signal.
According to the fourth aspect of the present invention, the digital input signal having a constant data rate regardless of the mode in the digital filter is increased to a data rate output to a subsequent device such as an amplifier in the conventional configuration. Can do.

Hereinafter, an embodiment according to the present invention will be described with reference to the drawings.
(theory)
Prior to the description of the embodiments of the present invention, the theory of the present invention will be described below.
The D / A converter of the present invention employs an FIR filter. The FIR filter performs a convolution operation on the digital input signals x ₁ , x ₂ ,... X _n and the filter coefficients (h ₁ , h ₂ ,... H _n ),
The result of the operation is output as a digital output signal yj. The convolution operation is expressed by the following equation (1). Note that n in equation (1) is the number of filter coefficients. The number of digital input signal values multiplied by the filter coefficient is hereinafter referred to as the tap number.
n
yj = Σ h _i · x _−i Equation (1)
i = 1

Here, the relationship between the sampling frequency of the FIR filter and the number of taps will be described.
1A to 1F show the sampling frequency of the digital input signal and the filter characteristics of the digital filter corresponding to the sampling frequency. The data rate of the digital input signal is determined by the sampling frequency. For this reason, in this specification, the terms “sampling frequency” and “data rate” are properly used, but both indicate the same numerical value.

FIGS. 1A and 1B show standard-speed digital input signals and filter characteristics. FIGS. 1C and 1D show double-speed digital input signals and filter characteristics, and FIGS. 1E and 1F show quad-speed digital input signals and filter characteristics. 1A to 1F, the vertical axis represents the gain of the input or output digital signal, and the horizontal axis represents the data rate (sampling frequency fs in the figure).
FIG. 2 is a diagram for explaining an output signal sequence (impulse response) of a digital filter corresponding to standard speed, double speed, and quadruple speed, respectively. The impulse response shown in FIG. 2 is for a D / A converter designed to satisfy the specifications shown in Table 2 below.

  FIG. 2A shows an impulse response corresponding to a standard-speed digital input signal. 2B shows an impulse response corresponding to a double-speed digital input signal, and FIG. 2C shows an impulse response corresponding to a quadruple-speed digital input signal. 2 (a) to 2 (c), the vertical axis represents gain, the horizontal axis represents period, TN represents a standard speed period, TD represents a double speed period, and TQ represents a quadruple speed period. ing.

In FIGS. 2A to 2C, the number of dots d forming a curve indicating an impulse response corresponds to the number of taps. However, the type of digital filter and the number of taps are determined by the stop band attenuation of the digital filter.
When the digital input signal is a standard speed, as shown in Table 1, the number of taps of the digital output signal shown in FIG. 2A is 511. In addition, when the digital input signal is double speed, the operation speed of the D / A converter of this embodiment does not change. Therefore, the double speed digital input signal is sampled every other standard speed digital input signal. Become a thing. For this reason, the number of taps at double speed is half of the number of taps at standard speed. The double speed cycle TD is (1/2) TD.

Further, when the digital input signal is 4 × speed, the 4 × speed digital input signal is obtained by sampling every 3 standard speed digital input signals, and the 4 × speed tap count is the standard speed tap count. It becomes 1/4 of. The quadruple speed cycle TQ is (1/4) TD.
From the above, the inventors of the present invention have a filter coefficient necessary for processing a standard speed digital signal when the digital filter processes a double speed or quadruple speed digital signal without changing the operation speed. Note that the digital input signal is multiplied every other or every third. Then, only one set of filter systems necessary for processing the standard-speed digital input signal is held in the memory, and only necessary filter coefficients are read out appropriately corresponding to the sampling frequency of the digital input signal.

  According to the present invention, since the digital filter is operated at a constant speed regardless of the data rate, a plurality of types of digital input signals having different sampling frequencies can be processed using one digital filter. For this reason, it is possible to configure a D / A converter that is simpler to control than the D / A converter provided with a plurality of stages of digital filters cited as the prior art and requires less man-hours for designing. In addition, since it is not necessary to have a plurality of types of memories, the area is reduced.

(D / A converter circuit configuration)
FIG. 3 is a block diagram for explaining the D / A converter of the present embodiment. The illustrated D / A converter 301 receives a digital input signal Din classified into one of a plurality of modes according to a data rate, and performs a digital operation for convolving a plurality of filter coefficients with the digital input signal. Has a filter.
The D / A converter of this embodiment is built in, for example, an audio amplifier. A data interface (data I / F) 302 for inputting a digital audio signal output from the audio player and processed by a DSP (Digital Signal Processor) (not shown) is provided. The digital input signal Din referred to in the present embodiment is digital data rounded by the DSP.

The data I / F 302 receives the digital input signal Din and first outputs it to the FIR filter 304. The D / A converter 301 includes an FIR filter 304, a sample and hold circuit 305, a delta-sigma modulator 306, and an SCF 307 (Switched Capacitor Filter). The FIR filter 304 corresponds to the digital filter of this embodiment.
The FIR filter 304 detects the mode of the digital input signal Din based on information included in the digital input signal Din. The mode detection in the FIR filter 304 is performed by a mode detection counter described later.

  The mode is a parameter determined by a sampling frequency at the time of recording digital data output from the audio player. In the present embodiment, the digital input signal can take three modes, and the three modes are a standard mode, a double speed mode, and a quadruple speed mode, respectively. The standard mode refers to an operation mode of the D / A converter corresponding to the digital input signal Din whose sampling frequency 1fs is 30 to 54 kHz or the digital input signal Din whose 1fs is 30 to 54 kHz.

The double speed mode is an operation mode of the D / A converter corresponding to a digital input signal Din in which 1fs is 54 to 108 kHz or a digital input signal Din in which 1fs is 54 to 108 kHz. Further, the quadruple speed mode refers to an operation mode of the D / A converter corresponding to a digital input signal Din in which 1fs is 108 to 216 kHz or a digital input signal Din in which 1fs is 108 to 216 kHz.
When it is detected that the digital input signal is in the n-times speed mode or when it is detected that the digital input signal is in the n-times speed mode by manual setting from the outside, the FIR filter 304 is 1 / n times that in the standard speed mode. By convolving the digital input signal with the rate, the digital input signal is set to a constant data rate regardless of the mode. Note that n is a natural number.

Specifically, the FIR filter 304 performs a convolution operation on the digital input signal Din in the standard speed mode at a rate of 8 times, and sets the data rate of the digital input signal that was 1 fs at the time of input to 8 fs. Further, when the digital input signal Din is in the double speed mode, the digital input signal Din is convolved at a rate of 4 times to set the data rate to 4 fs. Further, the digital input signal Din in the quadruple speed mode is convolved at a double rate to set the data rate to 2 fs. As a result, when the data is input to the FIR at the data rate of the digital input signal Din in Table 1, the frequency is constant at 384 kHz regardless of the sampling frequency (mode).
The change in the frequency of the digital input signal in the D / A converter of this embodiment is as shown in Table 3.

  Further, the FIR filter 304 outputs the result of the convolution operation of the digital input signal Din to the sample & hold circuit 305 as a digital output signal Dout. The sample and hold circuit 305 increases the data rate of the digital input signal Din that has been subjected to the arithmetic processing by a predetermined magnification regardless of the mode, and outputs it to the delta-sigma modulator 306. In the present embodiment, the predetermined magnification is 16 times.

When the sample and hold circuit 305 makes the result of the convolution calculation 16 times regardless of the mode, the data rate of the digital output signal Dout becomes 6.144 MHz regardless of the mode. For this reason, in the present embodiment, the data rate of the digital output signal output to a subsequent device such as an amplifier can be set to a value similar to that of the prior art. Therefore, the present invention can be applied to a D / A converter without changing the specifications of the subsequent device.
The signal processed in the delta sigma modulator 306 is output from the D / A converter 301 as an analog output signal Aout through an SCF (Switched Capacitor Filter).

(Digital filter)
FIG. 4 is a diagram for explaining a circuit configuration of the FIR filter 304 shown in FIG. The illustrated configuration includes the data I / F 302 and the sample and hold circuit 305 shown in FIG. 3 in addition to the FIR filter 304. A bit clock BICK (Bit Clock), a master clock MCLK (master Clock), and a sampling clock LRCK (Left Right ClocK) are input to the data I / F 302. With such a system clock, the data I / F 302 synchronizes the digital input signal Din and the operation of the D / A converter 301.

The FIR filter 304 includes a mode detection counter 402, a memory 409, a multiplier 408, an accumulator 403 including a calculation unit 404 and a storage unit 405, and a mode selector 407.
The mode detection counter 402 receives the master clock MCLK and the sampling clock LRCK. The mode detection counter 402 counts the data rate of the digital input signal Din using the system clock, and determines whether the digital input signal Din is classified into the standard speed mode, the double speed mode, or the quadruple speed mode. Alternatively, each mode can be selected manually from outside. Then, a signal indicating the determination result is output to the storage unit 405. Note that a signal indicating the result of determination is hereinafter referred to as a mode determination signal.

The memory 409 stores 512 filter coefficients necessary for the convolution calculation in the standard speed mode among a plurality of modes such as standard speed and double speed. The standard speed mode is the mode with the largest number of taps among the modes. In the memory 409, the filter coefficient is stored at an address corresponding to the order in which the filter coefficient is multiplied with the digital input signal Din.
The memory 409 is provided with an X (row direction) selector 409a and a Y (column direction) selector 409b. Each element included in the X selector 409a is connected to a row of addresses that are continuous in the X direction of the memory 409, and each element included in the Y selector 409b is connected to a row of elements that are continuous in the Y direction of the memory 409. Yes. Any element in the memory 409 can be turned on / off by a combination of turning on / off the elements included in the X selector 409a and the Y selector 409b.

FIG. 5 is a diagram for explaining the relationship between the elements included in the memory 409 and the X selector 409a and the Y selector 409b. A plurality of elements included in the memory 409 are all referred to as an element 501. In this embodiment, it is assumed that each element 501 corresponds to one address and stores one filter coefficient. The X selector 409a and the Y selector 409b include an element group including a plurality of elements arranged in a line. Each element included in the X selector 409a is referred to as an element 502a, and each element included in the Y selector 409b is referred to as an element 502b.

In this embodiment, for example, all the elements 502a are always turned on, and the element 502b is turned on according to the address of the element 501 to be turned on.
The X selector 409a and the Y selector 409b receive the mode determination signal from the mode detection counter 402 and determine the mode of the digital input signal. When the determination result is the standard mode, all of the elements 501 in the memory 409 are sequentially read and output to the multiplier 408.

In the present embodiment, when the digital input signal Din is in the double speed mode or the quadruple speed mode in which the number of taps is smaller than that in the standard mode, the filter coefficient is fixed by reading the filter coefficient at a constant address in the memory 409. Are read out at intervals of.
That is, when the determination result is the double speed mode, every other address of the element 501 of the memory 409 is sequentially read and output to the multiplier 408. As a result, among the elements 501 in FIG. 5, the filter coefficient is read from the address of the element 501 marked with ◯ and ◎ and sent to the multiplier 408. Further, when the determination result is the quadruple speed mode, every third address in the element 501 of the memory 409 is sequentially read and output to the multiplier 408. As a result, among the elements 501 in FIG. 5, the filter coefficient is read from the address of the element 501 marked with ◎ and sent to the multiplier.

It can be said that the X selector 409a and the Y selector 409b read out the filter coefficients used for the convolution calculation according to the mode of the digital input signal from the filter coefficients stored in the memory 409.
The multiplier 408 sequentially multiplies the filter coefficient read from the memory 409 by the digital input signal Din read from the RAM 401. The RAM 401 is a configuration for temporarily storing the digital input signal Din input via the data I / F 302 and outputting it at an appropriate timing. A signal indicating the multiplication value by the multiplier is sent to the accumulator 403.

  The accumulator 403 includes a computing unit 404 and a storage unit 405. The arithmetic unit 404 sequentially adds the multiplication values output from the multiplier 408. The added value is accumulated in the accumulation unit 405. The accumulation unit 405 receives the mode determination signal output from the mode detection counter 402. Then, the mode of the digital input signal Din is determined from the mode determination signal, and the accumulated value is reset every time the addition value for the filter coefficient corresponding to the mode is accumulated.

The mode selector 407 receives the mode determination signal and determines the mode of the digital input signal to be processed. Then, the addition value is extracted from the accumulation unit 405 at the timing when the addition value for the number of taps corresponding to the mode is accumulated, and is output to the sample and hold circuit 305.
In the configuration described above, the digital filter of the D / A converter of this embodiment corresponds to the FIR filter 304. The memory 409 corresponds to a storage device, the mode detection counter 402 corresponds to mode detection means, the X selector 409a and Y selector 409b correspond to reading means, and the multiplier 408 and accumulator 403 correspond to calculation means.

According to the present embodiment described above, since one FIR filter can be used to cope with digital input signals of a plurality of modes having different data rates, control is simpler than controlling a plurality of FIR filters. A D / A converter can be provided.
In addition, a conventional D / A converter using three FIR filters generates control signals so that FIR1 to FIR3 can be calculated in 1 fs in order to reduce the time required for the calculation. However, if only one FIR is used as in the present embodiment, the control signal can be simplified, and the number of steps for designing the FIR filter can be reduced.

Further, since a minimum filter coefficient is stored in a memory and the filter coefficient is thinned out corresponding to a digital input signal, the memory can be reduced in size, and a D / A converter suitable for element downsizing is provided. Can do.
The D / A converter of the present invention is not limited to the embodiment described above. For example, the specific values of the sampling frequency, the double speed, the quadruple speed, and the number of taps described in the present embodiment are not limited to the present embodiment, and needless to say, are determined as appropriate. Furthermore, the FIR filter used for the D / A converter of this embodiment can also be applied to the A / D converter.

It is the figure which showed the filter characteristic of the digital filter corresponding to the sampling frequency of the digital input signal of the D / A converter of this invention, and a sampling frequency. It is a figure for demonstrating the impulse response of the D / A converter of this invention. It is a block diagram for demonstrating the D / A converter of one Embodiment of this invention. It is a figure for demonstrating the circuit structure of the FIR filter shown in FIG. FIG. 5 is a diagram for explaining a relationship among elements included in the memory illustrated in FIG. 4, an X selector, and an X selector. It is the figure which illustrated the conventional D / A converter 5 provided with a some digital filter.

Explanation of symbols

301 D / A converter 302 Data I / F
304 FIR Filter 305 Sample & Hold Circuit 306 Delta Sigma Modulator 307 SCF (Switched Capacitor Filter)
402 mode detection counter 403 accumulator 404 arithmetic unit 405 storage unit 407 mode selector 408 multiplier 409 memory 409a X selector 409b Y selector 501 502a 502b element

Claims (4)

A D / A converter including a digital filter that inputs a digital input signal classified into one of a plurality of modes according to a data rate and sequentially multiplies the digital input signal by a plurality of filter coefficients,
The digital filter is
A storage device for storing a plurality of the filter coefficients;
Mode detection means for detecting the mode of the digital input signal;
Reading means for reading filter coefficients from the storage device in accordance with the mode detected by the mode detecting means;
An arithmetic means for performing a convolution operation at a constant operation speed regardless of the mode of the digital input signal, using the filter coefficient read by the reading means and the digital input signal;
With
The storage device stores filter coefficients necessary for a mode in which a digital input signal is multiplied by the largest number of filter coefficients among the plurality of modes, and the reading unit stores the filter coefficients stored in the storage device. A D / A converter characterized in that the filter coefficient used for the convolution calculation is read out in accordance with the mode of the digital input signal.   The storage device stores the filter coefficient at an address corresponding to the order of multiplication with the digital input signal, and the reading means reads out the filter coefficient at fixed intervals by reading out the filter coefficient at a fixed address. The D / A converter according to claim 1. The plurality of modes include a standard speed mode having a predetermined data rate, and an n-times speed mode in which the data rate is n times the data rate of the standard speed mode,
When the mode detection means detects that the digital input signal is in the n-times speed mode, the calculation means performs a digital operation by convolving the digital input signal at a rate 1 / n times that in the standard speed mode. 3. The D / A converter according to claim 1, wherein the input signal has a constant data rate regardless of the mode. A sample-and-hold circuit is provided after the digital filter,
The sample-and-hold circuit, D / A converter according to any one of claims 1 to 3, characterized in that to increase the data rate of the digital input signal regardless of the mode at a predetermined magnification.

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