JPH07212233A - D/a conversion device with digital filter - Google Patents

Abstract

PURPOSE:To reduce the level of a noise mixed from the digital filter part of the D/A conversion device with monolythic digital filter to an analog part. CONSTITUTION:This device is provided with a converting means 2 for converting an inputted digital signal based on fixed rules, RAM 3 for storing the output of the converter, ROM 7 for storing a filter coefficient, inverse converting means for returning the data read from the RAM 3 to its original value, digital filter equipped with a multiplier 6 and an accumulator 10 for convolving the data successively read from the RAM 3 with the filter coefficient through the inverse converting means 4, and D/A converter 12 for converting the digital filter output to an analog value, the data written in the RAM 3 are made random and especially when a fine signal is inputted, the change of a current amount to flow to the RAM 3 is suppressed at a minimum.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a D / A converter,
In particular, it is suitable for a monolithic LSI with a digital filter.

[0002]

2. Description of the Related Art With recent advances in digital signal processing technology, the importance of D / A conversion technology, which is an interface between a digital signal and an analog signal, is increasing. In particular, recently, there is also one in which D / A conversion is performed by using oversampling which is higher than the required sampling frequency fs, for example, 4 times or 8 times.

A conventional D / A converter with a digital filter is shown in FIG. 7 and will be described. Reference numeral 1 denotes an interface, which takes in a digital input given from the outside and outputs it at a predetermined timing. Reference numeral 3 is a writable storage means (hereinafter referred to as RAM), which stores and stores digital data given from the interface 1. Reference numeral 7 denotes a storage means (hereinafter referred to as a coefficient ROM) that stores the coefficients of the digital filter. A multiplier 6 multiplies the data given to the terminals A and B and outputs the result from the terminal C. Reference numerals 5, 8, 9, and 11 are flip-flops. An accumulator 10 accumulates input data. A D / A converter 12 performs D / A conversion of input digital data.

Next, the operation of the circuit shown in FIG. 7 will be described. Digital inputs provided to the interface 1 are sequentially stored in the RAM 3. The RAM 3 sequentially reads past digital inputs already stored, and the coefficient ROM 7 reads the corresponding filter coefficient. These data are synchronized in time by the flip-flops 5 and 8 and given to the multiplier 6. The multiplier 6 multiplies these values and the time is adjusted by the flip-flop 9 before being sent to the accumulator 10. In this way, the digital input and the filter coefficient are convolved to be oversampled, and the result is flip-flop 1
After being written to 1, it is given to the D / A converter 12, converted into an analog signal and output.

[0005]

However, in the above configuration, for example, when a minute digital input (that is, data that changes only about 1 to 2 digits around zero) is entered, it is convolved. To R
The bit pattern of the data read from AM3 changes between all 0's and all 1's. In general, the amount of current consumed by the RAM greatly differs depending on whether each bit outputs 0 or 1, and thus when the number of bits outputting 0 and the number of bits outputting 1 change greatly,
There has been a problem that the amount of current consumed by the RAM greatly changes, and this change in the amount of current affects the analog circuit and deteriorates performance.

In view of the above problems, it is an object of the present invention to provide a D / A converter which has a small performance deterioration even when a minute digital signal is input.

[0007]

In order to achieve this object, a D / A converter with a digital filter according to the present invention comprises a converting means for converting an input digital signal, and a first storing means for storing the output of the converting means. The first storage means, the second storage means that stores the filter coefficient, the inverse conversion means that performs the inverse conversion of the data read from the first storage means, and the data sequentially read from the first storage means. While performing inverse transformation by the inverse transformation means, a digital filter provided with multiplication means for performing multiplication with the filter coefficient, accumulating means for accumulating the output of the multiplication means, and D / A conversion of the output of the digital filter. And D / A conversion means.

[0008]

As described above, since the data input to the first storage means (RAM) is converted according to a certain law, even if a minute digital input is given, 0 is output in the RAM output. Since the number of bits to be output and the number of bits to output 1 do not change so much, the amount of current consumed by the RAM does not change so much and performance deterioration can be suppressed.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

FIG. 1 shows a D / A converter with a digital filter according to the present invention. Reference numeral 2 is a conversion means, which converts the input data into another value based on a certain law. Reference numeral 4 denotes an inverse conversion means, which returns the data converted by the conversion means 2 to the original value. In addition, in this figure, those having the same functions as those in FIG.

Next, the operation of the apparatus shown in FIG. 1 will be described. The digital input given to the interface (I / O) 1 is converted into another value by the conversion means 2 and then stored in the RAM 3 sequentially. The RAM 3 sequentially reads past digital inputs already stored, and the coefficient ROM 7 reads the corresponding filter coefficient. RAM
The data read from 3 is returned to the original value by the inverse conversion means 4, and these data are flip-flops 5, 8
The time is adjusted by and is given to the multiplier 6. The multiplier 6 multiplies these values and the time is adjusted by the flip-flop 9 before being sent to the accumulator 10. In this way, the digital input and the filter coefficient are convolved and oversampled, and the result is written in the flip-flop 11 and then applied to the D / A converter 12, converted into an analog signal and output. It

Considering the case where a minute digital input is given, the data input to the RAM 3 is converted by the conversion means 2 according to a certain law, so that, for example, all 0, all 1 (this is − Even when a digital input consisting of only values (meaning 1) is given, the value actually written in RAM3 is a value in which 0 and 1 are mixed appropriately, and 0 is output at RAM3 output. The number of bits to be output and the number of bits to output 1 do not change so much. Therefore, the amount of current consumed by the RAM 3 does not change so much, and performance deterioration during D / A conversion can be suppressed.

FIG. 2 shows a concrete example of the conversion means 2 and the inverse conversion means 4 in FIG. In this figure, 2
Reference numerals 1-28 are inverters, and reference numerals 29-35 are tristate gates. Here, the case where the RAM 3 has 16 bits is shown. In the conversion means 2, the inverters 21-2
4, the even-numbered input bits of the RAM 3 are inverted, and the inverse conversion means 4 inverts the bits again. Therefore, the input and the output are macroscopically the same. But actually RAM
The value written in 3 is 555 when input = 0, for example.
It is 5H, and when the input is −1, it becomes AAAAH. Therefore, for example, even when minute digital inputs such as 0 and −1 are alternately applied, the number of “1” s in the data output from the RAM 3 is 8 and the difference between them is 0, which is 16 in the conventional case. Considering that it was significantly smaller. Therefore, the amount of current consumed by the RAM 3 does not change so much, and performance deterioration during D / A conversion can be suppressed.

FIG. 3 shows another specific example of the converting means 2 and the inverse converting means 4 in FIG. In this figure, 49 is an address generator, which generates an address signal for the RAM 3. Reference numerals 40 to 45 are exclusive OR gates (hereinafter, referred to as EOR gates), which are input by using the bit most frequently changing in the address signal output from the address generator 49, here, the least significant bit (LSB). The control is performed to pass / invert the signal to be transmitted. 29-
31 is a tri-state gate. In this example,
The LSB of the address signal is used to perform an exclusive OR with the input data so that the inverted value is written in the even address of the RAM 3 and the unchanged data is written in the odd address of the RAM 3. In this example,
For example, considering the case where a minute digital input such as 0 or -1, is given, the data read during the convolution alternates between inversion and through depending on the address signal. Change at high speed. Therefore, although the amount of current consumed by the RAM 3 changes greatly, the change is fast and the influence on the audible band is small, so that the performance deterioration during D / A conversion can be suppressed.

FIG. 4 shows another specific example of the conversion means 2 and the inverse conversion means 4 in FIG. In this figure, reference numeral 50 denotes a Gray code converter, which is composed of EOR gates 55 to 58 as shown in FIG. 5, and converts an input normal binary number into a Gray code. 51
Is a Gray code demodulator, and as shown in FIG.
It is configured by R gates 61 to 64, and the input Gray code is returned to the original binary number. 52 is a tri-state gate. In this way, macroscopically the input and output are made equal.

Gray code means 0, 1, 2, 3, 4,
.., in the case of 4 bits,
It is a code such that the number of changing bits is always 1 in continuous numerical values such as 0011, 0010, 0110, .... Therefore, for example, even when minute digital inputs such as 0 and −1 are alternately applied, 0 is 0000H and −1 is 8000H and the RAM 3
The number of "1" s in the data output from the RAM3 is 0 when it is 0 and 1 when it is -1, and the difference between them is 1 and is 16 compared with the conventional case. Will be significantly smaller. Therefore, the amount of current consumed by the RAM 3 does not change so much, and performance deterioration during D / A conversion can be suppressed.

In FIG. 2, even number bits are inverted by the conversion means 2, but the present invention is not limited to this. In short, when a minute input such as 0 or -1 continues, "1" is output.
It is enough if the number of does not change so much.

[0018]

As described above, according to the present invention, the input digital signal is once converted and stored in the RAM.
Since the data read out is inversely converted again, the amount of current consumed by the RAM does not change so much, and the performance deterioration that occurs through the power supply or the substrate in the case of a monolithic LSI is greatly suppressed. It has an excellent effect of being able to.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a D / A converter with a digital filter according to the present invention.

2 is a block diagram showing a first specific example of a conversion unit 2 and an inverse conversion unit 4 for converting input data of a RAM 3 in FIG.

FIG. 3 is a block diagram showing a second specific example of a conversion unit 2 and an inverse conversion unit 4 for converting the input data of the RAM 3 in FIG.

FIG. 4 is a block diagram showing a third specific example of conversion means 2 and inverse conversion means 4 for converting input data of RAM 3 in FIG.

FIG. 5 is a circuit diagram showing a specific example of a Gray code converter for converting a binary number into a Gray code.

FIG. 6 is a circuit diagram showing a specific example of a Gray code inverse converter that converts a Gray code into a binary number.

FIG. 7 is a block diagram showing a conventional D / A converter with a digital filter.

[Explanation of symbols]

 1 interface 2 conversion means 3 RAM 4 inverse conversion means 6 multiplier 7 coefficient ROM 10 accumulator 12 D / A converter

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Hideaki Hatanaka 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd.

Claims (4)

[Claims] 1. A conversion means for converting an input digital signal, a first storage means for storing an output of the conversion means, a second storage means for storing a filter coefficient, and the first storage means. Inverse conversion means for performing inverse conversion of the data read from the storage means, and the filter read from the second storage means while inversely converting the data sequentially read from the first storage means by the inverse conversion means. A digital filter having a multiplication means for multiplying with a coefficient, an accumulation means for accumulating the output of the multiplication means, and a D / A for D / A converting the output of the digital filter.
A D / A conversion device with a digital filter, comprising a conversion means. 2. The conversion means inverts the value of a specific bit of an input digital signal, and the inverse conversion means inverts the value of the inverted bit again.
The D / A converter with the digital filter described. 3. The digital filter comprises address generating means for generating an address signal for the first storage means, the converting means inverts the input digital signal on the basis of the address signal, and the inverse converting means means for inverting the digital signal. 2. The D / A conversion device with a digital filter according to claim 1, wherein the value of the data inputted based on the address signal is inverted again. 4. The D / with digital filter according to claim 1, wherein the conversion means converts an input digital signal into a gray code, and the inverse conversion means converts the gray code into a normal binary number. A converter.