JPS6022544B2 - Signal control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention receives an AC signal digitally generated in the form of a serial binary signal and sends the AC signal to the output terminal when the control signal applied to the control terminal is at a first level. second worldly
The present invention relates to a signal control method that controls the signal to be transmitted when the AC signal is at the level of , and particularly to a signal control method that reduces the spread of the frequency spectrum that occurs when starting or stopping the transmission of the AC signal.

Generally, when transmitting and receiving AC signals through a line, if the AC signal is suddenly turned on or off on the transmitting side, the frequency spectrum may spread at the time when the transmission of the AC signal is started or stopped, which may adversely affect the receiving side. In many cases, it has been necessary to perform some kind of signal processing to reduce such frequency spectrum spread.

Conventionally, this type of signal processing is performed using an analog signal processing system, for example, as shown in FIG. Normally, this was done using a grounding circuit. below,
A conventional signal control method that reduces the spread of the frequency spectrum shown in FIG. 1 will be described. In FIG. 1, 101 is an input terminal for an AC signal, 102 is a control terminal into which a control signal for turning on and off the AC signal is input, 1
03 is a function generator, 104 is an amplifier, and 105 is an output terminal for an AC signal.

In the system shown in FIG. 1, a function generator 103 generates a signal like an exponential function using a control signal from 102, and this signal continuously changes the gain of an amplifier 104, so that the alternating current signal from 101 suddenly changes. This prevents the AC signal from turning on and off, and prevents the spread of the frequency spectrum that occurs when starting or stopping sending an AC signal to the output terminal 105. However, this method has nonlinear characteristics in addition to the diodes and transistors normally used to change the gain of the amplifier 104, and the function generator 10
There was a drawback that it was difficult to obtain desired on/off waveforms by combining with 3.

Furthermore, when turning on and off a digital signal, a D/A converter is required in addition to the analog circuit described above, which has the disadvantage of complicating the circuit configuration. SUMMARY OF THE INVENTION An object of the present invention is to provide a signal control system having a novel configuration capable of eliminating the above-mentioned drawbacks and causing less spread of the frequency spectrum when transmitting or stopping a signal. The present invention focuses on the fact that the above-mentioned drawbacks are caused by the analog processing method.

That is, the present invention eliminates the above-mentioned drawbacks by providing a novel configuration that digitally processes the on/off state of the AC signal and also digitally processes the reduction of the spread of the frequency spectrum. Next, embodiments of the present invention will be described with reference to the drawings.

Referring to FIG. 2, a basic configuration of an embodiment of the present invention is shown. In this embodiment, the input terminal 201 receives an AC signal that is digitally generated in the form of a serial binary signal. In this embodiment, when the control signal applied to the control terminal 102 is "0", the AC signal input to the input terminal 201 is not sent to the output terminal 202, but when the other level is "1", it is sent. to control. It is assumed that n bits corresponding to one unit of an AC signal are input in series to the input terminal 201. Reference numeral 203 denotes an n-bit shift register having a number of bits corresponding to one unit of the AC signal.

In addition, 204 combines a first operation and a second operation, which will be described later.
This is a control circuit that repeats as a cycle. As a first operation, the control circuit 204 leads 201 AC signals to the input terminal s of the shift register 203, and applies n clocks to the clock terminal CL of the shift register 203, so that the shift register 203 receives one unit of the AC signal ( n bits). In the second operation following this first operation, the input of the AC signal from 201 to the input terminal s of the shift register 203 is cut off, and the clock terminal cl of the shift register 203 is set based on the control signal of the control terminal 102. Give the number of clocks and shift registers 20 for that number
3, an operation is performed to shift the contents read in the first operation. Reference numeral 205 is an n-bit storage circuit that outputs the contents of the shift register 203 in response to the second operation to the output terminal 202 each time the control circuit 204 performs the second operation.

When the control signal 102 is constantly "0" or "1", the control circuit 204 is in a steady setting state in which the number of clocks given to the shift register 203 is unified to n or 0 in each second operation period. It is designed to take

Furthermore, when the level of the control signal 102 changes, the control circuit 204 enters the steady setting state through a transient setting state in which a number of clocks between the n clocks and the zero clocks are applied to the shift register 203 during the second operation period. It is becoming more and more like this. The AC binary signal from the input terminal 201 is read into the shift register 203 one unit (n bits) each time the control circuit 204 performs the first operation.
If the control signal given to the memory circuit 205 is constantly "0", it will be cleared every time the control circuit 204 performs the second operation. No signal is sent.

Conversely, if the control signal applied to the control terminal 102 is constantly "1", the shift register 203 is
Since one unit (n bits) of the AC binary signal read in is not cleared by the second operation, one unit of the AC binary signal is output to the output terminal 202 each time the second operation is performed. (
n bits) at a time. Further, when the level of the control signal applied to the control terminal 102 changes, one unit (n bits) of the AC binary signal read into the shift register 203 in the first operation is transferred to the control circuit in the second operation. 2
Since the AC binary signal is shifted by the set number of clocks due to the excessive setting state of 04, the phenomenon in which the AC binary signal is suddenly turned on and off at the output device 202 does not occur, and the level of the AC signal obtained at the output terminal 202 is gradually changed. Changes to Therefore, it is possible to reduce the spread of the frequency spectrum that occurs when transmission of an AC signal is started or stopped. The basic structure of one embodiment of the present invention has been explained above, and next, the specific structure of this embodiment will be explained with reference to FIGS. 3 and 4. Figure 3 shows the specific configuration of Figure 2, and Figure 4 shows the configuration of Figure 3.
A time chart of waveforms in each part of the figure is shown. Note that FIGS. 3 and 4 show the case where one unit of the AC signal is 7 bits. In FIG. 3, an AC binary signal is input to an input terminal 201 in order from the LSB (0th bit).

The MSB (sixth bit) is a sign bit, and negative numbers are input in two's complement form. Note that the sign bit is set to 1 if it is a negative number and 0 in other cases. The control signal shown as F in FIG. 4 is input to the control terminal 102, and as described above, when the control signal is "0", the AC signal input to the input terminal 201 is not sent to the output terminal 202. , the signal in FIG. 3 is operated to transmit when the signal is at a high level "1".
The shift register 203 is a 7-bit shift register with serial input and parallel output functions. This shift register 20
3 reads data one bit at a time from the input terminal s every time a clock pulse is input to the clock terminal cl, shifts it to the right, and outputs it to the output terminals a to g. Terminals 301 and 302 of the control circuit 204 are connected to terminals E in FIG. 4, respectively. A signal indicated as D is input. The signal ○ applied to the terminal 302 is a signal for determining the operation of the control circuit 204. When this signal is "1", the control circuit 204 performs the above-mentioned first operation, and when it is "0", the control circuit 204 performs the above-mentioned first operation. Perform step 2.
A signal E applied to the terminal 301 is a signal for storing the sign bit of the AC signal input to the input terminal 201 in the ○ flip-flop 311. Further, the basic clock pulse shown in FIG. 4A is inputted to the terminal 303 of the control circuit 204. As is clear from FIGS. 4A and 4D, seven clock pulses are generated while the D signal of 302 is "1", and seven clock pulses are generated while it is "0". ing. First, the operation of the control circuit 204 when the signal applied to the terminal 302 is logic "1" (ie, the first operation) will be described.

During this period, the binary signal changes from state 201 to AND gate 3.
12, shift register 203 via OR gate 313
input terminal s, while seven clock pulses,
From terminal 303 to AND gate 314 and OR gate 315
is led to the clock terminal cl of the shift register 203 via the clock terminal cl of the shift register 203. In this way, when the signal applied to the terminal 302 is "1", the control circuit 204 applies seven clock pulses to the clock terminal cl from the pattern 303 to cause the shift register 203 to read a 7-bit binary signal. do. Next, the operation of the control circuit 204 when the signal applied to the terminal 302 is logic "0" (ie, the second operation) will be described.

During this period, the input of the binary signal to the input terminal s of the shift register 203 is cut off by the AND gate 312, and the clock terminal cl of the shift register 203 is connected to the control terminal 10.
A set number of clock pulses based on the second control signal are applied from the output of the AND gate 316 via an AND gate 318 opened by an inverter 317 and an OR gate 315. Therefore, the shift register 203 shifts the internal data to the right by the number of clock pulses input to the clock terminal cl, and the sign bit stored in the flip-flop 311 is read from the input terminal s via an AND gate 319 and an OR gate 313. It goes down. In this way, when the signal applied to the terminal 302 is "0", the control circuit 204 applies a set number of clock pulses to the clock terminal tl based on the control signal of the terminal 102, and the shift register 203 receives the clock pulses by that number. It performs an operation to shift the data read in the first operation. The contents of the shift register 203 change approximately 1/2, 1/4, and 1 of the initial value each time a clock pulse is input to the clock terminal cl.
/8,... The function of setting the number of clock pulses to be applied to the output side of AND gate 316 based on the control signal shown in figure 102 will be described below. This clock number setting function is performed by AND gates 316, 320, 321, 3
22, inverters 323, 324, and NAND gate 3
25, exclusive OR circuit 326, and OR gate 327
and a 6-bit shift register 328.

A signal having the waveform shown in FIG. 4B is applied to the terminal 304 for controlling level changes when the AC signal is turned on and off. Further, a signal having a waveform shown in FIG. 4C, which becomes "0" every seventh basic clock pulse of the terminal 303, is applied to the terminal 305. Now, if the control signal given to the control terminal 102 is constantly "0", then the output of the AND gate 321 is always "0".The output of the inverter 323 is 1, so the output of the AND gate 320 is terminal 3
Every time the B signal from 04 becomes “0”, it becomes “0”,
The output signal of the AND gate 322 is read from the input terminal s of the shift register 328 and further shifted.

Eventually, everything inside the shift register 328 becomes "0", and "1" is output from the output terminal Q every time a clock pulse is input to the clock terminal °C1. AND gate 3 input to clock terminal cl of shift register 328
The waveform of the output signal of No. 22 is shown in FIG. 4G. Further, the waveform of the output signal of the band gate 316 is shown in FIG. Therefore, as is clear from the time chart in Figure 4,
When the control signal at the control terminal 102 is constantly "0", seven pulses are always given to the clock terminal cl of the shift register 203 each time the signal at the terminal 302 becomes "0".

This state is the first steady setting state of the control circuit 204. This causes the shift register 203 to shift from input terminal s to D.
Since the sign bit stored in the flip-flop 311 is read and shifted by 7 bits, the contents of the shift register 203 are all “0” or “1”.
”. In addition, in order to read and store the outputs a to g of the shift register 203 in parallel as the memory circuit 205,
D flip-flops 329-335 are used.
With the above operation, while the control signal input to the control terminal 102 is "0", the signals output to the output terminals 336 to 342 are off. Next, a case where the control signal input to the control terminal 102 becomes "1" will be described.

When the signal input to the terminal 304 is “1”, the output of the output terminal Q of the shift register 328 is output from the NAND gate 325.
Since the signal is inverted and input to the input terminal s of the shift register 328, the contents of the shift register 328 do not change. When the B signal input to the terminal 304 is “0”, the signal input to the input terminal s of the shift register 328 is “0”.
1”, and the contents of the shift register 328 are all “0”.
”, only one bit becomes “1”.Similarly, each time the signal input to the terminal 304' becomes “0”, the contents of the shift register 328 increase by “1”, and the output from Q The signal to be output gradually increases from "1" to "0". When the control signal at the control terminal 102 changes to "1", the signal at the terminal 302 changes by the above operation. Shift register 20 every time it becomes “0”
The number of clock pulses applied to the clock terminal cl of No. 3 gradually decreases from seven until it finally reaches zero.

That is, the control circuit 204 goes through a transient setting state in which it provides between seven and zero clock pulses, and then enters a second steady state setting in which it repeatedly provides zero clock pulses. Therefore, if the level of the binary signal input from the input terminal s of the shift register 203 is 1, then the output terminal 3
The level of the signal output to 36 to 342 is determined by the control terminal 10.
When the control signal input to the control terminal 102 was “0”, the value was 0, but the control signal input to the control terminal 102 was “0”.
When it reaches "1", it goes through a transient state that increases to 1/32, 1'16, and 1'8, and finally becomes 1.Next, from the above state, the control signal input to the control terminal 102 changes to "0". If the change occurs, "0" is read into the input terminal s of the shift register 328 every time "0" is input to the terminal 304, so as is clear from the time chart of FIG. When the input signal is "0", the number of clock pulses input to the clock terminal cl of the shift register 203 gradually increases from 0 to 7 in the end.

That is, the control circuit 204 goes from a second steady setting state in which 0 clocks are always provided, to a transient setting state in which a number of clocks between 0 and 7 is provided, and then to a first state in which 7 clocks are always provided. becomes the steady setting state. therefore,
The level of the AC binary signal outputted to the output terminal 202 decreases from 1 to 1/2, 1/4, . . . and finally reaches 0. As is clear from the above description, according to the present invention, the level of the AC signal is changed stepwise and turned on and off by digital processing based on the control signal, so that the AC signal is turned on and off. - It is possible to reduce the spread of the frequency spectrum when turning off.

In addition, since digital processing can be performed, the circuit configuration is simplified, which is a great advantage for integrated circuits.

[Brief explanation of drawings]

Figure 1 is a block diagram showing the conventional signal control system, Figure 2 is a block diagram showing the conventional signal control system.
The figure is a block diagram showing the principle configuration of an embodiment of the present invention, FIG. 3 is a circuit diagram showing the specific configuration of FIG. 2, and FIG. FIG. 102... Control terminal, 201... Input terminal, 202... Output terminal, 203...
Shift register, 204...Control circuit, 205
...Memory circuit. Figure 1 Figure 2 Figure 3 Figure 4

Claims (1)

[Claims] 1 An AC signal digitally generated in the form of a serial binary signal is input, and when the control signal given to the control terminal is at the first level, it is not sent to the output terminal, but when it is at the second level, it is not sent to the output terminal. In a signal control method for controlling transmission, a shift register having a number of bits corresponding to one unit of the alternating current signal is provided, the alternating current signal is guided to an input terminal of the shift register, and a clock terminal of the shift register is connected to the shift register. A first operation of applying the same number of clocks as the number of bits of the shift register to read one unit of the AC signal into the shift register, and a first operation of cutting off the input of the AC signal to the input terminal of the shift register and performing the shift. A second operation in which a set number of clocks is applied to the clock terminal of the register based on the control signal and the contents read in the first operation are shifted into the shift register by the number of clocks, and this is repeated as one cycle. and a storage circuit that outputs the contents of the shift register in response to the second operation to the output terminal each time the control circuit performs the second operation, and the control circuit is configured such that the control signal is constant. When the clock is at the first level or the second level, a steady setting state is established in which the number of clocks applied to the shift register is unified to the same number as the number of bits of the shift register or zero during each second operation period. Further, when the level of the control signal changes, the shift register undergoes a transient setting state in which a number between the same number of clocks and zero clocks is applied to the shift register during the second operation period, and then the steady setting state is reached. A signal control method characterized by: