JP3455584B2 - Partial product generation circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a partial product generation circuit that can be used in a multiplier, and more particularly to an improvement for reducing power consumption in a usage mode with a fixed multiplier.

[0002]

2. Description of the Related Art For a multiplier, which is a device for outputting a product of an input multiplier and a multiplicand, a mode of use is known in which the multiplier is fixed and only the multiplicand is changed appropriately for calculation. A typical example is a digital filter incorporating a multiplier. With the development of digital signal processing technology, digital filters have come to be widely used in place of analog filters in communication fields and consumer fields.

In the multiplier used for the digital filter, the coefficient of the digital filter serves as a multiplier and the input signal serves as a multiplicand. The coefficients are preset (loaded before operation) and are fixed during operation of the digital filter. Therefore, the multiplier of the multiplier is fixed during the operation of the digital filter.

The operation speed of the multiplier affects the processing speed of the digital filter. In order to speed up the multiplier, it is effective to reduce the number of partial products intermediately generated in the process of calculation, and Booth's algorithm is known as a typical calculation method. . Figure 9
FIG. 6 is a block diagram showing a configuration of a conventional multiplier that executes an operation according to this Booth's algorithm. This multiplier is a binary number m + 1 digit multiplicand X, that is, X _{0 to} X _m ,
A product of the binary number n + 1 digit multiplier Y, that is, Y _{0 to} Y _n is calculated and output. In this multiplier, according to Booth's algorithm, 3-bit multipliers Y _2i-1 , Y _2i , Y _{2i + 1}
Then, the products 0X, ± X, ± 2X of the multiplicand X are temporarily calculated as partial products, and the final products are calculated by adding these partial products.

In FIG. 9, reference numeral 100 is a Booth decoder for converting 3-bit multipliers Y _2i-1 , Y _2i , Y _{2i + 1} into 3-bit decoded signals C ₁ , C ₂ , C ₃ according to a certain rule. , 101 are converted decode signals C ₁ , C ₂ , C ₃
A partial product generation circuit that calculates and outputs a partial product based on
Reference numeral 2 is a partial product addition unit that calculates the product of the multiplier Y and the multiplicand X by adding the partial products.

FIG. 10 is a circuit diagram showing the internal structure of the Booth decoder 100. In FIG. 10, 46 and 47 are exclusive OR elements that output an exclusive OR of input signals (hereinafter abbreviated as EXOR), and 48, 49, and 51 are inverter elements that output inverted signals of the input signals (hereinafter abbreviated as EXOR). , I
NV is abbreviated), and 50 and 52 are turned on (conduction) or turned off (non-conduction) between input and output in response to a gate signal
A transmission gate element (hereinafter abbreviated as TG). Each element INV53, 58 other than TG,
The EXOR 56 and the NAND 57 are both configured with CMOS in order to reduce power consumption. Booth decoder 1
00 is configured in this way, so three input signals Y
_2i-1, Y _2i, in accordance with the Y _{2i + 1,} the three decoded signals _{C 1, C 2, C 3} , and outputs according to a conversion rule shown in FIG. 11.

FIG. 12 is a block diagram showing the internal structure of the partial product generation circuit 101. As shown in FIG. 12, one unit partial product generation circuit 103 is provided for each digit X _i (i = 0 to m) of the multiplicand X. Each unit partial product generating circuit 103 having the same internal configuration to each other, and one digit X _i, the lower digit X _i-1 one, and the decoded signal C
₁ , C ₂ , C ₃ have been input. Each unit partial product generation circuit 103 calculates and outputs one digit Z _i of the partial product Z based on these signals. Note that X _-1 is a signal whose value is fixed to 0.

FIG. 13 is a circuit diagram showing the internal structure of the unit partial product generating circuit 103. In FIG. 13, 53, 5
Reference numeral 8 is an INV, 54 and 55 are TGs, 56 is an EXOR, and 57 is an inverted logical product element (hereinafter abbreviated as NAND) that outputs an inverted signal of a logical product of two inputs. Since the unit partial product generation circuit 103 is configured in this way, the decoded signals C ₁ , C ₂ , and C ₃ function as follows. That is, the decode signal C ₁ functions as a shift signal for generating + X and + 2X, and the decode signal C ₂ is -X.
And -2X to function as an inversion signal. In addition, the decode signal C ₃ functions as an enable signal for generating 0X. As a result, the partial product generation circuit 101 having m + 1 unit partial product generation circuits 103 has 0X, ± X, and 0X, ± X, depending on the values of the decoded signals C ₁ , C ₂ , and C ₃ .
Output ± 2X as a partial product.

[0009]

By the way, as in the case of being used in a digital filter, the use of calculating the product of various multiplicands X inputted one after another while keeping the multiplier Y fixed to a constant value. In the mode, the shift signal C ₁ , the inverted signal C ₂ , and the enable signal C ₃ input to the unit partial product generation circuit 103 are maintained at constant values, and only the multiplicand X which is the other input signal changes. Among these,
When the enable signal C ₃ is fixed at 0, N
Since one input of the AND 57 is fixed to 0, the AND 57 outputs 1 to the INV 58 regardless of the other input signal. As a result, 0 is always obtained as the output Z _i of the partial product generation circuit.

At this time, especially when the shift signal C ₁ is 1, the TG 54 is turned on and the TG 55 is turned off, so that X _{i -1} is input to the EXOR 56. The output Z _i becomes 0 due to the enable signal C _3, but when the value of X _i-1 changes between 0 and 1, the through current (CMOS on the transition from ON to OFF and from OFF to ON) is passed to the EXOR 56. A power supply current that transiently flows in the element of the structure is generated, and a charging / discharging current (current that charges / discharges the capacitance parasitically present in the output terminal of the element) flows to the input terminals of the EXOR 56 and the NAND 57.

On the other hand, when the shift signal C ₁ is 0, the TG 54 is turned off and the TG 55 is turned on.
X _i is input to OR56. At this time, the output Z _i becomes 0 by the enable signal C _3, but when the value of X _i changes between 0 and 1, a through current is generated in the EXOR 56 and a charge / discharge current flows in the EXOR 56 and the NAND 57.

As described above, the conventional unit partial product generation circuit 1
In 03, since the value of the enable signal C ₃ is fixed to 0, the output Z _i becomes 0 regardless of the value of the multiplicand X.
Even when is output, a through current, a charging / discharging current, and an on-current flow through the element. Therefore, there is a problem that the power loss in the unit partial product generating circuit 103 or the partial product generating circuit 101 is large.

The present invention has been made to solve the above-mentioned problems in the conventional device, and an object of the present invention is to provide a partial product generation circuit with low power loss.

[0014]

In the partial product generating circuit according to the first aspect of the present invention, a shift signal, an inversion signal, an enable signal, and a multiplicand which are obtained by converting adjacent three digits of a multiplier by a Booth decoder. In a partial product generation circuit capable of calculating a partial product based on the above, a unit partial product generation circuit, which is provided for each digit of the multiplicand and outputs the partial product individually by one digit, includes the following elements: , A first selection element that selectively conducts only one of the two adjacent digits of the multiplicand to the output based on the shift signal and cuts off the other; a predetermined constant when the enable signal has a specific value. A second selection element that outputs and outputs the output of the first selection element when it is not the specific value; the output of the second selection element is selectively inverted based on the inversion signal or Inverting element for inverting and outputting; and, when the enable signal is not the specific value selects the output of the inverting element, as well as select zero when the is a specific value, each of the partial product 1
Third selection element that outputs as one digit.

In the partial product generating circuit according to a second aspect of the present invention, the partial product is generated based on the shift signal, the inverted signal, the enable signal, and the multiplicand, which are obtained by converting three adjacent digits of the multiplier by the Booth decoder. In the partial product generation circuit capable of calculating, the unit partial product generation circuit, which is provided for each digit of the multiplicand and individually outputs the partial product by one digit, includes the following elements: That is, the multiplicands adjacent to each other When the enable signal has a specific value, the constant is selected from the three inputs of two digits and a constant, and when the enable signal has a specific value, the constant is selected based on the shift signal.
A first selection element that selects one of the digits and conducts the selected signal to the output and cuts off the other signals; the output of the first selection element is selectively inverted or non-inverted based on the inverted signal. An inverting element that inverts and outputs; and, when the enable signal is not the specific value, the output of the inverting element is selected, and when the enable signal is the specific value, zero is selected and output as one digit of the partial product. Second selection element.

In the partial product generating circuit according to a third aspect of the present invention, the partial product is generated based on the shift signal, the inverted signal, the enable signal, and the multiplicand, which are obtained by converting adjacent three digits of the multiplier by the Booth decoder. In the partial product generation circuit capable of calculating, the unit partial product generation circuit, which is provided for each digit of the multiplicand and individually outputs the partial product by one digit, includes the following elements: That is, the multiplicands adjacent to each other Of the three inputs of two digits and the inverted signal, the inverted signal is selected when the enable signal has a specific value, and one of the two digits is selected based on the shift signal when the enable signal does not have the specific value. In addition, a selection element that conducts the selected signal to the output and cuts off the other signals; and an exclusive OR of the output of the selection element and the inverted signal is calculated. Inverting element to output as one digit of the partial product.

In the partial product generating circuit according to a fourth aspect of the present invention, a partial product is generated based on a shift signal, an inversion signal, an enable signal, and a multiplicand, which are obtained by converting three adjacent digits of a multiplier by a Booth decoder. In the partial product generation circuit capable of calculating, the unit partial product generation circuit, which is provided for each digit of the multiplicand and individually outputs the partial product by one digit, includes the following elements: that is, the enable signal and the A logical product element that outputs a value determined by the shift signal and outputs a second predetermined value only when the enable signal is not a specific value and the shift signal has a first predetermined value; the logical product A first switching element that conducts one digit of the multiplicand to the output when the output of the element is at the second predetermined value and shuts off when it is not at the second predetermined value; When the shift signal is not the first predetermined value, another digit adjacent to the one digit is conducted to the output, and when it is not the first predetermined value, the second switch element is cut off; the enable signal Is the specified value, the inverted signal is conducted to the output, and when it is not the specified value, the third switch element is cut off; and the outputs of the first to third switch elements are short-circuited to each other and input to one side. An inverting element that inputs the inverted signal to the other and outputs the exclusive OR of these two inputs as one digit of the partial product.

In the partial product generating circuit according to a fifth aspect of the present invention, the partial product is generated based on the shift signal, the inverted signal, the enable signal, and the multiplicand which are obtained by converting three adjacent digits of the multiplier by the Booth decoder. In the partial product generation circuit capable of computing the above, a unit partial product generation circuit which is provided for each digit of the multiplicand and individually outputs the partial product by one digit includes the following elements: Of the two inputs of digit and constant, the constant is selected when the enable signal is a specific value, the one digit is selected when the enable signal is not the specific value, and the selected signal is conducted to the output. And a first selection element that cuts off the others; an inverting element that selectively inverts or non-inverts the output of the first selection element based on the inversion signal and outputs the output; 2 of the output, the output of the inverting element the unit partial product generating circuit of the same structure is provided corresponding to the digit one subordinate of the one digit of the multiplicand comprises
A second selection element that selectively conducts only one of the inputs to the output based on the previous shift signal and cuts off the other; and an output of the second selection element when the enable signal is not the specific value. A third selection element which selects and outputs zero as one digit of the partial product when the selected value is the specific value.

In the partial product generating circuit according to a sixth aspect of the present invention, the partial product is generated based on the shift signal, the inverted signal, the enable signal, and the multiplicand, which are obtained by converting three adjacent digits of the multiplier by the Booth decoder. In the partial product generation circuit capable of computing the above, a unit partial product generation circuit which is provided for each digit of the multiplicand and individually outputs the partial product by one digit includes the following elements: Of the two inputs of digit and constant, the constant is selected when the enable signal is a specific value, the one digit is selected when the enable signal is not the specific value, and the selected signal is conducted to the output. And a first selection element that cuts off the others; outputs the same value as the inversion signal when the enable signal is not the specific value, and outputs the same value when the enable signal is the specific value. A second selection element that outputs the same value as; a inverting element that selectively inverts or non-inverts the output of the first selection element based on the output of the second selection element; and From the two inputs of the output and the output of the inverting element included in the unit partial product generating circuit of the same structure provided corresponding to the one lower digit of the one digit of the multiplicand, to the previous shift signal Based on this, only one is selected as one digit of the partial product to conduct to the output and the other is shut off.

[0020]

[Action]

<Operation of the Invention According to Claim 1> In the partial product generation circuit of the present invention, since the unit partial product generation circuit includes the first to third selection elements and the inversion element, the shift signal, the inversion signal, and the enable signal are generated. The partial product can be calculated based on the multiplicand. Therefore, this partial product generation circuit is suitable for a multiplier according to Booth's algorithm. Moreover, when the enable signal has a specific value, that is, when the partial product unconditionally outputs zero, the second selection element outputs a constant to the inverting element, so that the output of the inverting element varies even if the multiplicand changes. do not do. Also, the second and third
The output of the selection element is also fixed to constant and zero and does not change. Therefore, in a usage mode in which the multiplier is fixed and the enable signal has a specific value, the power consumption associated with the operation of the device is reduced.

<Operation of the Invention According to Claim 2> In the partial product generation circuit of the present invention, since the unit partial product generation circuit includes the first and second selection elements and the inverting element, the shift signal,
The partial product can be calculated based on the inverted signal, the enable signal, and the multiplicand. Therefore, this partial product generation circuit is suitable for a multiplier according to Booth's algorithm. Moreover, when the enable signal has a specific value, the first selection element outputs a constant to the inverting element, so that the output of the inverting element does not change even if the multiplicand changes. Also,
The output of the second selection element is also fixed at zero and does not change.

Therefore, in the usage mode in which the multiplier is fixed and the enable signal has a specific value, the power consumption associated with the operation of the element is reduced. Further, in this usage mode, since the input signals to the second selection element and the inverting element do not change, the power consumption due to the charge / discharge current of these elements is also reduced. In addition, in this usage mode, since the first selection element blocks any of the two digits of the multiplicand, the power consumption due to the ON current due to the change of the multiplicand is also reduced.

<Operation of the Invention According to Claim 3> In the partial product generation circuit of the present invention, since the unit partial product generation circuit includes the selection element and the inversion element, the shift signal, the inversion signal,
The partial product can be calculated based on the enable signal and the multiplicand. Therefore, this partial product generation circuit is suitable for a multiplier according to Booth's algorithm. Moreover, when the enable signal has a specific value, the selection element outputs the inversion signal to the inversion element, so that the output of the inversion element does not change even if the multiplicand changes.

Therefore, in a usage mode in which the multiplier is fixed and the enable signal has a specific value, the power consumption associated with the operation of the element is reduced. Further, in this usage mode, since the input signal to the inverting element does not change, the power consumption due to the charging / discharging current of this element is also reduced. In addition, in this usage mode, the selection element cuts off any of the two digits of the multiplicand, so that the power consumption due to the on-current due to the change of the multiplicand is also reduced.

<Operation of the Invention According to Claim 4> In the partial product generating circuit of the present invention, since the unit partial product generating circuit includes the first to third switch elements, the logical product element, and the inverting element, the enable signal is generated. Is a specific value, the partial product can be calculated by using a Booth decoder in which the shift signal takes only the first predetermined value. Therefore, this partial product generation circuit is suitable for a multiplier according to Booth's algorithm. Moreover, when the enable signal has the specific value and the shift signal has the first predetermined value, the inversion signal is input to the inversion element due to the conduction of only the third switch element, so that the multiplicand changes. However, the output of the inverting element does not change. Further, since the shift signal and the enable signal are input to the logical product element, the output thereof does not depend on the multiplicand.

Therefore, in a usage mode in which the multiplier is fixed and the enable signal has a specific value, the power consumption associated with the operation of the device is reduced. Further, in this usage mode, since the input signals to the third switch element, the inverting element, and the AND element do not change, the power consumption due to the charge / discharge current of these elements is also reduced. In addition, in this usage mode, since the first and second switch elements cut off any of the two digits of the multiplicand, the power consumption due to the on-current accompanying the change of the multiplicand is also reduced.

<Operation of Invention of Claim 5> In the partial product generating circuit of the present invention, since the unit partial product generating circuit includes the first to third selection elements and the inverting element, the shift signal,
The partial product can be calculated based on the inverted signal, the enable signal, and the multiplicand. Therefore, this partial product generation circuit is suitable for a multiplier according to Booth's algorithm. Moreover, when the enable signal has a specific value, the first selection element outputs a constant to the inverting element, so that the output of the inverting element does not change even if the multiplicand changes. At the same time, an inversion element or a constant output by the inversion element in the unit partial product generation circuit of the next lower digit is output to the third selection element,
Since the enable signal is input, its output also does not depend on the multiplicand.

Therefore, in the usage mode in which the multiplier is fixed and the enable signal has a specific value, the power consumption associated with the operation of the element is reduced. Further, in this usage mode, since the input signals to the third selection element and the inverting element do not change, the power consumption due to the charging / discharging current of these elements is also reduced. In addition, in this usage mode, since the multiplicand is cut off by the first selection element and the multiplicand is not input to the second selection element, the power consumption due to the ON current of these elements due to the change of the multiplicand is also reduced. It

<Operation of the Invention According to Claim 6> In the partial product generation circuit of the present invention, since the unit partial product generation circuit includes the first to third selection elements and the inverting element, the shift signal,
The partial product can be calculated based on the inverted signal, the enable signal, and the multiplicand. Therefore, this partial product generation circuit is suitable for a multiplier according to Booth's algorithm. Moreover, when the enable signal has a specific value, the first selection element outputs a constant to the inverting element, so that the output of the inverting element does not change even if the multiplicand changes. At the same time, the enable signal and the inverted signal are input to the second selection element, so that the output is also independent of the multiplicand.

Therefore, in the usage mode in which the multiplier is fixed and the enable signal has a specific value, the power consumption associated with the operation of the element is reduced. Further, in this usage mode, since the input signals to the second selection element and the inverting element do not change, the power consumption due to the charge / discharge current of these elements is also reduced. In addition, in this usage mode, since the multiplicand is cut off by the first selection element and the multiplicand is not input to the third selection element, the power consumption due to the ON current of these elements due to the change of the multiplicand is also reduced. It

[0031]

【Example】

<First Embodiment> First, a first embodiment of the present invention will be described. FIG. 1 is a circuit diagram showing the internal configuration of the unit partial product generation circuit 110 of this embodiment. In the partial product generation circuit 101 of FIG. 12, the unit partial product generation circuit 103 is replaced with the unit partial product generation circuit 110,
The partial product generation circuit of this embodiment is realized.

In FIG. 1, 1 and 7 are INVs, 2 and 3 are TGs, 4 is a logical product element (hereinafter abbreviated as AND) which outputs a logical product of 2 inputs, 5 is EXOR, and 6 is NAND. Is. Each element other than TG has a CMOS structure. Since the unit partial product generation circuit 110 is configured in this way, it operates as follows.

First, the operation when the shift signal C ₁ is 1, the inverted signal C ₂ is 1 and the enable signal C ₃ is 1 (non-specific value) will be described. At this time, since TG2 is turned on and TG3 is turned off, X _i-1 is selected as one input of AND4. Since the enable signal C ₃ is at 1, AND4
X _i-1 is transmitted from EXOR5 to EXOR5. Inversion signal C ₂ is 1
For it, the bar X _i-1 is an inverted signal of the X _i-1 is, E
It is output from XOR5 to AND6. Further, since the enable signal C ₃ is 1, X _i-1 is I from the NAND 6.
Output to NV7. As a result, the output Z from INV7
_A bar X _i-1 is obtained as _i .

Next, the shift signal C ₁ is 0 and the inverted signal C _{2 is}
1 and the enable signal C ₃ is 1 will be described. At this time, since TG2 is turned off and TG3 is turned on, X _i is selected as one input of AND4. Since the enable signal C ₃ is 1, AND4 to EXOR
X _i is transmitted to 5. Since the inverted signal C ₂ is 1,
Which is an inverted signal of the X _i bar X _i is, AND from EXOR5
It is output to 6. Since the enable signal C ₃ is 1, X _i is output from the NAND 6 to INV 7. As a result, the bar X _i is obtained as the output Z _i from the INV 7.

Next, the shift signal C ₁ is 1, and the inverted signal C _{2 is}
The operation when 0 is 0 and the enable signal C ₃ is 1 will be described. At this time, since TG2 is turned on and TG3 is turned off, X _i-1 is selected as one input of AND4. Since the enable signal C ₃ is 1, AND4 to EXO
X _i-1 is transmitted to R5. Since the inverted signal C ₂ is 0, X _i-1 is further output from EXOR5 to AND6. Further, since the enable signal C ₃ is 1, N
Bar X _i-1 is output from IN6 to INV7. As a result, X _i−1 is obtained as the output Z _i from INV7.

Next, the shift signal C ₁ is 0 and the inverted signal C _{2 is}
The operation when 0 is 0 and the enable signal C ₃ is 1 will be described. At this time, since TG2 is turned off and TG3 is turned on, X _i is selected as one input of AND4. Since the enable signal C ₃ is 1, AND4 to EXOR
X _i is transmitted to 5. Since the inverted signal C ₂ is 0,
X _i is further output from EXOR5 to AND6. Further, since the enable signal C ₃ is 1, the NAN
The bar X _i is output from D6 to INV7. As a result, X _i is obtained as the output Z _i from INV7.

Next, the shift signal C ₁ is 1, and the inverted signal C _{2 is}
Is 1 and the enable signal C ₃ is 0 (specific value). At this time, since TG2 is turned on and TG3 is turned off, X _i-1 is selected as one input of AND4. However, since the enable signal C ₃ is 0, regardless of the value of X _i−1 , AND 4 to EXOR
0 is output to 5. Since the inverted signal C ₂ which is the other input signal to the EXOR ₅ is 1, the EXOR 5 outputs 1 to the NAND 6. However, since the enable signal C ₃ is 0, 1 is output from the NAND 6 to the INV 7 regardless of the output of the EXOR 5. As a result, 0 is obtained as the output Z _i from INV7.

Next, the shift signal C ₁ is 0 and the inverted signal C _{2 is}
1 and the enable signal C ₃ is 0 will be described. At this time, since TG2 is turned off and TG3 is turned on, X _i is selected as one input of AND4. However, since the enable signal C ₃ is 0, 0 is output from the AND 4 to the EXOR 5 regardless of the value of X _i . Since the inverted signal C ₂ which is the other input signal to the EXOR ₅ is 1, the EXOR 5 outputs 1 to the NAND 6. However, the enable signal C ₃ is 0
Therefore, regardless of the output of this EXOR5, NA
1 is output from ND6 to INV7. as a result,
0 is obtained as the output Z _i from INV7.

Next, the shift signal C ₁ is 1, and the inverted signal C _{2 is}
Will be described and the enable signal C ₃ is 0. At this time, since TG2 is turned on and TG3 is turned off, X _i-1 is selected as the input of AND4. However, since the enable signal C ₃ is 0, 0 is output from the AND 4 to the EXOR 5 regardless of the value of X _i−1 . Since the inverted signal C ₂ which is the other input signal to the EXOR5 is 0, the EXOR5 outputs 0 to the NAND6. However, the enable signal C ₃ is 0
Therefore, regardless of the output of this EXOR5, NA
1 is output from ND6 to INV7. as a result,
0 is obtained as the output Z _i from INV7.

Next, the shift signal C ₁ is 0 and the inverted signal C _{2 is}
Will be described and the enable signal C ₃ is 0. At this time, since TG2 is turned off and TG3 is turned on, X _i is selected as the input of AND4. However, since the enable signal C ₃ is 0, 0 is output from the AND 4 to the EXOR 5 regardless of the value of X _i .
Inverted signal C ₂ which is the other input signal to EXOR ₅
Is 0, so EXOR5 goes to NAND6
Is output. However, since the enable signal C ₃ is 0, regardless of the output of this EXOR 5, the NAND
1 is output from 6 to INV7. As a result, IN
0 is obtained as the output Z _i from V7.

The three input signals C ₁ , C ₂ , C ₃ described above
2 and the output Z _i , that is, the relationship between the input and output in the unit partial product generation circuit 110 is summarized as shown in FIG. That is, the unit partial product generation circuit 110 and the partial product generation circuit configured by the unit partial product generation circuit 110 have the same input / output relationships as those of the conventional unit partial product generation circuit 103 and partial product generation circuit 101, respectively. Therefore, it is suitable for constructing a multiplier according to Booth's algorithm.

In the unit partial product generation circuit 110, AND4
Is inserted into one input of EXOR5, and therefore
When the enable signal C ₃ is 0, the multiplicand X _i-1 ,
Regardless of the value of X _i , not only INV7 and NAND6 but also the output of EXOR5 is fixed. Also, the output of AND4 itself is similarly fixed. Therefore, when the enable signal C ₃ is fixed to 0 and therefore the output Z _i is always 0, no through current flows in any of the elements forming the unit partial product generating circuit 110. Therefore, the power consumption in the unit partial product generation circuit 110 is reduced.

<Second Embodiment> Next, a second embodiment of the present invention will be described. FIG. 3 is a circuit diagram showing the internal structure of the unit partial product generation circuit of this embodiment. Similar to the unit partial product generating circuit 110, the unit partial product generating circuit 120 also replaces the unit partial product generating circuit 103 in FIG. 12 to form a partial product generating circuit of this embodiment.

In FIG. 3, 8, 13, 15, 17, 1
9 is INV, 9, 10, 18 is TG, 14 and 16 is AN
D and 11 are EXOR, and 12 is NAND.
Each element other than TG has a CMOS structure. In the unit partial product generation circuit 120, the shift signal C ₁ and the enable signal C ₃ are input to the AND 14, and the output of the AND 14 controls the TG 9. At the same time, the inversion signal of the shift signal C ₁ obtained by the INV ₁₅ and the enable signal C ₃ are A
The TG 10 is controlled by the output of the AND 16 which is input to the ND 16 and obtained as a result.

First, the operation when the shift signal C ₁ is 1, the inverted signal C ₂ is 1 and the enable signal C ₃ is 1 will be described. At this time, the output of AND14 becomes 1, so TG
9 turns on, and the output of one AND16 becomes 0, so T
G10 turns off. As a result, X _i-1 is selected as one input to the EXOR 11. Since the other input of the EXOR 11 is fixed at 1 by the inverted signal C ₂ , EX
OR11 outputs the inverted signal bar X _i-1 of X _i-1 to one input of NAND 12. Since the other input of the NAND 12 is fixed at 1 by the enable signal C ₃ ,
The AND 12 outputs X _i-1 to the INV 13. As a result, the bar X _i-1 is obtained as the output Z _i of the INV 13.

Next, the shift signal C ₁ is 0 and the inverted signal C _{2 is}
1 and the enable signal C ₃ is 1 will be described. At this time, the output of AND14 becomes 0, so T
G9 turns off, and the output of one AND16 becomes 1, so TG10 turns on. As a result, X _i is selected as one input to EXOR 11. Since the other input of the EXOR 11 is fixed at 1 by the inverted signal C ₂ , EX
OR11 outputs the inverted signal bar X _i of X _i to one input of NAND 12. Since the other input of the NAND 12 is fixed at 1 by the enable signal C ₃ ,
D12 outputs X _i to INV13. As a result, I
The bar X _i is obtained as the output Z _i of the NV 13.

Next, the shift signal C ₁ is 1, and the inverted signal C _{2 is}
The operation when 0 is 0 and the enable signal C ₃ is 1 will be described. At this time, the output of AND14 becomes 1, so TG
9 turns on, and the output of one AND16 becomes 0, so T
G10 turns off. As a result, X _i-1 is selected as one input to the EXOR 11. Since the other input of the EXOR 11 is fixed to 0 by the inverted signal C ₂ , EX
The OR 11 outputs X _i-1 to one input of the NAND 12. Since the other input of the NAND 12 is fixed at 1 by the enable signal C ₃ , the NAND 12 has a bar X
_i-1 is output to INV13. As a result, INV13
X _i−1 is obtained as the output Z _i of

Next, the operation when the shift signal C ₁ 0, the inverted signal C ₂ is 0 and the enable signal C ₃ is 1 will be described. At this time, the output of AND14 becomes 0, so TG9
Turns off and the output of one AND16 becomes 1, so TG
10 turns on. As a result, X _i is selected as one input to EXOR 11. Since the other input of the EXOR11 is fixed to 0 by the inverted signal C _2, EXOR
11 outputs X _i to one input of the NAND 12. N
Since the other input of the AND 12 is fixed at 1 by the enable signal C ₃ , the NAND 12 sets the bar X _i to I
Output to NV13. As a result, the output Z of INV13
X _i is obtained as _i.

Next, the operation when the enable signal C ₃ is 0 will be described. At this time, TG9 and TG10 are simultaneously turned off regardless of the value of the shift signal C1. At the same time, since the TG 18 is turned on, the inverted signal C ₂ is input to one input of the EXOR 11. Since the inverted signal C ₂ is also input to the other input of the EXOR 11,
11 always outputs 0 regardless of the values of X _i-1 and X _i .
Since both inputs of the NAND 12 are fixed to 0, the NAND 12 always outputs 1 to the INV 13. As a result, INV
13 always outputs 0.

As described above, this unit partial product generation circuit 1
Similarly to the unit partial product generation circuit 110, the relationship between the inputs and outputs of the unit 20 is represented by the relationship diagram of FIG. That is, the unit partial product generation circuit 120 and the partial product generation circuit configured by the unit partial product generation circuit 120 are suitable for forming a multiplier according to Booth's algorithm.

Further, in the unit partial product generation circuit 120, when the enable signal C ₃ is 0, the input signals of all the elements other than the TGs 9 and 10 are shift signals regardless of X _i-1 and X _i. C ₁ , inverted signal C ₂ , enable signal C ₃
It is a fixed value determined by. Therefore, when the enable signal C ₃ is 0, the unit partial product generating circuit 12
No through current flows through any of the elements forming 0, and no charging / discharging current flows. Furthermore, since both of the TGs 9 and 10 are turned off, no on-current flows through these TGs 9 and 10. Therefore, in the unit partial product generation circuit 120,
Power consumption is further reduced.

From the above description of operation, it is clear that N
Even if the AND 12 and INV 13 are removed and the output of the EXOR 11 is directly used as the output Z _i , the decoded signals C ₁ ,
The same output Z _i is obtained for all combinations of C ₂ and C ₃ . Further, the signal input to the TG 18 may be any fixed signal, that is, a constant, instead of the inverted signal C ₂ . However, in this case, NAND 12 and I
NV13 cannot be removed.

<Third Embodiment> Next, a third embodiment of the present invention will be described. FIG. 4 is a circuit diagram showing the internal configuration of the unit partial product generation circuit of this embodiment. Similar to the unit partial product generating circuit 110, the unit partial product generating circuit 130 also replaces the unit partial product generating circuit 103 in FIG. 12 to form a partial product generating circuit of this embodiment.

In FIG. 4, 21, 23 and 25 are IN
V, 22, 24, and 26 are TGs, 20 is a NAND, and 27 is an EXOR. Each element other than TG is CMO
It has an S structure. In the unit partial product generation circuit 120, the shift signal C ₁ and the enable signal C ₃ are input to the NAND 20, and the output of the NAND 20 controls the TG 22. The shift signal C ₁ controls the TG 24, and the enable signal C ₃ controls the TG 26.

First, the operation when the shift signal C ₁ is 1, the inverted signal C ₂ is 1 and the enable signal C ₃ is 1 will be described. At this time, the output of the NAND 20 becomes 0, so T
G22 turns on. On the other hand, since the shift signal C ₁ and the enable signal C ₃ are both 1, both the TGs 24 and 26 are turned off. Therefore, X _i-1 is selected as one input of the EXOR 27. Since the other input of the EXOR 27 is fixed to 1 which is the value of the inverted signal C ₂ ,
The output Z _i from 27 is the bar X which is the inverted signal of X _i-1.
i-1 is obtained.

Next, the shift signal C ₁ is 0 and the inverted signal C _{2 is}
1 and the enable signal C ₃ is 1 will be described. At this time, the output of the NAND 20 is 1, so
The TG22 turns off. On the other hand, since the shift signal C ₁ is 0, the TG 24 turns on. Also, enable signal C ₃
Is 1, the TG 26 is turned off. Therefore, EX
X _i is selected as one input of the OR 27. EXOR
Since the other input 27 is fixed to 1 the value of the inverted signal C _2, bar X _i is obtained, which is an inverted signal of the X _i as the output Z _i from EXOR27.

Next, the shift signal C ₁ is 1, and the inverted signal C _{2 is}
The operation when 0 is 0 and the enable signal C ₃ is 1 will be described. At this time, since the output of the NAND 20 becomes 0,
The TG22 turns on. On the other hand, since the shift signal C ₁ and the enable signal C ₃ are both 1, both the TGs 24 and 26 are turned off. Therefore, X _i-1 is selected as one input of the EXOR 27. Since the other input of the EXOR 27 is fixed to 0 which is the value of the inverted signal C ₂ ,
X _i-1 is obtained as the output Z _i from R27.

Next, the shift signal C ₁ is 0 and the inverted signal C _{2 is}
The operation when 0 is 0 and the enable signal C ₃ is 1 will be described. At this time, the output of the NAND 20 is 1, so
The TG22 turns off. On the other hand, since the shift signal C ₁ is 0, the TG 24 turns on. Also, enable signal C ₃
Is 1, the TG 26 is turned off. Therefore, EX
X _i is selected as one input of the OR 27. EXOR
Since the other input of 27 is fixed to 0 which is the value of the inverted signal C ₂ , X _i is obtained as the output Z _i from the EXOR 27.

Next, the shift signal C ₁ is 1, and the inverted signal C _{2 is}
1 and the enable signal C ₃ is 0 will be described. At this time, the output of the NAND 20 is 1, so
The TG22 turns off. Further, since the shift signal C ₁ is 1, the TG 24 is turned off, and since the enable signal C ₃ is 0, the TG 26 is turned on. Therefore, the inverted signal C ₂ that has passed through the TG 26 is selected as one input of the EXOR 27. The inverted signal C is also applied to the other input of the EXOR 27.
_{Since 2} is input, the EXOR 27 always outputs 0 as the output Z _i regardless of the values of X _i−1 and X _i .

Next, the shift signal C ₁ is 0 and the inverted signal C _{2 is}
1 and the enable signal C ₃ is 0 will be described. At this time, the output of the NAND 20 is 1, so
The TG22 turns off. Further, since the shift signal C ₁ is 0, the TG 24 is turned on, and since the enable signal C ₃ is 0, the TG 26 is also turned on. As a result, TG24 and TG
26 outputs collide with each other. Therefore, the shift signal C ₁ is 0, the inverted signal C ₂ is 1, and the enable signal C ₃ is 0.
The combination of is prohibited.

Therefore, the Booth decoder in front of the unit partial product generating circuit 130 needs to be constructed so as not to output such a combination. The booth decoder 100 shown in FIG. 10 satisfies this request.

Next, the shift signal C ₁ is 1, and the inverted signal C _{2 is}
Will be described and the enable signal C ₃ is 0. At this time, the output of the NAND 20 is 1, so
The TG22 turns off. Further, since the shift signal C ₁ is 1, the TG 24 is turned off, and since the enable signal C ₃ is 0, the TG 26 is turned on. Therefore, the inverted signal C ₂ that has passed through the TG 26 is selected as one input of the EXOR 27. The inverted signal C is also applied to the other input of the EXOR 27.
_{Since 2} is input, the EXOR 27 always outputs 0 as the output Z _i regardless of the values of X _i−1 and X _i .

Next, the shift signal C ₁ is 0 and the inverted signal C _{2 is}
Will be described and the enable signal C ₃ is 0. At this time, the output of the NAND 20 is 1, so
The TG22 turns off. Further, since the shift signal C ₁ is 0, the TG 24 is turned on, and since the enable signal C ₃ is 0, the TG 26 is also turned on. As a result, TG24 and TG
26 outputs collide with each other. Therefore, the shift signal C ₁ is 0, the inverted signal C ₂ is 0, and the enable signal C ₃ is 0.
The combination of is prohibited.

Therefore, the Booth decoder in front of the unit partial product generating circuit 130 needs to be constructed so as not to output such a combination. The Booth decoder 100 shown in FIG. 10 also satisfies this request.
For this reason, the Booth decoder 100 is suitable for a Booth decoder provided in front of the unit partial product generation circuit 130.

The relationship between the input and output described above can be summarized as shown in the relationship diagram of FIG. Therefore, the unit partial product generation circuit 130 and the partial product generation circuit configured by the unit partial product generation circuit 130 can be used to configure a multiplier according to Booth's algorithm.

In the unit partial product generation circuit 130, when the enable signal C ₃ is 0, the TGs 22 and 24 are generated.
The input signals of all elements except the shift signal C ₁ , the inverted signal C ₂ , and the enable signal C ₃ are independent of X _i−1 and X _i.
It is a fixed value determined by. Therefore, when the enable signal C ₃ is 0, the unit partial product generating circuit 13
No through current and no charging / discharging current flow through any of the elements forming 0. Furthermore, since both of the TGs 22 and 24 are turned off, the on-current does not flow in these TGs 22 and 24. Further, since the fixed inverted signal C ₂ is supplied to the TG 26, the ON current does not flow again.
Therefore, the unit partial product generation circuit 130 has a high effect of reducing power consumption. Further, as compared with the unit partial product generation circuit 120, the number of elements is smaller, which is advantageous in that the manufacturing cost is lower.

<Fourth Embodiment> Next, a fourth embodiment of the present invention will be described. FIG. 6 is a block diagram showing the internal structure of the partial product generation circuit of this embodiment. As shown in FIG. 6, in the partial product generation circuit 141, one unit partial product generation circuit 140 is provided for each digit X _i (i = 0 to m) of the multiplicand X. Each unit partial product generation circuit 140 having the same internal configuration has a unit part corresponding to one digit X _i and decode signals C ₁ , C ₂ , C ₃ , and one lower digit X _{i -1.} The variable S _i-1 intermediately generated by the product generation circuit 140 is input. Each unit partial product generation circuit 140 generates a partial product Z based on these signals.
One digit Z _{i of} is calculated and output. Note that S _-1 is a signal whose value is fixed to 0.

FIG. 7 is a circuit diagram showing the internal structure of the unit partial product generating circuit 140. In FIG. 7, 28, 32,
36 is INV, 29, 30, 33, 34 are TG, 31 is EXOR, and 35 is NAND. Each element other than TG has a CMOS structure. Unit partial product generation circuit 1
At 40, the enable signal C ₃ causes the TG 29, ₃
The ON / OFF of 0 is controlled, and the output of the NAND 35 is controlled. In addition, the shift signal C ₁ causes T
ON / OFF of G33 and G34 is controlled. The variable S _i-1 is input to the TG 33. Partial product Z from INV36
Z _i, which is one digit of, is output, and the EXOR 31 outputs the variable S _i . Variable S input to TG33
_i-1 is output by the EXOR 31 in the unit partial product generation circuit 140 corresponding to the one lower digit X _i-1 .

[0069] Since which unit the partial product generating circuit 140 is also configured the same, when the variable S _i which EXOR31 the partial product generating circuit 140 corresponding to the X _i is output is X _i is
S _i-1 input to the TG 33 in the same unit partial product generation circuit 140 is X _i-1 , and when S _i is bar X _i , S _i-1 becomes bar X _i-1 . When S _i is 1, S _i-1 is 1, and when S _i is 0, S _i-1 is 0.
Becomes Therefore, the unit partial product generation circuit 140 corresponding to X _i operates as follows.

First, the operation when the shift signal C ₁ is 1, the inverted signal C ₂ is 1 and the enable signal C ₃ is 1 will be described. At this time, since the enable signal C ₃ is 1, T
G29 turns on and TG30 turns off. Therefore, X _i is selected as one input of the EXOR 31.
Since the other input of EXOR31 inverted signal C ₂ is a value 1 is input, EXOR31 outputs bar X _i is the inverted signal of the X _i. Further, since the shift signal C ₁ is 1, the TG 33 turns on and the TG 34 turns off.
Therefore, as one input of the NAND 35, the value is the bar X.
_The variable S _{i -1,} which is _i-1 , is selected. Since the enable signal C ₃ which is the other input of the NAND 35 is 1, the NAN
X _i-1 is transmitted from D35 to INV36. As a result, INV 36 outputs bar X _i-1 as output Z _i .

Next, the shift signal C ₁ is 0 and the inverted signal C _{2 is}
1 and the enable signal C ₃ is 1 will be described. At this time, since the enable signal C ₃ is 1, the TG 29 is turned on and the TG 30 is turned off. Therefore, X _i is selected as one input of the EXOR 31. An inverted signal C having a value of 1 is input to the other input of the EXOR 31.
Because ₂ is input, EXOR31 outputs bar X _i is the inverted signal of the X _i. Further, since the shift signal C ₁ is 0, the TG 33 turns off and the TG 34 turns on. Therefore, as one input of the NAND 35, the bar X
_i is selected. Since the enable signal C ₃ which is the other input of the NAND 35 is 1, the NAND 35 outputs INV
The bar X _i is transmitted to 36. As a result, INV36
Outputs a bar X _i as the output Z _i.

Next, the shift signal C ₁ is 1, and the inverted signal C _{2 is}
The operation when 0 is 0 and the enable signal C ₃ is 1 will be described. At this time, since the enable signal C ₃ is 1, the TG 29 is turned on and the TG 30 is turned off. Therefore, X _i is selected as one input of the EXOR 31. The other input of the EXOR 31 has an inverted signal C having a value 0.
_{Since 2} is input, the EXOR 31 outputs X _i . Further, since the shift signal C ₁ is 1, the TG 33 turns on and the TG 34 turns off. Therefore, NAND3
As one input 5, the variable S _i-1 value is X _i-1 is selected. Since the enable signal C ₃ which is the other input of the NAND 35 is 1, the bar X _i-1 is transmitted from the NAND 35 to the INV 36. As a result, the INV 36 outputs X _i-1 as the output Z _i .

Next, the shift signal C ₁ is 0 and the inverted signal C _{2 is}
The operation when 0 is 0 and the enable signal C ₃ is 1 will be described. At this time, since the enable signal C ₃ is 1, the TG 29 is turned on and the TG 30 is turned off. Therefore, X _i is selected as one input of the EXOR 31. The other input of the EXOR 31 has an inverted signal C having a value 0.
_{Since 2} is input, the EXOR 31 outputs X _i . Further, since the shift signal C ₁ is 0, the TG 33 turns off and the TG 34 turns on. Therefore, NAND3
X _i is selected as one input of 5. NAND35
Since the enable signal C ₃ which is the other input of the is 1,
The bar X _i is transmitted from the NAND 35 to the INV 36. As a result, the INV 36 outputs X _i as the output Z _i .

Next, the shift signal C ₁ is 1, and the inverted signal C _{2 is}
1 and the enable signal C ₃ is 0 will be described. At this time, since the enable signal C ₃ is 0, the TG 29 turns off and the TG 30 turns on.
Therefore, 0 is selected as one input of the EXOR 31. An inverted signal C having a value of 1 is input to the other input of the EXOR 31.
_{Since 2} is input, the EXOR 31 outputs 1. Further, since the shift signal C ₁ is 1, the TG 33 turns on and the TG 34 turns off. Therefore, NAND3
As one input of 5, the variable S _i-1 whose value is ₁ is selected. However, since the enable signal C ₃ that is the other input of the NAND 35 is 0, the NAND 35 outputs the value 1 to the INV 36 regardless of the value of the variable S _i-1 . As a result, the INV 36 outputs 0 as the output Z _i .

Next, the shift signal C ₁ is 0 and the inverted signal C _{2 is}
1 and the enable signal C ₃ is 0 will be described. At this time, since the enable signal C ₃ is 0, the TG 29 turns off and the TG 30 turns on.
Therefore, 0 is selected as one input of the EXOR 31. An inverted signal C having a value of 1 is input to the other input of the EXOR 31.
_{Since 2} is input, the EXOR 31 outputs 1. Further, since the shift signal C ₁ is 0, the TG 33 turns off and the TG 34 turns on. Therefore, NAND3
As one input of 5, the value 1 output by the EXOR 31 is selected. However, since the enable signal C ₃ which is the other input of the NAND 35 is 0, the NAND 35 outputs the value 1 to the INV 36 regardless of the output of the EXOR 31. As a result, the INV 36 outputs 0 as the output Z _i .

Next, the shift signal C ₁ is 1, and the inverted signal C _{2 is}
Will be described and the enable signal C ₃ is 0. At this time, since the enable signal C ₃ is 0, the TG 29 turns off and the TG 30 turns on.
Therefore, 0 is selected as one input of the EXOR 31. The other input of the EXOR 31 has an inverted signal C having a value 0.
_{Since 2} is input, the EXOR 31 outputs 0. Further, since the shift signal C ₁ is 1, the TG 33 turns on and the TG 34 turns off. Therefore, NAND3
As one input of 5, the variable S _i-1 whose value is 0 is selected. However, since the enable signal C ₃ that is the other input of the NAND 35 is 0, the NAND 35 outputs the value 1 to the INV 36 regardless of the value of the variable S _i-1 . As a result, the INV 36 outputs 0 as the output Z _i .

Next, the shift signal C ₁ is 0 and the inverted signal C _{2 is}
Will be described and the enable signal C ₃ is 0. At this time, since the enable signal C ₃ is 0, the TG 29 turns off and the TG 30 turns on.
Therefore, 0 is selected as one input of the EXOR 31. The other input of the EXOR 31 has an inverted signal C having a value 0.
_{Since 2} is input, the EXOR 31 outputs 0. Further, since the shift signal C ₁ is 0, the TG 33 turns off and the TG 34 turns on. Therefore, NAND3
As one input of 5, the value 0 output by the EXOR 31 is selected. However, since the enable signal C ₃ which is the other input of the NAND 35 is 0, the NAND 35 outputs the value 1 to the INV 36 regardless of the output of the EXOR 31. As a result, the INV 36 outputs 0 as the output Z _i .

The relationship between the input and the output described above is shown in the relationship diagram of FIG. Therefore, the unit partial product generation circuit 14
0 and the partial product generation circuit 141 configured by the unit partial product generation circuit 140 are suitable for configuring a multiplier according to Booth's algorithm.

Further, in the unit partial product generation circuit 140, when the enable signal C ₃ is 0, all the input signals except the TG 29 have the shift signal C ₁ and the inverted signal regardless of X _i-1 and X _i. It has a fixed value determined by the signal C ₂ and the enable signal C ₃ . Therefore, the enable signal C ₃ is 0
When, the through current does not flow in any of the elements forming the unit partial product generating circuit 140, and the charging / discharging current does not flow. Further, since the TG 29 is turned off, the on-current does not flow in the TG 29 even if X _i changes. Also TG3
Since a fixed signal is supplied to each of 0, 33, and 34, no on-current flows in these TGs. Therefore, in the unit partial product generating circuit 140, power consumption is further reduced. Further, since it is composed of a relatively small number of elements, there is an advantage that the manufacturing cost is relatively low. Further, since there is no prohibition on the values of the decoded signals C ₁ , C ₂ , and C ₃ , there is an advantage that there is no restriction on the configuration of the Booth decoder preceding the partial product generation circuit 141.

<Fifth Embodiment> Next, a fifth embodiment of the present invention will be described. FIG. 8 is a circuit diagram showing the internal structure of the unit partial product generating circuit of this embodiment. In the partial product generation circuit 141 shown in FIG. 6, the unit partial product generation circuit 150 is replaced with the unit partial product generation circuit 140 to form the partial product generation circuit of this embodiment.

In FIG. 8, 37 and 41 are INV and 3
8, 39, 42 and 43 are TGs, 40 is EXOR, and 44 is AND. Each element other than TG is CMOS
Have a structure. In the unit partial product generation circuit 150, ON / OFF of the TGs 38 and 39 is controlled by the enable signal C ₃ . Further, the output of the AND 44 is controlled by the inversion signal C ₂ and the enable signal C ₃ . Further, the shift signal C ₁ controls ON / OFF of the TGs 42 and 43. The variable S _i-1 is input to the TG 42. Further, Z _i, which is one digit of the partial product Z, is output from the TG 42 or TG 43, and the variable S _i is output from the EXOR 40. The variable S _i-1 input to the TG 42 is output by the EXOR 40 in the unit partial product generation circuit 150 corresponding to the digit X _i-1 one lower order.

[0082] Since which unit the partial product generating circuit 150 is also configured the same, when the variable S _i which EXOR40 partial product generating circuit 150 corresponding to the X _i is output is X _i is
S _i-1 input to the TG 42 in the same unit partial product generation circuit 150 is X _i-1 , and when S _i is bar X _i , S _i-1 becomes bar X _i-1 . When S _i is 1, S _i-1 is 1, and when S _i is 0, S _i-1 is 0.
Becomes Therefore, the unit partial product generation circuit 150 corresponding to X _i operates as follows.

First, the operation when the shift signal C ₁ is 1, the inverted signal C ₂ is 1 and the enable signal C ₃ is 1 will be described. At this time, since the enable signal C ₃ is 1,
TG38 turns on and TG39 turns off. Therefore, X _i is selected as one input of the EXOR 40. Since the inversion signal C ₂ is 1 and the enable signal C ₃ is 1, the AND 44 outputs 1 to the other input of the EXOR 40. As a result, EXOR40 outputs the bar X _i is the inverted signal of the X _i. However, since the shift signal C ₁ is 1, the TG 42 is turned on and the TG 43 is turned off. Therefore, the output Z _i is S which is the bar X _i-1.
i-1 is selected. That is, the output Z _i becomes the bar X _i-1 .

Next, the shift signal C ₁ is 0 and the inverted signal C _{2 is}
1 and the enable signal C ₃ is 1 will be described. At this time, since the enable signal C ₃ is 1, the TG 38 is turned on and the TG 39 is turned off.
Therefore, X _i is selected as one input of the EXOR 40. Since the inversion signal C ₂ is 1 and the enable signal C ₃ is 1, the AND 44 outputs 1 to the other input of the EXOR 40. As a result, EXOR40 outputs the bar X _i is the inverted signal of the X _i. Since the shift signal C ₁ is 0, the TG 42 is off and the TG 43 is on. Therefore, the bar X _i is selected as the output Z _i .

Next, the shift signal C ₁ is 1, and the inverted signal C _{2 is}
The operation when 0 is 0 and the enable signal C ₃ is 1 will be described. At this time, since the enable signal C ₃ is 1, the TG 38 is turned on and the TG 39 is turned off.
Therefore, X _i is selected as one input of the EXOR 40. Since the inversion signal C ₂ is 0 and the enable signal C ₃ is 1, the AND 44 outputs 0 to the other input of the EXOR 40. As a result, the EXOR 40 outputs X _i .
However, since the shift signal C ₁ is 1, the TG 42
Is turned on and TG43 is turned off. Thus, S _i-1 is the X _i-1 is selected to the output Z _i. That is, the output Z _i becomes X _i-1 .

Next, the shift signal C ₁ is 0 and the inverted signal C _{2 is}
The operation when 0 is 0 and the enable signal C ₃ is 1 will be described. At this time, since the enable signal C ₃ is 1, the TG 38 is turned on and the TG 39 is turned off.
Therefore, X _i is selected as one input of the EXOR 40. Since the inversion signal C ₂ is 0 and the enable signal C ₃ is 1, the AND 44 outputs 0 to the other input of the EXOR 40. As a result, the EXOR 40 outputs X _i .
Since the shift signal C ₁ is 0, the TG 42 is off and the TG 43 is on. Therefore, the output Z _i
X _i is selected for.

Next, the shift signal C ₁ is 1, and the inverted signal C _{2 is}
1 and the enable signal C ₃ is 0 will be described. At this time, since the enable signal C ₃ is 0, the TG 38 is turned off and the TG 39 is turned on.
Therefore, the value 0 is selected as one input of the EXOR 40. Since the inverted signal C ₂ is 1 and the enable signal C ₃ is 0, the AND 44 outputs 0 to the other input of the EXOR 40. As a result, EXOR 40 outputs the value 0.
By the way, since the shift signal C ₁ is 1, the TG 42
Is turned on and TG43 is turned off. Therefore, S _i-1 having a value of 0 is selected for the output Z _i . That is, the output Z _i becomes zero.

Next, the shift signal C ₁ is 0 and the inverted signal C _{2 is}
1 and the enable signal C ₃ is 0 will be described. At this time, since the enable signal C ₃ is 0, the TG 38 is turned off and the TG 39 is turned on.
Therefore, the value 0 is selected as one input of the EXOR 40. Since the inverted signal C ₂ is 1 and the enable signal C ₃ is 0, the AND 44 outputs 0 to the other input of the EXOR 40. As a result, EXOR 40 outputs the value 0.
By the way, since the shift signal C ₁ is 0, the TG 42
Turns off and TG43 turns on. Therefore, the value 0 which is the output of the EXOR 40 is selected as the output Z _i . That is, the output Z _i becomes zero.

Next, the shift signal C ₁ is 1, and the inverted signal C _{2 is}
Will be described and the enable signal C ₃ is 0. At this time, since the enable signal C ₃ is 0, the TG 38 is turned off and the TG 39 is turned on.
Therefore, the value 0 is selected as one input of the EXOR 40. Since the inverted signal C ₂ is 0 and the enable signal C ₃ is 0, the AND 44 outputs 0 to the other input of the EXOR 40. As a result, EXOR 40 outputs the value 0.
By the way, since the shift signal C ₁ is 1, the TG 42
Is turned on and TG43 is turned off. Therefore, S _i-1 having a value of 0 is selected for the output Z _i . That is, the output Z _i becomes zero.

Next, the shift signal C ₁ is 0 and the inversion signal C _{2 is}
Will be described and the enable signal C ₃ is 0. At this time, since the enable signal C ₃ is 0, the TG 38 is turned off and the TG 39 is turned on.
Therefore, the value 0 is selected as one input of the EXOR 40. Since the inverted signal C ₂ is 0 and the enable signal C ₃ is 0, the AND 44 outputs 0 to the other input of the EXOR 40. As a result, EXOR 40 outputs the value 0.
By the way, since the shift signal C ₁ is 0, the TG 42
Turns off and TG43 turns on. Therefore, the value 0 which is the output of the EXOR 40 is selected as the output Z _i . That is, the output Z _i becomes zero.

The relationship between the input and output described above is shown in the relationship diagram of FIG. Therefore, the unit partial product generation circuit 15
0 and the partial product generation circuit composed of the unit partial product generation circuit 150 are suitable for forming a multiplier according to Booth's algorithm.

Further, in the unit partial product generation circuit 150,
Navel signal C₃Is 0, other than TG38
All input signals are X_i-1, X_iRegardless of the shift
Issue C ₁, Inverted signal C₂, Enable signal C₃Determined by
It is a fixed value. Therefore, the enable signal C₃Is 0
Then the unit partial product generation circuit 150 is configured.
No through current flows through any element, and the charging / discharging current does not
Not flowing. Furthermore, since TG38 is turned off, X_iBut
Even if it changes, the on-current does not flow through the TG 38. Also TG3
A fixed signal is supplied to each of 9, 42 and 43.
Therefore, no on-current flows through these TGs. this
Therefore, the unit partial product generation circuit 150 consumes more power.
Will be reduced. In addition, it consists of a relatively small number of elements
Therefore, there is an advantage that the manufacturing cost is relatively low. Well
Decode signal C₁, C₂, C₃For the value of
Therefore, there is no booth in front of the partial product generation circuit 151.
There is an advantage that there is no restriction on the configuration of the decoder.

[0093]

【The invention's effect】

<Effect of the Invention According to Claim 1> In the partial product generation circuit of the present invention, when the enable signal has a specific value, that is, when zero is unconditionally output as the partial product,
Since the selection element outputs a constant to the inverting element, the output of the inverting element does not change even if the multiplicand changes. Also, the outputs of the second and third selection elements are fixed to constant and zero, respectively, and do not change. Therefore, in a usage mode in which the multiplier is fixed and the enable signal has a specific value, the power consumption associated with the operation of the device is reduced. Therefore, for example, a digital filter with low power consumption can be realized.

<Effect of Invention of Claim 2> In the partial product generating circuit of this invention, when the enable signal has a specific value, the first selection element outputs a constant to the inverting element, so that the multiplicand changes. However, the output of the inverting element does not change.
Also, the output of the second selection element is fixed to zero and does not change. Therefore, in a usage mode in which the multiplier is fixed and the enable signal has a specific value, the power consumption associated with the operation of the device is reduced. Further, in this usage mode, since the input signals to the second selection element and the inverting element do not change, the power consumption due to the charge / discharge current of these elements is also reduced. In addition, in this usage mode, since the first selection element blocks any of the two digits of the multiplicand, the power consumption due to the ON current due to the change of the multiplicand is also reduced.
That is, in this partial product generation circuit, the effect of reducing power consumption is high.

<Effect of the Invention According to Claim 3> In the partial product generating circuit of the present invention, when the enable signal has a specific value, the select element outputs the inversion signal to the inversion element, so that the multiplicand changes. However, the output of the inverting element does not change.
Therefore, in a usage mode in which the multiplier is fixed and the enable signal has a specific value, the power consumption associated with the operation of the device is reduced. Further, in this usage mode, since the input signal to the inverting element does not change, the power consumption due to the charging / discharging current of this element is also reduced. In addition, in this usage mode, the selection element cuts off any of the two digits of the multiplicand, so that the power consumption due to the on-current due to the change of the multiplicand is also reduced. That is, in this partial product generation circuit, the effect of reducing power consumption is high. Further, it can be configured with a small number of elements.

<Effect of the Invention According to Claim 4> In the partial product generating circuit according to the present invention, when the enable signal has a specific value and the shift signal has a first predetermined value, only the third switch element is provided. Since the inverted signal is input to the inverting element due to conduction, the output of the inverting element does not change even if the multiplicand changes. Further, since the shift signal and the enable signal are input to the logical product element, the output thereof does not depend on the multiplicand. Therefore, in a usage mode in which the multiplier is fixed and the enable signal has a specific value, the power consumption associated with the operation of the device is reduced. further,
In this usage mode, the input signals to the third switch element, the inverting element, and the AND element do not change, so that the power consumption due to the charge / discharge current of these elements is also reduced.
In addition, in this usage mode, since the first and second switch elements cut off any of the two digits of the multiplicand, the power consumption due to the on-current accompanying the change of the multiplicand is also reduced. That is, in this partial product generation circuit, the effect of reducing power consumption is high. Moreover, it can be configured with a small number of elements.

<Effect of the Invention According to Claim 5> In the partial product generation circuit of the present invention, when the enable signal has a specific value, the first partial product generation circuit provided corresponding to each digit of the multiplicand. Since the selection element outputs a constant to the inverting element, the output of the inverting element does not change even if the multiplicand changes. At the same time, the constant and the enable signal output from the inverting element or the inverting element in the unit partial product generating circuit of the next lower digit are input to the third selection element.
Its output is also independent of the multiplicand. Therefore,
In a usage mode in which the multiplier is fixed and the enable signal has a specific value, power consumption due to the operation of the device is reduced. Further, in this usage mode, since the input signals to the third selection element and the inverting element do not change, the power consumption due to the charging / discharging current of these elements is also reduced. in addition,
In this usage mode, since the multiplicand is cut off by the first selection element and the multiplicand is not input to the second selection element, the power consumption due to the on-current of these elements due to the change of the multiplicand is also reduced. That is, in this partial product generation circuit, the effect of reducing power consumption is high.

<Effect of Invention of Claim 6> In the partial product generating circuit of this invention, when the enable signal has a specific value, the first select element outputs a constant to the inverting element, so that the multiplicand changes. However, the output of the inverting element does not change.
At the same time, the enable signal and the inverted signal are input to the second selection element, so that the output is also independent of the multiplicand. Therefore, in a usage mode in which the multiplier is fixed and the enable signal has a specific value, the power consumption associated with the operation of the device is reduced. Further, in this usage mode, since the input signals to the second selection element and the inverting element do not change, the power consumption due to the charge / discharge current of these elements is also reduced. In addition, in this usage mode, since the multiplicand is cut off by the first selection element and the multiplicand is not input to the third selection element, the power consumption due to the ON current of these elements due to the change of the multiplicand is also reduced. It That is, in this partial product generation circuit, the effect of reducing power consumption is high.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a unit partial product generation circuit according to a first embodiment.

FIG. 2 is an input / output relationship diagram of the unit partial product generation circuit according to the first embodiment.

FIG. 3 is a circuit diagram of a unit partial product generation circuit according to a second embodiment.

FIG. 4 is a circuit diagram of a unit partial product generation circuit according to a third embodiment.

FIG. 5 is an input / output relationship diagram of a unit partial product generation circuit according to a third embodiment.

FIG. 6 is a block diagram of a partial product generation circuit according to a fourth embodiment.

FIG. 7 is a circuit diagram of a unit partial product generation circuit according to a fourth embodiment.

FIG. 8 is a circuit diagram of a unit partial product generation circuit according to a fifth embodiment.

FIG. 9 is a block diagram of a conventional multiplier.

FIG. 10 is a circuit diagram of a conventional Booth decoder.

FIG. 11 is an input / output relationship diagram of a conventional Booth decoder.

FIG. 12 is a block diagram of a conventional partial product generation circuit.

FIG. 13 is a circuit diagram of a conventional unit partial product generation circuit.

[Explanation of symbols]

2,3,9,10,18,22,24,26,29,3
0, 33, 34, 38, 39, 42, 43 Transmission gate element, 1, 7, 8, 13, 15, 17,
19, 21, 23, 25, 28, 32, 36, 37, 4
1 Inverter element, 4, 14, 16, 44 AND element, 6, 12, 20, 35 Inversion element, 5, 1
1, 27, 31, 40 Exclusive OR elements.

─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-6-19685 (JP, A) JP-A-5-341964 (JP, A) JP-A-6-103031 (JP, A) JP-A-5- 88852 (JP, A) (58) Fields surveyed (Int.Cl. ⁷ , DB name) G06F 7/52 310

Claims (6)

(57) [Claims] 1. A partial product generation circuit capable of calculating a partial product based on a shift signal, an inversion signal, and an enable signal obtained by converting adjacent three digits of a multiplier by a Booth decoder, and each of the multiplicands. A partial product generation circuit provided for each digit and individually outputting the partial product one digit at a time includes a following partial product generation circuit: That is, based on the shift signal from two adjacent digits of the multiplicand. A first selection element that selectively conducts only one to an output and cuts off the other; a predetermined constant is output when the enable signal is a specific value, and an output of the first selection element is output when the enable signal is not the specific value. A second selection element for outputting; an inverting element for selectively inverting or non-inverting the output of the second selection element based on the inversion signal; and the enable No. selects the output of the inverting element when not the specific value, as well as select zero when the is a specific value, a third selection element which outputs each of them as one digit of the partial product. 2. A partial product generation circuit capable of calculating a partial product based on a shift signal, an inversion signal, and an enable signal obtained by converting three adjacent digits of a multiplier by a Booth decoder, and each of the multiplicands. A partial product generating circuit, which is provided for each digit and outputs the partial products individually by one digit, includes the following elements: That is, among the three inputs of the adjacent two digits of the multiplicand and a constant. Therefore, when the enable signal is a specific value, the constant is selected, and when the enable signal is not the specific value, one of the two digits is selected based on the shift signal, and the selected signal is conducted to the output. And a first selection element that shuts off the others, an inverting element that selectively inverts or non-inverts the output of the first selection element based on the inversion signal, and outputs the output. When Buru signal is not the specific value to select the output of the inverting element, the line when in a particular value by choosing zero, second selection element which outputs as a single digit of the partial product. 3. A partial product generation circuit capable of calculating a partial product based on a shift signal, an inversion signal, and an enable signal obtained by converting adjacent three digits of a multiplier by a Booth decoder, and each of said multiplicands. A partial product generation circuit provided for each digit and individually outputting the partial product one digit at a time includes a partial product generation circuit including the following elements: That is, three inputs of the adjacent two digits of the multiplicand and the inverted signal From among the above, when the enable signal has a specific value, the inverted signal is selected, and when it is not the specific value, one of the two digits is selected based on the shift signal, and the selected signal is output. A selection element that conducts with and cuts off the others; and an exclusive OR of the output of the selection element and the inverted signal is calculated and output as one digit of the partial product. Inverting element. 4. A partial product generation circuit capable of calculating a partial product based on a shift signal, an inversion signal, and an enable signal obtained by converting adjacent three digits of a multiplier by a Booth decoder, and each of the multiplicands. A unit partial product generation circuit that is provided for each digit and that outputs the partial products individually by one digit includes the following elements: Partial product generation circuit that outputs a value determined by the enable signal and the shift signal An AND element that outputs a second predetermined value only when the enable signal is not a specific value and the shift signal is a first predetermined value; and the output of the AND element is the second predetermined value. A first switch element that conducts one digit of the multiplicand to the output when the value is a value, and shuts off when the digit is not the second predetermined value; the shift signal is the first predetermined value A second switch element which, when not present, conducts another digit adjacent to the one digit to the output and shuts off when it is not the first predetermined value; when the enable signal is the specific value, the inverted signal A third switch element that conducts to the output and shuts off when the value is not the specific value; and outputs of the first to third switch elements are short-circuited to each other and input to one, and the inverted signal is input to the other,
An inverting element that outputs the exclusive OR of these two inputs as one digit of the partial product. 5. A partial product generation circuit capable of calculating a partial product based on a shift signal, an inversion signal, and an enable signal obtained by converting three adjacent digits of a multiplier by a Booth decoder, and each of the multiplicands. A partial product generating circuit, which is provided for each digit and outputs the partial products individually by one digit, includes the following elements: That is, from among two inputs of one digit of the multiplicand and a constant. When the enable signal is a specific value, the constant is selected, and when the enable signal is not the specific value, the one digit is selected,
Moreover, a first selection element that conducts the selected signal to the output and cuts off the others; an inverting element that selectively inverts or non-inverts the output of the first selection element based on the inversion signal; and From the two inputs of the output of the inverting element and the output of the inverting element provided in the unit partial product generating circuit of the same structure provided corresponding to the digit one lower than the one digit of the multiplicand, A second selection element that selectively conducts only one to an output and cuts off the other based on a shift signal; and, when the enable signal is not the specific value, selects an output of the second selection element and outputs the specific value. And a third selection element that selects zero and outputs it as one digit of the partial product. 6. A partial product generation circuit capable of calculating a partial product based on a shift signal, an inversion signal, and an enable signal obtained by converting adjacent three digits of a multiplier by a Booth decoder, and each of said multiplicands. A partial product generating circuit, which is provided for each digit and outputs the partial products individually by one digit, includes the following elements: That is, from among two inputs of one digit of the multiplicand and a constant. When the enable signal is a specific value, the constant is selected, and when the enable signal is not the specific value, the one digit is selected,
Moreover, the first selection element that conducts the selected signal to the output and shuts off the other signals; outputs the same value as the inversion signal when the enable signal is not the specific value,
A second selection element that outputs the same value as the constant when it is the specific value; an inversion that selectively inverts or non-inverts the output of the first selection element based on the output of the second selection element, and outputs the inverted output. An element; and two inputs of an output of the inverting element and an output of the inverting element included in the unit partial product generation circuit of the same structure provided corresponding to one digit lower than the one digit of the multiplicand A third selection element that selects only one of the two as one digit of the partial product based on the previous shift signal, conducts to the output, and shuts off the other.