JPH0588852A - Partial product generating circuit and multiplying circuit - Google Patents

Abstract

PURPOSE:To carry out the multiplication at a high speed by reducing the number of the constitution gates of a partial product generating circuit used for a multiplying circuit using the Booth's algorithm. CONSTITUTION:The circuits are constituted of an E-NOR gate 2 to select to output multiplicands X0, X1, X2 and X3 as they are or invert and output them, in accordance with a signal SGN1 of a Booth's encoder 1 to show the code of (Y-1+Y0-2Y1) based on the Booth's algorithm, a transmission gate 6 to output the output of the E-NOR gate 2 in accordance with a signal M1-1 to show + or -1 by (Y-1+Y0-2Y1), a transmission gate 8 to shift the output of the E-NOR gate 2 to 1 bit higher order and output it, and a P channel MOS to make a partial product output into 0 by the output of an OR gate 3 to detect 0 by (Y-1+Y0-2Y1).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital multiplication circuit used in a digital signal processing device or the like, and more particularly to a partial product generation circuit and a multiplication circuit using Booth's algorithm.

[0002]

2. Description of the Related Art Conventionally, a multiplication circuit using a secondary Booth algorithm has been constructed as shown in FIG. In FIG. 3, the Booth logic circuit 13 follows the second-order Booth's algorithm and calculates (Y _2i-1 + Y _2i -2) of the multiplier Y.
It is detected whether the value of (Y _{2i + 1} ) is 0, +1, +2, -1, or -2, and the detection signal is output. The switching circuit 14 to which the multiplicand X is applied applies the multiplicand 2X multiplied by 2 to the addition / subtraction switching circuit 15 based on the detection output of the Booth logic circuit 13. The addition / subtraction switching circuit 15 performs a sign process on the multiplicand X or 2X output from the switching circuit 14, and when the detection result of the Booth logic circuit 13 is negative, 2's complement process, that is, the input multiplier. The process of inverting each bit and adding 1 to the least significant bit is performed. Then, the output of the addition / subtraction switching circuit 15 is applied as a partial product output to the adding circuit 16 together with other partial product outputs. This adder circuit 16
Is output as the multiplication output of the multiplier Y and the multiplicand X.

[0003]

According to the multiplication circuit shown in FIG. 3, each switching circuit 14 is composed of a logical gate such as an AND gate (or NAND gate), and the addition / subtraction switching circuit 15 is further provided. It was composed of an adder circuit and a switching gate for performing the 2's complement process. Therefore, the signal flow of the multiplicand X is performed from the switching circuit 14 through the addition / subtraction switching circuit 15, and when the sign is negative, addition processing for 2's complement processing is added, and therefore, as a whole. There was a drawback that the multiplication speed of was slow. Further, since the number of elements forming the switching circuit 14 and the addition / subtraction switching circuit 15 also increases, there is a drawback that the chip area of the integrated circuit increases.

[0004]

The present invention was made in view of the above-mentioned points, and from each bit of the applied multiplier B, according to the quadratic Booth algorithm (Y _2i-1 +
Y _2i −2Y _{2i + 1} ) for each i (i = 0, 1, ...) Is a positive or negative first signal, and +
The second signal indicating 1 and -1, and +2 and-
A Booth encoder that creates and outputs a third signal indicating that the signal is 2, and the (Y _2i-1 + Y _2i -2Y _{2i + 1)} from the first signal, the second signal, and the third signal. ) Is 0, a 0 output circuit that sets the partial product output to 0 based on the detection output of the 0 detection circuit, and outputs each bit of the multiplicand as it is based on the first signal. Alternatively, a bit inversion control circuit that inverts and outputs each bit, a first output circuit that outputs the output of the bit inversion control circuit as the partial product output based on the second signal, and the third signal Based on the second output circuit which shifts the output of the bit inversion control circuit by 1 bit to the upper bit side and outputs it as a partial product output based on the above, a partial product generating circuit with a small number of constituent gates can be obtained.

[0005]

According to the first signal, the second signal, the third signal output according to the multiplier and the detection output of the 0 detection circuit, 0 is output from the 0 output circuit or is output from the first output circuit. Whether or not to output from the second output circuit is directly selected, and whether or not the multiplicands selectively output from the first output circuit and the second output circuit are inverted or remain unchanged is determined in advance. By doing so, the number of logic gates to be configured can be small, so that the multiplication can be speeded up.

[0006]

1 is a circuit diagram showing an embodiment of the present invention.
In the figure, the multiplier is 4-bit data represented by 2's complement consisting of Y ₀ , Y ₁ , Y ₂ , and Y ₃ , and the multiplicand is X.
It is 4-bit data in ₀ , X ₁ , X ₂ , X ₃ which is expressed in 2's complement. The Booth encoder 1 has a multiplier Y ₀ ,
Signals SGN ₁ , M _1-1 , M _2-1 , SGN ₂ , M _1-2 , M _2-2 from Y ₁ , Y ₂ , Y _{3 according} to the second order Booth's algorithm.
Is a circuit for creating and outputting. As is well known, the second-order Booth algorithm is that the multiplication result XY is

[0007]

[Equation 1]

The Booth encoder 1 is represented as
(Y in Equation 1_2i-1+ Y_2i-2Y_{2i + 1}) Is positive or negative
Yes, absolute value is 1 and absolute value is 2
Determine whether. In this booth encoder 1, i =
Multiplier Y represented by 0_-1(= 0), Y₀, Y₁Against
Signal SGN₁Is (Y_-1+ Y₀-2Y₁) Is negative
Only becomes "1" and signal M_1-1Is (Y_-1+ Y₀-2
Y₁) Is +1 and -1, it becomes "1", and
Issue M_2-1Is (Y_-1+ Y₀-2Y₁) Is +2 and -2
Only when it becomes "1". Similarly, a multiplier represented by i = 1
Y₁, Y₂, Y₃To the signal SGN₂Is (Y₁+ Y₂-2
Y₃) Is negative only when the signal M is _1-2Is (Y
₁+ Y₂-2Y₃) Is "1" only when +1 and -1
Signal M_2-2Is (Y₁+ Y₂-2Y₃) Is +2 and -2
Only in the case, it becomes "1".

Here, multiplication (Y_-1+ Y₀-2Y₁) X and
(Y₁+ Y₂-2Y₃) X can be done with exactly the same circuit configuration
Therefore, the following multiplication (Y_-1+ Y₀-2Y₁) About X
Reveal Signal SGN₁Is each bit X of the multiplicand X₀,
X₁, X₂, X₃Of the E-NOR gate 2 to which
Applied to one input. This E-NOR gate 2 is
Signal SGN₁Is “0”, that is, each bit of the multiplicand is positive.
To X₀, X₁, X₂, X₃Is output as is as a partial product output
In order to do so, it acts to invert once and the signal SGN₁But
"1", that is, each bit X of the multiplicand when negative₀, X₁, X
₂, X₃To invert and output as the partial product output,
It works as it is without rolling it. OR gate 3
Signal SGN₁, Signal M_1-1, And signal M_2-1Enter
(Y_-1+ Y₀-2Y ₁) Is detected when the value of 0 is 0
The output of the OR gate 3 is the partial product output P_1-0, P
_1-1, P_1-2, P_1-3, P_1-4Each of the inverter 4 that outputs
Input and power V_DDOf the P-channel MOS5 connected between
Applied to the gate. Signal M_1-1Is each bit of the multiplicand
X₀, X₁, X₂, X₃Is multiplied by ± 1 and the partial product output P_1-0, P
_1-1, P_1-2, P_1-3, P_1-4Signal to output to
Output of each E-NOR gate 2 and input of each inverter 4
Applied to the control input of a transmission gate 6 connected between
And the partial product output P_1-3X output to₃To P
_1-4Applied to the control input of the transmission gate 7 to output
To be done. Also, the signal M_2-1Is each bit X of the multiplicand₀, X
₁, X₂, X₃Is multiplied by ± 2 and the partial product output P_1-0, P_1-1, P
_1-2, P_1-3, P_1-4Is a signal to be output to
Between the input of the inverter 4 and the output of each E-NOR gate 2.
It is applied to the control input of the connected transmission gate 8.
To the signal SGN ₁Output and part of the inverter 9 that inverts
Product output P_1-0Connected between the inputs of the inverter 4 that outputs
Applied to the control input of the transmitted transmission gate 10.

The above configuration is a partial product circuit of (Y _-1 + Y ₀ -2Y ₁ ) and the multiplicand X, and the operation will be described below.
When the value of (Y ₋₁ + Y ₀ −2Y ₁ ) is 0, the signal SGN ₁ , the signal M _1-1 and the signal M _2-1 are all “0”. Therefore,
The transmission gates 6 and 8 are turned off. On the other hand, since the output of the OR gate 3 is "0", the P channel MOS5
All are turned on, the input voltage of each inverter 4 is raised to V _DD , and partial product outputs P _1-0 , P _1-1 , P _1-2 , P _1-3 ,
All 0s are output to P _1-4 . That is, the multiplication result of 0 × X is output to the partial product output.

When the value of (Y _-1 + Y ₀ -2Y ₁ ) is +1, only the signal M _1-1 becomes "1", so that the output of the OR gate 3 turns off the P-channel MOS 5 to transmit the signal. Gates 6 and 7 are turned on. Therefore, each bit X of the multiplicand
₀ , X ₁ , X ₂ , X ₃ are inverted by the E-NOR gate 2 and applied to the input of the inverter 4, so that partial product outputs P _1-0 , P _1-1 , P _1-2 , P _{1 -3} is the multiplicand X ₀ , X ₁ ,
X ₂ and X ₃ are output. Here Although multiplicand X ₃ to the partial product output P _1-4 is output, this is because the X ₃ is the sign bit, is because the same sign it is necessary to output to the most significant bit. Thus, the partial product outputs P _1-0 ,
The result of multiplying the multiplicand X by +1 is output to P _1-1 , P _1-2 , P _1-3 , and P _1-4 .

When the value of (Y _-1 + Y ₀ -2Y ₁ ) is +2, only the signal M _2-1 becomes "1", so that all the P-channel MOSs 5 are turned off and the transmission gate 8 and 10
Turns on. Therefore, each bit X ₀ , X ₁ , X of the multiplicand
₂ , X ₃ are inverted by the E-NOR gate 2 and applied to the input of the inverter 4, so that partial product outputs P _1-1 , P 3
Multiplicands X ₀ , X ₁ , X ₂ and X ₃ are output to _1-2 , P _1-3 and P _1-4 . That is, since X ₀ , X ₁ , X ₂ , and X ₃ are shifted upward by 1 bit, the multiplicand is multiplied by 2. On the other hand, since the inverted output “1” of the signal SGN ₁ is applied to the input of the inverter 4 which outputs the partial product output P _1-0 via the transmission gate 10, the partial product output P _1-0 becomes “ 0 "is output.

(Y_-1+ Y₀-2Y₁When the value of) is -1,
No. SGN₁And signal M_1-1Both are “1”, so transmission
Gates 6 and 7 turn on, and the E-NOR gate is turned on as described above.
Output from the inverter 2 via the inverter 4 is a partial product output P_1-0,
P_1-1, P_1-2, P_1-3, P_1-4Output to the E-NO
The output of the R gate 2 is the bit X of the multiplicand.₀, X₁, X₂,
X₃The output is not the inverted output of X₀, X₁,
X₂, X₃Therefore, the partial product output P_1-0, P_1-1,
P_1-2, P_1-3, P_1-4For each bit X of the multiplicand₀,
X ₁, X₂, X₃The inverted signal of appears. Therefore, the department
Product output P_1-0, P_1-1, P_{1 -2}, P_1-3, P_1-4Is applied
In the adder circuit, the partial product output P_1-0, P_1-1, P
_1-2, P_1-3, P_1-4Signal P in the least significant bit of_1-SGN(=
1) is added to obtain a multiplication result of -1 × X.
Be done.

When the value of (Y _-1 + Y ₀ -2Y ₁ ) is -2, both the signal SGN ₁ and the signal M _2-1 are "1". Therefore,
Similarly to the above, since the output of the E-NOR gate 2 is not the inverted output of each bit X ₀ , X ₁ , X ₂ , X ₃ of the multiplicand, the partial product output P ₁ output via the transmission gate 8 _-1 , P _1-2 , P _1-3 , P _1-4 are each bit X of the multiplicand.
The inverted signals of ₀ , X ₁ , X ₂ and X ₃ are output. At this time, the signal SGN ₁ (= 1) is output to the partial product output P _1-0 . The partial product outputs P _1-0 , P _1-1 , P _1-2 , P _1-3 ,
By adding the signal P _{1 -SGN} to the least significant bit of P _1-4 , the multiplication result of −2 × X is obtained.

According to the partial product generation circuit using the above Booth's algorithm, the number of gate circuits constituting the partial product generation circuit can be small, and the multiplication speed can be increased.
FIG. 2 is a partial product output P of the partial product generation circuit shown in FIG.
_1-0 , P _1-1 , P _1-2 , P _1-3 , P _1-4 , P _1-SGN and P _2-0 , P _2-1 , P _2-2 , P _2-3 , P _2-4 is a circuit diagram of an adder circuit that inputs P _{2 -SGN} and adds them to obtain a multiplication output. That is, the circuits of FIGS. 1 and 2 form a multiplication circuit using the Booth algorithm.

In FIG. 2, the partial product output P_1-0, P_1-1,
P_1-2, P_1-3, P_1-4Is the addition input b of the half adder circuit 11.
Input to the half-adder circuit 11 of the least significant bit
a is the signal P_1-SGNIs applied. Also, each half addition times
Carry output C on path 11_OIs the half adder circuit 1 for the next bit
Applied to the summing input a of 1. This half adder circuit 11
Lower bit output and next output are multiplication output S₀And S₁age
Of the other bits and the most significant bit
The carry output is applied to the addition input a of the full addition circuit 12, respectively.
To be done. The partial product output is output to the addition input b of the full addition circuit 12.
P_2-0, P_2-1, P _2-2, P_2-3, P_2-4Is applied at the bottom
Carry input C of full adder circuit 12 for the most significant bit_INo signal
P_2-SGNIs applied to the carry of each full adder circuit 12.
-Output C_OIs the upper carry input C_IApplied to. So
Then, each output of the full adder circuit 12 is the multiplication output S₂, S₃, S
_Four, S_Five, S₆Is output as
Carry output C on path 12_OIs the multiplication output S₇Output as
Be done.

As shown in FIG. 2, the partial product output P_1-0, P_1-1, P
_1-2, P_1-3, P_1-4Signal P indicating the sign of_1-SGNAnd partial shipment
Power P_2-0, P_2-1, P_2-2, P_2-3, P_2-4Signal indicating the sign of
Issue P _1-SGNIs added to the least significant bit of each partial product output
As a result, the 2's complement process can be performed by the adder circuit.
Then, in the partial product generation circuit, a part of the 2's complement process, that is, the multiplicand
It is only necessary to invert each bit of the number.

[0018]

As described above, according to the present invention, the number of logic gate circuits forming the partial product generation circuit is reduced, and there is an advantage that multiplication can be performed at high speed. Occupies a small area, and the chip size can be reduced.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing an adder circuit that is connected to the circuit of FIG. 1 to form a multiplication circuit.

FIG. 3 is a block diagram showing a conventional circuit.

[Explanation of symbols]

 1 Booth Encoder 2 E-NOR Gate 3 OR Gate 4, 9 Inverter 5 P Channel MOS 6, 7, 8, 10 Transmission Gate 11 Half Adder Circuit 12 Full Adder Circuit

Claims (2)

[Claims] 1. From each bit of the applied multiplier Y to the quadratic
According to Booth's algorithm (Y_2i-1+ Y_2i-2
Y_{2i + 1}) Is for each i (i = 0, 1, ...)
A first signal indicating positive or negative and +1 and-
The second signal indicating 1 and +2 and -2
Booth Encoder that creates and outputs a third signal indicating that
And the first signal, the second signal, and the third signal
From the above (Y _2i-1+ Y_2i-2Y_{2i + 1}) Is 0
Based on the 0 detection circuit for detection and the detection output of the 0 detection circuit
0 output circuit for setting the partial product output to 0, and the first signal
Whether to output each bit of the multiplicand as it is based on
Is a bit inversion control circuit that inverts and outputs each bit,
Output of the bit inversion control circuit based on the second signal
A first output circuit for outputting as a partial product output,
The output of the bit inversion control circuit based on the third signal
Shift 1 bit to the upper bit side and output as partial product output
And a second output circuit for outputting the partial product. 2. A plurality of partial product generation circuits according to claim 1 are provided, and an adder circuit for shifting and adding a partial product output of each partial product generation circuit by a predetermined bit, and an adder circuit for each partial product generation circuit. And a first adder circuit for adding 1 to the least significant bit of the partial product output when the first signal is a negative signal.