CN106533392B

CN106533392B - Digital filter and method for pulse width modulated signals

Info

Publication number: CN106533392B
Application number: CN201610939774.XA
Authority: CN
Inventors: 赵煌; 钱泽斌
Original assignee: Hangzhou Silan Microelectronics Co Ltd
Current assignee: Hangzhou Silan Microelectronics Co Ltd
Priority date: 2016-10-31
Filing date: 2016-10-31
Publication date: 2023-09-08
Anticipated expiration: 2036-10-31
Also published as: CN106533392A

Abstract

The application discloses a digital filter and a method for pulse width modulation signals. The digital filter includes: a first filter for low-pass filtering the pre-processed signal of the pulse width modulated signal to produce a first intermediate signal; a second filter for high-pass filtering the first intermediate signal to produce audio data; a memory for storing parameter values and history values of the first filter and the second filter; a multiplier for performing a multiplication operation according to the parameter value and the history value, thereby performing a filtering operation; and a data controller for connecting the memory and the multiplier with the first filter and the second filter, respectively, in a time-sharing manner, thereby performing a filtering operation. The digital filter can utilize shared modules to reduce power consumption and chip size and reduce cost.

Description

Digital filter and method for pulse width modulated signals

Technical Field

The present application relates to signal processing technology, and more particularly, to digital filters and methods for pulse width modulated (PDM) signals.

Background

In signal processing, an analog-to-digital converter is used to convert an analog signal into a digital signal, and then the digital signal is modulated to generate a digital modulated signal, and the digital modulated signal is filtered to remove quantization noise, thereby obtaining a low-noise digital signal. Signal processing chips integrating analog-to-digital converters and modulators are already commercially available. For example, a digital microphone chip internal sigma-delta analog-to-digital converter dedicated to processing audio signals, in which the analog signal is converted into a pulse width modulation (PDM) format. The PDM signal includes an oversampled one or more bits (e.g., 2 to 4 bits) signal. The relative pulse width of the PDM signal may characterize the amplitude of the input signal.

The working principle of the sigma-delta analog-to-digital converter in the digital processing chip is over-sampling and noise shaping, wherein a digital decimation filter is adopted to decimate output data of a modulator, and the original over-sampling frequency is reduced to a Nyquist sampling rate so as to remove quantization noise, reduce the sampling frequency and prevent aliasing. Thus, digital filters are an important part of digital processing chips.

Among digital filters, finite length impulse response (Finite Impulse Response, i.e., FIR) filters and infinite length impulse response (Infinite Impulse Response, i.e., IIR) filters are fundamental elements of digital signal processing systems. The FIR filter adopts a non-recursive structure including a multistage multiplier and a memory for holding a history value and a parameter value, the history value and the parameter value being obtained from the memory at each stage of operation, and the multiplication operation being performed, and then the calculated value being stored in the memory as a history value of a next stage of operation. The IIR filter adopts a recursive structure including a delay, a multiplier, an adder, and a memory for holding a history value and a parameter value, obtains the history value and the parameter value from the memory at each recursive operation, performs multiplication and addition operations, and then stores the calculated value in the memory as a history value of the next recursive operation.

The above-mentioned existing digital filter may include a plurality of FIR filters and a plurality of IIR filters, and requires a high-frequency read-write memory and multiplication operation in digital signal processing, resulting in an increase in operation time and a loss of system power consumption. Due to the limitation of the system clock, each FIR filter and each IIR filter require separate multipliers and memories, resulting in an increase in chip size and an increase in cost.

Disclosure of Invention

In view of the above, it is an object of the present application to provide a digital filter and method in which a memory and a multiplier are shared in a time-sharing manner, so that power consumption and chip size can be reduced, and cost can be reduced.

According to a first aspect of the present application there is provided a digital filter for pulse width modulated signals comprising: a first filter for low-pass filtering the pre-processed signal of the pulse width modulated signal to produce a first intermediate signal; a second filter for high-pass filtering the first intermediate signal to produce audio data; a memory for storing parameter values and history values of the first filter and the second filter; a multiplier for performing a multiplication operation according to the parameter value and the history value, thereby performing a filtering operation; and a data controller for connecting the memory and the multiplier with the first filter and the second filter, respectively, in a time-sharing manner, thereby performing a filtering operation.

Preferably, the system further comprises an input sampling module, wherein the input sampling module receives a pulse width modulation signal and a clock signal and samples the pulse width modulation signal to obtain a sampling signal.

Preferably, the input sampling module is further configured to perform downsampling on the sampled signal to obtain a second intermediate signal.

Preferably, the frequency compensation circuit further comprises a fourth filter connected with the third filter, and configured to frequency compensate the second intermediate signal, so as to generate a third intermediate signal.

Preferably, the first filter is connected to any one of the input sampling module, the third filter and the fourth filter to obtain an output signal thereof as the preprocessing signal.

Preferably, the first filter, the second filter and the fourth filter are down-sampled respectively.

Preferably, the data controller connects the memory and the multiplier to the fourth filter in a time-sharing manner, thereby performing a filtering operation.

Preferably, the third filter is a cascaded integrator-comb filter, the first filter and the fourth filter are finite length impulse response filters, respectively, and the second filter is an infinite length impulse response filter.

Preferably, the finite impulse response filter generates a plurality of history values using a multi-stage operation in one filtering operation, and the infinite impulse response filter generates a plurality of history values using a plurality of recursions in one filtering operation.

Preferably, the data controller reads the parameter value to the memory in each filtering operation, allocates the history value storage space in the memory, and accesses the history value storage space in a FIFO control manner.

Preferably, the data controller writes back a plurality of history values stored in the history value storage space into the memory after the filtering operation is finished.

Preferably, the data controller alternately performs a history value copy and a filtering operation in a continuous filtering operation, wherein a plurality of history values are generated in the filtering operation, and the plurality of history values generated in the previous filtering operation are copied as a plurality of history values of the next filtering operation in the history value copy.

Preferably, the memory is provided with a read pointer and a write pointer, after all the history values are read and the operation is completed, the read pointer is moved up to be used as a starting address for the next reading, and the write pointer points to the position of the read pointer, so that the input data is written into the memory to be used as the history value for the next operation.

According to a second aspect of the present application, there is provided a digital filtering method for pulse width modulated signals, comprising: low-pass filtering the pre-processed signal of the pulse width modulated signal to produce a first intermediate signal; and high-pass filtering the first intermediate signal to generate audio data, wherein the low-pass filtering and the high-pass filtering respectively comprise storing a parameter value and a history value in a time-sharing manner, and reading the parameter value and the history value to perform multiplication operation, so as to perform filtering operation.

Preferably, the method further comprises: the pulse width modulated signal is sampled to obtain a sampled signal.

Preferably, the method further comprises: the sampled signal is downsampled to obtain a second intermediate signal.

Preferably, the method further comprises: the second intermediate signal is frequency compensated to produce a third intermediate signal.

Preferably, any one of the sampling signal, the second intermediate signal, and the third intermediate signal is taken as the preprocessing signal.

Preferably, in the steps of generating the first intermediate signal, generating the audio data and frequency compensating, downsampling is performed separately.

Preferably, the step of frequency compensation comprises storing the parameter values and the history values in a time-shared manner, and reading the parameter values and the history values for multiplication.

Preferably, in the step of generating the first intermediate signal and performing frequency compensation, a plurality of history values are generated using a multi-stage operation in one filtering operation, and in the step of generating the audio data, a plurality of history values are generated using a plurality of recursions in one filtering operation.

Preferably, in each filtering operation, the parameter values are read to the memory, and the history value storage space is allocated in the memory, and is accessed in a FIFO control manner.

Preferably, after the filtering operation is finished, the plurality of history values stored in the history value storage space are written back to the memory.

Preferably, in the continuous filtering operation, a history value copying and a filtering operation are alternately performed, wherein a plurality of history values are generated in the filtering operation, and in the history value copying, a plurality of history values generated by an operation of a previous filtering operation are copied as a plurality of history values of a next filtering operation.

Preferably, the step of accessing the history value storage space in a FIFO control manner includes: after all the history values are read and the operation is completed, the read pointer is moved upwards to serve as a starting address for next reading, and the write pointer points to the position of the read pointer, so that input data is written into the memory to serve as a history value for next operation.

According to the digital filter of the embodiment of the application, the data controller is used for connecting the memory and the multiplier with the first filter and the second filter respectively in a time-sharing mode. Since the first filter and the second filter share one multiplier and one memory when they are phase-separated, the chip size and cost can be reduced.

In a preferred embodiment, the data controller reads the parameter values from the memory to the memory at the time of the filtering operation, and allocates the history value storage space in the memory, and performs FIFO control at the time of memory access. Accordingly, the operation modes of the first filter and the second filter phase are changed. Therefore, the first filter and the second filter can save the time for the memory read-write operation, so that the respective operation time is obviously reduced, and the time slot requirement shared by time sharing is met.

Drawings

The above and other objects, features and advantages of the present application will become more apparent from the following description of embodiments of the present application with reference to the accompanying drawings.

Fig. 1 shows a schematic block diagram of a digital filter according to the prior art.

Fig. 2 shows a schematic diagram of the FIR filter in a digital filter according to the prior art.

Fig. 3 shows a schematic block diagram of a digital filter according to an embodiment of the application.

Fig. 4 is a schematic diagram illustrating a memory operation of a digital filter according to an embodiment of the present application.

Detailed Description

Various embodiments of the present application will be described in more detail below with reference to the accompanying drawings. The same reference numbers will be used throughout the drawings to refer to the same or like parts. For clarity, the various features of the drawings are not drawn to scale.

The application may be embodied in various forms, some examples of which are described below.

The application adopts a more optimized structure and method to realize the PDM digital filter with high efficiency and low cost.

Fig. 1 shows a schematic block diagram of a digital filter according to the prior art. The digital filter supports sampling rates Fs of 48K, 44.1K, … and 8KHz of audio data, and samples and filters the PDM signal by sampling an oversampling clock PDM_clk which is fixed by 64 times. For example, in the case of a sampling rate Fs of 48KHz, the frequency of the oversampling clock pdm_clk is 3.072MHz.

The digital filter 100 includes an input sampling module IS, (modulated-Integrator-Comb, CIC) filter CIC, a first finite impulse response (Finite Impulse Response, FIR) filter cic_comp, a second FIR filter hb_fir, and a first infinite impulse response (Infinite Impulse Response, IIR) filter hp_iir, connected in sequence. The first FIR filter cic_comp, the second FIR filter hb_fir, and the first IIR filter hp_iir respectively perform a plurality of recursive operations, thereby removing signal noise.

The first FIR filter cic_comp is connected to the memory MEM1 and the multiplier MULT1, wherein the memory MEM1 is used to store the history value and parameter value of the recursive operation, and the multiplier MULT1 is used to perform the multiplication operation.

The second FIR filter hb_fir is connected to the memory MEM2 and the multiplier MULT2, wherein the memory MEM2 is used to store the history value and the parameter value of the recursive operation, and the multiplier MULT2 is used to perform the multiplication operation.

The first IIR filter hp_iir is connected to the memory MEM3 and the multiplier MULT3, wherein the memory MEM3 is used to store the history value and parameter value of the recursive operation, and the multiplier MULT3 is used to perform the multiplication operation.

In the digital filter 100, an input sampling module IS receives the synchronized PDM clock pdm_clk and the PDM signal pdm_din, and performs input signal sampling. CIC filter CIC performs a first low pass filtering of the PDM signal, where 16 times down-sampling is performed. The first FIR filter cic_comp frequency compensates the PDM signal, with a 2-fold down-sampling. The second FIR filter hb_fir performs a second low pass filtering, wherein a 2-fold downsampling is performed. The first IIR wave device hp_iir performs a first high-pass filtering to remove low-frequency noise, and outputs audio data Fo with a sampling rate Fs.

The plurality of FIR filters and the IIR filter of the digital filter 100 perform high-pass filtering and low-pass filtering while downsampling, so that high-frequency noise and low-frequency noise in the PDM signal can be removed, and noise shaping is realized. The audio data Fo generated after digital filtering of the PDM signal may be used for further signal processing, such as amplification and digital-to-analog conversion.

However, in the above-described conventional digital filter 100, the plurality of FIR filters and the plurality of IIR filters each require a high-frequency read/write memory and multiplication operation in digital signal processing, which results in an increase in operation time and a loss of system power consumption. Due to the limitation of the system clock, each FIR filter and each IIR filter require separate multipliers and memories, resulting in an increase in chip size and an increase in cost.

Fig. 2 shows a schematic diagram of the FIR filter in a digital filter according to the prior art. The FIR filter includes a multistage multiplier and a memory. The history value is stored in a memory (for example, a static random access memory SRAM), the history value and the parameter value are obtained from the memory at each stage of operation, and multiplication operation is performed, and then the calculated value is stored in the memory as the history value of the next stage of operation. In the read-write operation of the memory, the history values and the corresponding coefficients are sequentially read in reverse order to perform multiplication operation, and then the current history values are written into the next address. How many stages the FIR filter has, how many read and write-back operations are to be performed.

Specifically, as shown in FIG. 2, Z ^-1 The time delay unit is used for performing time delay preservation on the data input in the history as v; x (n) is the current input data, and y (n) is the output result after the current data operation. v0 holds the value of the previous input data, assuming x (n) is the nth input data, v0 holds the data of the n-1 th input, and so on pushing v1 holds the data … … of the n-2 th input. b0 represents the first order coefficient of the FIR filter, b1 represents the 2 nd order coefficient of the FIR filter, and so on … …. v. data is saved to memory. In the conventional method, each operation needs to be read from the memory, and after the operation is completed, data needs to be written into the next address of the memory, that is, x (n) needs to be written into the address of the memory where v0 is located, v0 needs to be written into the memory where v1 is located, and M-1 times (M represents the order of the filter).

Therefore, the FIR filter requires a high-frequency read-write memory and performs multiplication operation in digital signal processing, resulting in an increase in operation time and a loss of system power consumption.

We haveThe design method is that the FIFO structure is used for writing x (n) into V by writing back 1 time each time _M-2 The read pointer is then moved up.

Fig. 3 shows a schematic block diagram of a digital filter according to an embodiment of the application. The digital filter supports sampling rates Fs of 48K, 44.1K, … and 8KHz of audio data, and samples and filters the PDM signal by sampling an oversampling clock PDM_clk which is fixed by 64 times. For example, in the case of a sampling rate Fs of 48KHz, the frequency of the oversampling clock pdm_clk is 3.072MHz.

The digital filter 200 includes an input sampling block IS, a CIC filter CIC, a first FIR filter cic_comp, a second FIR filter hb_fir, and a first IIR filter hp_iir, a memory MEM, and a multiplier MULT, which are connected in order. Unlike the prior art digital filter 100, the digital filter 200 further includes a DATA controller data_ctrl.

In the digital filter 200, the input sampling module IS receives the synchronized PDM clock pdm_clk and the PDM signal pdm_din, and performs input signal sampling. CIC filter CIC performs a first low pass filtering of the PDM signal, where 16 times down-sampling is performed. The first FIR filter cic_comp frequency compensates the PDM signal, with a 2-fold down-sampling. The second FIR filter hb_fir performs a second low pass filtering, wherein a 2-fold downsampling is performed. The first IIR wave device hp_iir performs a first high-pass filtering to remove low-frequency noise, and outputs audio data Fo with a sampling rate Fs.

In this digital filter 200, the first FIR filter cic_comp, the second FIR filter hb_fir, and the first IIR wave device hp_iir are connected to a common memory MEM and multiplier MULT via a DATA controller data_ctrl. The DATA controller data_ctrl performs time-sharing control so that the first FIR filter cic_comp, the second FIR filter hb_fir, and the first IIR wave device hp_iir can read and write the memory MEM in different time periods and perform multiplication by using the multiplier MULT. Further, the DATA controller data_ctrl reads the parameter values from the memory to the memory, allocates the history value storage space in the memory, and performs FIFO control at the time of memory access.

The plurality of FIR filters and the IIR filter of the digital filter 200 perform high-pass filtering and low-pass filtering while down-sampling, so that high-frequency noise and low-frequency noise in the PDM signal can be removed, and noise shaping is realized. The audio data Fo generated after digital filtering of the PDM signal may be used for further signal processing, such as amplification and digital-to-analog conversion.

In the digital filter 200, the DATA controller data_ctrl may read the parameter values and the history values of the previous stages from the memory in each operation of the FIR filter, and in each recursive operation of the IIR filter. After the end of the multistage operation of the FIR filter, all the history values stored in the memory are written back to the memory MEM. After the end of the multiple recursions of the IIR filter, the last history value stored in the memory is written back to the memory MEM. Thus, the digital filter 200 can reduce the number of memory read and write operations.

In the digital filter according to the related art, since a high frequency read-write memory is required and multiplication is performed at each operation, a slot cannot satisfy the demand of time sharing. The first FIR filter cic_comp, the second FIR filter hb_fir and the first IIR wave hp_iir respectively require the use of separate multipliers MULT and memories MEM.

According to the digital filter 200 of the embodiment of the present application, the operation modes of the FIR filter and the IIR filter are changed, so that a plurality of FIR filters and one IIR filter can save time for memory read/write operations, thereby significantly reducing the respective operation time. At a system clock of 16MHz, the first FIR filter cic_comp, the second FIR filter hb_fir, and the first IIR wave device hp_iir may share one multiplier MULT and one memory MEM in a time-sharing manner, thereby reducing the chip size and the cost.

Fig. 4 is a schematic diagram illustrating a memory operation of a digital filter according to an embodiment of the present application. In one example, the memory operation shown in FIG. 4 is performed during the operation of the second FIR filter HB_FIR in the digital filter 200 shown in FIG. 3. The second FIR filter hb_fir performs, for example, M-stage operations, where M is an integer of 1 or more.

The DATA controller data_ctrl reads parameter values from the memory to the memory, and allocates history value storage space in the memory, and performs FIFO control at the time of memory access. The size of the history value storage space corresponds to the number of stages of the FIR filter, for example, M storage units are allocated in the memory to store the history value corresponding to the M-stage operation.

In one operation of the FIR filter, M-stage operations are performed. The DATA controller data_ctrl sequentially stores the M history values in M memory cells addressed by consecutive addresses, and sets the read pointer rd_adr and the write pointer wr_adr. After all the history values are read and the operation is completed, the read pointer is moved up by one address as the starting address for the next reading, and the write pointer points to the position of the read pointer, so that the input data x is written in as the history value for the next operation. Therefore, in one operation of the FIR filter, M history values generated by M-stage operations are written back only once by using the FIFO structure, instead of the useless full write back operation. Because the complete FIR operation is completed once through the structure of the FIFO only needs to be written back once, time and power consumption are saved.

In the digital filter according to the related art, M-level operations are performed in successive operations of the FIR filter, respectively. Since the FIR filter also needs to perform downsampling by a factor of 2, the calculation result of one operation will be extracted from the two operations. Although each operation of the FIR filter requires time consuming and power consuming operations, the result of the operation of only one operation is useful.

In the digital filter according to the embodiment of the present application, the history value copying and the M-level operation are alternately performed in the continuous operation of the FIR filter, and therefore, the FIR filter performs the M-level operation only in half the number of operations, and directly copies the result of the M-level operation in the previous operation in the other half of the number of operations. That is, after performing the M-stage operation in the first operation, only the operation of writing back the history value is performed for the second operation, and no multiplication operation is performed, thus saving time and power consumption.

In a preferred embodiment, the digital filter 200 is, for example, a filter for a digital microphone, comprising a 5 th order CIC filter, a 28 th order first FIR filter cic_comp, a 95 th order second FIR filter hb_fir, a 1 st order first IIR filter hp_iir, thereby achieving filtering and downsampling of the digital audio signal. By adopting the FIFO structure to store the history value in the memory and optimizing the memory in the modes of the history value up-shifting, time-sharing multiplexing multiplier and the memory, the chip area can be reduced and the power consumption can be reduced. The digital filter 200 can achieve high performance of 80db SNR and filtering effect of 20-24 KHz bandwidth. Under the process of SMIC 130 nm, the chip area is only 0.045 square mm, and the area of ARCH reaches 0.112 square mm, and the area is reduced by more than 1 time.

In the above-described embodiment, it IS described that the digital filter includes the input sampling block IS, the CIC filter CIC, the first FIR filter cic_comp, the second FIR filter hb_fir, and the first IIR filter hp_iir, and the DATA controller data_ctrl and the shared memory MEM and multiplier MULT.

In an alternative embodiment, the input sampling module IS may be omitted if the input signal of the digital filter IS a sampled digital signal. If the frequency of the pulse width modulated signal is close to the frequency of the audio data, the CIC filter CIC and the first FIR filter cic_comp may be omitted. Thus, in alternative embodiments, the digital filter may comprise only the second FIR filter hb_fir and the first IIR filter hp_iir, and the DATA controller data_ctrl and the shared memory MEM and multiplier MULT, the second FIR filter hb_fir and the first IIR filter hp_iir being used for high-pass filtering and low-pass filtering, respectively, to obtain the audio DATA from the pulse-width modulated signal, depending on the actual requirements of the signal conversion.

Embodiments in accordance with the present application, as described above, are not intended to be exhaustive or to limit the application to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the application and the practical application, to thereby enable others skilled in the art to best utilize the application and various modifications as are suited to the particular use contemplated. The scope of the application should be determined by the following claims.

Claims

1. A digital filter for pulse width modulated signals, comprising:

a first filter for low-pass filtering the pre-processed signal of the pulse width modulated signal to produce a first intermediate signal;

a second filter for high-pass filtering the first intermediate signal to produce audio data;

a memory for storing parameter values and history values of the first filter and the second filter;

a multiplier for performing a multiplication operation according to the parameter value and the history value, thereby performing a filtering operation; and

a data controller for connecting the memory and the multiplier with the first filter and the second filter respectively in a time-sharing manner, thereby performing a filtering operation,

wherein the data controller reads the parameter value to the memory in each filtering operation, allocates the history value storage space in the memory, accesses the history value storage space in a FIFO control manner,

and after the filtering operation is finished, the data controller writes back a plurality of historical values stored in the historical value storage space into the memory.

2. The digital filter of claim 1, further comprising an input sampling module that receives a pulse width modulated signal and a clock signal, the pulse width modulated signal being sampled to obtain a sampled signal.

3. The digital filter of claim 2, further comprising a third filter coupled to the input sampling module for downsampling the sampled signal to obtain a second intermediate signal.

4. A digital filter according to claim 3, further comprising a fourth filter connected to the third filter for frequency compensating the second intermediate signal to produce a third intermediate signal, the first filter being connected to any one of the input sampling module, the third filter and the fourth filter to obtain its output signal as the pre-processed signal.

5. The digital filter of claim 4, wherein the first filter, the second filter, and the fourth filter are downsampled, respectively.

6. The digital filter of claim 4, wherein the data controller connects the memory and the multiplier to the fourth filter in a time-sharing manner to perform a filtering operation.

7. The digital filter of claim 4, wherein the third filter is a cascaded integrator-comb filter, the first and fourth filters are each finite-length impulse response filters, and the second filter is an infinite-length impulse response filter.

8. The digital filter of claim 7, wherein the finite impulse response filter employs multiple stages of operations in one filtering operation to produce a plurality of history values, and wherein the finite impulse response filter employs multiple recursions in one filtering operation to produce a plurality of history values.

9. The digital filter according to claim 1, wherein the data controller alternately performs a history value copy and a filtering operation in a continuous filtering operation, wherein a plurality of history values are generated in the filtering operation, and wherein a plurality of history values generated in an operation of a previous filtering operation are copied as a plurality of history values of a next filtering operation in the history value copy.

10. The digital filter according to claim 9, wherein the memory is provided with a read pointer and a write pointer, the read pointer being moved up one as a start address of the next reading after all the history values are read and the operation is completed, the write pointer pointing to a position of the read pointer, thereby writing the input data into the memory as a history value of the next operation.

11. A digital filtering method for pulse width modulated signals, comprising:

low-pass filtering the pre-processed signal of the pulse width modulated signal to produce a first intermediate signal; and

high-pass filtering the first intermediate signal to produce audio data,

wherein the low-pass filtering and the high-pass filtering respectively comprise storing a parameter value and a history value in a time-sharing manner, and reading the parameter value and the history value to perform multiplication operation, thereby performing filtering operation,

wherein, in each filtering operation, the parameter value is read to the memory, and the history value storage space is allocated in the memory, and the history value storage space is accessed by adopting a FIFO control mode,

after the filtering operation is finished, the plurality of history values stored in the history value storage space are written back into the memory.

12. The method of claim 11, further comprising: the pulse width modulated signal is sampled to obtain a sampled signal.

13. The method of claim 12, further comprising: the sampled signal is downsampled to obtain a second intermediate signal.

14. The method of claim 13, further comprising: and performing frequency compensation on the second intermediate signal so as to generate a third intermediate signal, wherein any one of the sampling signal, the second intermediate signal and the third intermediate signal is used as the preprocessing signal.

15. The method of claim 14, wherein the steps of generating the first intermediate signal, generating the audio data, and frequency compensating are downsampling, respectively.

16. The method of claim 14, wherein the step of frequency compensating includes storing the parameter values and the history values in a time-shared manner, and reading the parameter values and the history values for multiplication.

17. The method of claim 14, wherein in the step of generating the first intermediate signal and performing frequency compensation, a plurality of history values are generated using a multi-stage operation in one filtering operation, and in the step of generating the audio data, a plurality of history values are generated using a plurality of recursions in one filtering operation.

18. The method of claim 12, wherein in the continuous filtering operation, a history value copying and a filtering operation are alternately performed, wherein in the filtering operation, a plurality of history values are generated, and in the history value copying, a plurality of history values generated by an operation of a previous filtering operation are copied as a plurality of history values of a next filtering operation.

19. The method of claim 18, wherein accessing the history value storage space in a FIFO controlled manner comprises: after all the history values are read and the operation is completed, the read pointer is moved upwards to serve as a starting address for next reading, and the write pointer points to the position of the read pointer, so that input data is written into the memory to serve as a history value for next operation.