JPH036919A - Delay device - Google Patents

Abstract

PURPOSE:To obtain a long delay time with a small scale of memory device by applying A/D conversion in a sampling rate being twice the input signal band or over, reducing the rate into a required minimum sampling rate with a decimation filter and writing the result in the storage device. CONSTITUTION:An audio signal whose band is limited by an LPF 1 is converted into a 48kHz digital signal by an A/D converter 2. A decimation filter 4 cuts off a band of 12.5kHz or over of the 48kHz digital signal and converts the result into a 24kHz digital signal, which is stored in a RAM 5. A timing signal generator 3 executes write and readout alternately, and an over sampling filter 6 applies oversampling to the readout digital signal to convert the signal into the digital signal whose sampling rate is 48kHz and whose frequency band of <=11.5kHz is attenuated and only the audio signal with a required band is sent to a D/A converter 7.

Description

DETAILED DESCRIPTION OF THE INVENTION INDUSTRIAL APPLICATIONS The present invention relates to delay devices, and more particularly to delay devices that digitally delay signals.

2. Description of the Related Art With recent advances in digital signal processing technology, delay devices have also been digitized. 7th delay device
It is shown in the figure and explained (for example, Electronics Life magazine, January 1888 issue, pp. 105-112).

The audio input is band-limited by a low-pass filter (LPF) 100 and then A/D converted by an adaptive delta modulation (ADM) modulator 101.
Here, it is converted into a 500kHzl bit digital signal. This digital signal is stored in the dynamic RAM 103 by the control logic 102, and
Reading is performed using a read signal that has a certain difference from the address signal during writing. This read digital signal is converted into an analog signal by an ADM demodulator 104, and after aliasing noise is removed by a low pass filter (LPF) 105, it is taken out as an audio output. In this way, writing and reading to and from RAM are always performed by shifting the address value by a constant value,
It generates an audio signal that is delayed for a certain period of time.

Problems to be Solved by the Invention However, in the above configuration, A/D conversion is performed at a fairly high sampling rate for the audio band, so in order to obtain a sufficient delay time, a large-scale storage device is required. Furthermore, since an ADM modulator is used for A/D conversion, the distortion rate becomes high.

In view of the above-mentioned problems, the present invention provides a delay device that is a small-scale storage device and can provide audio output with a low distortion rate.

Means for Solving the Problems In order to achieve the above object, a delay device according to the present invention converts an input analog signal into a digital signal at a sampling rate higher than twice the required band.
A/D conversion means, an FIR filter for decimating the output of the A/D conversion means, a storage means for sequentially storing the output of the FIR filter, and sequentially reading stored contents from the storage means and converting them into analog signals. This is how it was done.

In addition, in order to achieve the above object, the delay device according to the present invention is capable of transmitting an input analog signal into two bands of a required band.
A/D conversion means for converting the digital signal into a digital signal at a sampling rate higher than twice the sampling rate; a first FIR filter for decimating the output of the A/D conversion means;
a second FIR filter that sequentially reads out stored contents from the storage means and performs oversampling;
The output of the IR filter is converted into an analog signal.

In order to achieve the above object, the delay device according to the present invention further includes an A/D conversion means for converting an input analog signal into a digital signal at a sampling rate higher than twice the required band; a first FIR filter for decimating the output of the /D conversion means; a storage means for sequentially storing the output of the first FIR filter at a period T; The apparatus includes an oversampling means that performs oversampling by reading out and multiplying the read storage contents by a preset coefficient, and converting the output of the oversampling means into an analog signal.

In order to achieve the above object, the delay device according to the present invention further includes an A/D conversion means for converting an input analog signal into a digital signal at a sampling rate higher than twice the required band; a first FIR filter for decimating the output of the /D conversion means; a storage means for sequentially storing the output of the first FIR filter at a period T; a second FIR filter that performs oversampling by reading out and multiplying the read storage content by a preset coefficient; and a D/A conversion means that converts the output of the second FIR filter into an analog signal. The number of filter taps of the second FIR filter is greater than the number of filter taps of the first FIR filter.

Effect As mentioned above, since A/D conversion is performed at a sampling rate that is more than twice the input signal band when capturing audio input (hereinafter referred to as A/D conversion by oversampling), the input stage Analog low-pass filter (
A simple LPF (hereinafter referred to as LPF) is required, and since the sampling rate is reduced to the minimum necessary using a decimating d filter and then written to the storage device, it is possible to obtain a long delay time with a small-scale storage device. It is something that can be done.

In addition, since A/D conversion is performed by oversampling, the analog LPF at the input stage can be simple, and a decimation filter is used to reduce the sampling rate to the minimum necessary before writing to the storage device. Because of this, it is possible to obtain a long delay time with a small-scale storage device, and during playback, the sampling rate can be increased with an oversampling filter to increase the D/A
Since conversion is performed, a simple analog LPF at the output stage is sufficient.

In addition, when performing D/A conversion by increasing the sampling rate with an oversampling filter during playback as described above, oversampling is performed using the above storage device, so there is no need to increase the storage device. It is possible to perform oversampling.

In addition, when performing D/A conversion by increasing the sampling rate with an oversampling filter during playback as described above, oversampling is performed using the above storage device, and the number of taps of the FIR filter for decimation is Since the number of taps of the FIR filter for oversampling is increased, there is no need to increase the storage device (because the FIR filter for oversampling can have higher performance, the decimation filter can be made smaller accordingly). You can also
Since the number of taps of the FIR filter for oversampling is greater than the number of taps of the FIR filter for decimation, the transition region of the FIR filter for oversampling is wider than the transition region of the FIR filter for decimation. Signals in the band that could not be removed sufficiently can be removed by the oversampling FIR filter, and high-performance filter characteristics can be obtained as a whole.

Example The present invention will be explained below based on the drawings.

FIG. 1 is a block diagram of a delay device according to the invention.

Reference numeral 1 denotes an LPF, which limits the band of audio input. Here, the required frequency band for input audio is 10kHz.
Therefore, it is assumed that LPF'l passes a band up to 10 kHz. 2 is an A/D converter (ADC
), which converts the input analog signal into a 16-bit digital signal. Here, in order to perform double oversampling, the sampling rate is set to 48kHz.
It is said that

3 is a timing signal generator, which generates and supplies necessary timing signals to each block. 4 is a 9B tap finite impulse response (hereinafter referred to as FIR) type decimation filter, which limits the band of the given digital signal and then converts the 16-bit 48kllz digital signal into a 16-bit 24kHz digital signal. . As shown in Figure 2A, its characteristics are a pass band of 0 to 10 kHz.

Cutoff band: 12.5~24kHz, transition region: 10~
It is 12.5kllz. A RAM 5 stores the low sampling rate digital signal obtained from the decimation filter 4. Here, 1024
A word (lk word) x 16 bit RAM is used. Reference numeral 6 denotes a 128-tap FIR type oversampling filter (0°S filter), which performs oversampling of the digital signal read out from the RAM 5 at a sampling rate of 24kllz. This converts the sampling rate to 48 kHz and outputs it as a 16-bit digital signal. 7 is a D/A converter (DA
C), which converts the input digital signal into an analog signal. Its characteristics, as shown in Figure 2B, are a passband of 0 to 10 kHz and a cutoff band of 11.5 to 2.
4 kHz, with a transition region of 10 to 11.5 kHz. 8 is an LPF that removes aliasing noise output from the D/A converter 7.

Next, the operation shown in FIG. 1 will be explained. The given audio input is band-limited by the LPF 1. A/D
Since the sampling rate of the converter 2 is 48 kHz and the required band is 10 kHz, it is possible to use an LPFI with a simple configuration in which the passband is below LO kHz and the cutoff band is above 24 Hz.

The audio signal band-limited by LPF 1 is processed by A/D
The converter 2 converts it into a 48kHz digital signal.

The decimation filter 4 cuts off frequencies above 12.5 kHz of the 48 kHz digital signal, converts it into a 24 kHz digital signal by decimation, and stores it in the RAM 5. In this way, since the digital signal obtained by the A/D converter 2 is stored in the RAM 5 after lowering the sampling rate, it becomes possible to store a longer period of audio signal. Since the RAM 5 is a one-word RAM, it can store 42.7 ms worth of audio input. The timing signal generator 3 performs writing and reading alternately, and the address at that time is always shifted by a certain amount, so if (read address) - (write address) = D, then delay time: ( 1024-D)÷24 [ms]
...(The delay time of ri can be obtained.

The digital signal read out in this way is oversampled by an oversampling filter 6 and converted into a digital signal of 48 kHz (sampling frequency) in which frequencies above 11.5 kHz are attenuated. As shown in FIG. 2A, the cutoff band for the decimator 1 and filter 4 is 12.5 kHz or more, so 11.5~
12kHz includes aliasing noise, but the cutoff frequency of this oversampling filter 6 is set to 11.5kHz.
Hz, the above-mentioned aliasing noise is removed at this point (see FIG. 2B), and only the audio signal in the necessary band is sent to the D/A converter 7. Therefore, D/A converter 7
The analog signal output from
Since no Hz signal is included, the LPF 8 can be a filter with a simple configuration.

With the above configuration, almost no distortion occurs during A/D conversion and D/A conversion, and since other blocks basically perform linear conversion, overall distortion is reduced. A small clear audio signal is output from the LPF8.

FIG. 3 is a block diagram showing a specific embodiment of the decimation filter 4 in FIG. 1.

To explain this figure, 10 is an address generator, which has a period T (T=1/48m) as shown in FIG. 4A.
5) is 0. 1. 2. -, 95. Then 9
4°95, 0. 1. ..., 93. It generates an address signal like this. 11 is RAM;
It has an address space of 96 words. 13 is a coefficient ROM that stores tap coefficients of the filter. The frequency characteristics of this tap coefficient are as shown in FIG. 2A. 12, 14, and 16 are latches that hold input data. F is an accumulator and accumulates input data.

When the control signal AC is applied, the accumulation result is cleared and a new accumulation is started.

Next, the operation of FIG. 3 will be explained. Address generator 10 generates an address signal as shown in FIG. 4A, and reads data from RAMII. The read data is held by the latch 12 (FIG. 4B) and the multiplier 1
given to 5. The other input of the multiplier 15 has a coefficient RO
The tap coefficient read out from M13 is given via the latch 14 (FIG. 4C), and these two Rn,
Multiplication of the value of Kn is performed. The multiplication result is held by latch 16 (FIG. 4D) and provided to accumulator 17.

The accumulator 17 receives a control signal A as shown in FIG.
Based on C, the multiplication results Mn are accumulated (FIG. 4E).

At the end of 96 accumulations, the accumulation result A@-as is loaded into the latch 18 and the decimation filter output Yi
(Figure 4G). The coefficient ROM 13 has a second
Since coefficients having frequency characteristics as shown in Figure A are stored, 12.
Sampling rate 2 after components above 5Hz are removed
A digital signal decimated to 4kHz is output. Therefore, the hatched part in Figure 2A (
11.5 to 12 kHz) remains as aliasing noise.

Next, a specific example of the oversampling filter 6 shown in FIG. 1 will be described. The block diagram of the oversampling filter 6 has the same configuration as the block diagram shown in FIG. 3, so using FIG.
I will explain the different parts.

First, the address generator 10 has a configuration as shown in FIG.
10-bit counter 24 counting down by s
and an adder 23, two groups of 25 DEG AND gates, and six groups.

As shown in FIG. 6B, the 7-pit counter 20 has a period T.
Address signals from 0 to 63 are generated twice within (T = 1/48 m5). The constant generator 21 is used to set the delay time. The 10-bit counter 24 indicates the address to which the output of the decimation filter 4 is written, and changes at a period T as shown in FIG. 6A. When the control signal Z received on the AND gate group 2 becomes "0", the result of the adder 23 becomes all "0" and is applied to the adder 25. When writing the output of the decimation filter 4 to RAMII, the control signal Z is “
In other cases, it is always "1".

By generating the address signal in this manner, it becomes possible to perform filtering for oversampling using the RAM 5 provided for data delay. Next, the coefficient ROM 13 stores tap coefficients for 128 taps having frequency characteristics as shown in FIG. 2B, and the tap coefficients are read out as shown in FIG. 6. That is, tap coefficients stored in even addresses are read out in the first half, and tap coefficients stored in odd addresses are read out in the second half. The data and tap coefficients of the RAM 11 read out in this way are held in the latches 12 and 14, respectively, and the multiplier 15
The multiplication result is accumulated by the accumulator 17. Thereafter, in the same manner as in the case of the decimation filter 4, the latch 18 outputs the output as an oversampling filter output. Since the coefficient ROM 13 stores coefficients having frequency characteristics as shown in FIG. 2B, 1
A digital signal with a sampling rate of 48 kHz from which components of 1.5 kHz or higher are removed is output. Therefore, the 11.
The aliasing noise of 5 to 12 kHz is removed at this stage, and a clean audio signal without aliasing distortion is obtained from the output of the oversampling filter 6.

As described above, since the RAM 5 provided for delay is also used for oversampling, the number of filter taps can be increased in the oversampling filter without increasing the filter size. Therefore, for example, if you want to perform equalization processing by giving the system as a whole some kind of frequency characteristic, if you use the oversampling filter 8 instead of the decimation filter 4, you can perform decimation, oversampling, and Equalization can be performed. Furthermore, since it is possible to increase the number of taps of the oversampling filter, even if the transition region of the decimation filter 4 is widened and the region of the oversampling filter 6 is made narrower, the difference within each band can be increased. Ripple and cutoff band attenuation can be made approximately the same for each filter.

Effects of the Invention As described above, the present invention is a delay device that converts an analog signal into a digital signal, delays the digital signal for a certain period of time, and takes out the digital signal. Convert it to a digital signal at a sampling rate higher than twice the band, decimate the converted output using an FIR filter, sequentially store the output of the FIR filter in a storage device, and sequentially store the stored contents from the storage device. By reading the data and converting it into an analog signal, a long delay time can be obtained with a small-scale storage device.

Further, the first FIR filter decimates the A/D conversion output, the output of the first FIR filter is sequentially stored in a storage device, the stored contents are sequentially read from the storage device, and the second FIR filter By performing oversampling and converting the output of the second FIR filter into an analog signal, the analog low-pass filters in the input and output stages can be simple.
Furthermore, since data is written to the storage device after lowering the sampling rate, it is possible to downsize the storage device.

Also, the output of the first FIR filter is stored in a storage device with a period T
A specific number of memory contents are read from the storage device during a period T, oversampling is performed by multiplying the read memory contents by a preset coefficient, and the oversampling output is converted into an analog signal. By converting the data into a signal, an oversampling FIR filter can be constructed without increasing the number of storage devices.

The second FIR filter also includes a second FIR filter that reads a specific number of stored contents from the storage device during a period T, and performs oversampling by multiplying the read stored contents by a preset coefficient; and a D/A converter that converts the output of the FIR filter into an analog signal,
The number of filter taps of the second FIR filter is
By making the number of filter taps larger than that of the R filter, the transition region of the FIR filter for oversampling is wider than the transition region of the FIR filter for decimation, and the FIR filter for decimator 1 can sufficiently remove the transition region. The oversampling FIR filter can remove signals in the band that cannot be processed, and as a result, high-performance filter characteristics can be obtained, which is an excellent effect.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the delay device according to the present invention, FIG. 2 is a frequency characteristic diagram of the decimation filter 4 and the oversampling filter 6, and FIG. 3 is a specific example of the decimation filter 4 and the oversampling filter 6. 4 is a timing diagram showing the operation of the decimation filter 4, FIG. 5 is a block diagram showing a specific example of the address generator 10 of the oversampling filter 6, and FIG. 6 is a timing diagram showing the operation of the oversampling filter 8. FIG. 7 is a block diagram showing a conventional example of a delay device. 1...LPFl 2...A/D converter, 3.
...Timing signal generator, 4...Decimation filler, 5...RAM, 6...Auto sampling filter, 7...D/A converter, LPF.

Claims (5)

[Claims] (1) 2 of the band required for the input analog signal
an A/D conversion means for converting into a digital signal at a sampling rate higher than 100%; and an FIR for decimating the output of the A/D conversion means;
A delay device comprising: a filter; storage means for sequentially storing the output of the FIR filter; and D/A conversion means for sequentially reading out stored contents from the storage means and converting them into analog signals. (2) Two of the bands required for the input analog signal
A/D conversion means for converting into a digital signal at a sampling rate higher than twice the sampling rate; a first FIR filter for decimating the output of the A/D conversion means; and a memory for sequentially storing the output of the first FIR filter. A second FIR filter that sequentially reads out stored contents from the storage means and performs oversampling; and a D/A conversion means that converts the output of the second FIR filter into an analog signal. delay device. (3) 2 of the required band for input analog signals
A/D conversion means for converting into a digital signal at a sampling rate higher than 2 times the sampling rate; and an FI for decimating the output of the A/D conversion means.
R filter; storage means for sequentially storing the output of the FIR filter at a period T; reading a specific number of stored contents from the storage means during the period T, and applying a preset coefficient to the read stored contents; A delay device comprising: oversampling means that performs oversampling by multiplication; and D/A conversion means that converts the output of the oversampling means into an analog signal. (4) 2 of the required band for input analog signals
A/D conversion means for converting into a digital signal at a sampling rate higher than twice the sampling rate; a first FIR filter for decimating the output of the A/D conversion means; a storage means for storing; and a second storage means for reading out a specific number of storage contents from the storage means during a period T, and performing oversampling by multiplying the read storage contents by a preset coefficient.
and a D/A conversion means for converting the output of the second FIR filter into an analog signal, the number of filter taps of the second FIR filter being greater than the number of filter taps of the first FIR filter. A delay device characterized by a lot of things. (5) The delay device according to claim 4, wherein the transition region of the first FIR filter is narrower than the transition region of the second FIR filter.