CN101331395A - Ultrasonic fault detection system - Google Patents

Abstract

A method and apparatus for effecting ultrasonic flaw detection of an object processes an echo signal received from the object being tested in at least three signal channels, wherein the echo signal is scaled to different degrees along each channel to increase and extend the dynamic range of an associated A/D converter system, in a manner which dispenses with the need for using numerous analog high pass and low pass filters and a variable gain amplifier. This reduces complexity and avoids performance limitations. The digital to analog converters sample the differently scaled input signal and a selection circuit selects the output of the digital output obtained from that analog to digital converter which has the highest gain, but which has not overflowed. The digital outputs are seamlessly merged to produce an output that can be displayed as a scan display which shows the location of faults.

Description

Ultrasonic fault detection system

Cross reference to related application

The application's requirement enjoys in submission on October 14th, 2005, the sequence number that name is called ULTRASONICFAULT DETECTION SYSTEM USING A HIGH DYNAMIC RANGE ANALOG TODIGITAL CONVERSION SYSTEM is 60/726,798 U.S. Provisional Patent Application, with submit on October 14th, 2005, the sequence number that name is called ULTRASONIC DETECTIONMEASUREMENT SYSTEM USING A TUNABLE DIGITAL FILTER WITH 4XINTERPOLATOR is 60/726,776 U.S. Provisional Patent Application, and submit on October 14th, 2005, the sequence number that name is called DIGITAL TIME VARIABLE AMPLIFIERFOR NON-DETRUCTIVE TEST INSTRUMENT is 60/726, the interests of 575 U.S. Provisional Patent Application and right of priority here openly are incorporated herein by reference the whole of them.

Background technology

The present invention relates in general to and is used to survey the inner structure defective, for example in object or the material, for example in the ultrasonic inspection system as crack, interruption, corrosion or variation in thickness in this key structure of flight wing.This is by to target object emission ultrasonic pulse, and analyzes that the echoed signal from this target object that detects realizes.More specifically, the present invention relates to can be used for the analog-to-digital system and method for high dynamic range in this ultrasonic inspection system, particularly whereby with ultrasonic probe or transducer scanning object.The invention still further relates to the eddy current inspection system that is used to survey the inner structure defective.

Ultra-sonic defect detector of the prior art with such as this directly the product of (instantassignee ' s) Epoch 4Plus product of assignee as example.Can be called USM 35X, USN 58L and USN 60 fault detection systems from the competitive products that General Electric obtains.Must, the ultra-sonic defect detector of prior art utilizes the AFE (analog front end) of high complexity, described AFE (analog front end) comprises a lot of parts, and there is insoluble especially problem in this part in calibration, reliability, setup time, result's consistance with to the aspects such as optimization of special applications and setting.

The ultra-sonic defect detector of common prior art comprises transducer, its with respect to want detected object place and with a large amount of mimic channel collaborative works, described mimic channel is such as gain calibration device, prime amplifier and attenuator, variable gain amplifier, and the high pass and the low-pass analog filter of operating and needing careful calibration and safeguard on a lot of different frequency bands.

As a result, current defectoscope brings a lot of problems for the deviser and the user of this equipment because their complexity, these problems affect their troubleshooting and maintenance.These problems comprise such as, the input impedance that will see by the transducer that changes be switched to and switch the problem that the different gains amplifier that signal path mates.This just causes the influence of not expecting to frequency response, and causes various nonlinear gains.This just causes when mimic channel and is switched to and switches calibration problem when signal path.

Another problem of existing defectoscope is attributable to their rear wall fade performance, and described performance impact is to the ability that the defective that is close to very much the object rear wall that is detecting is surveyed.This problem causes special problem concerning the time-varying gain function, described time-varying gain function has limited gain margin and change in gain rate in one type of prior art syringe.

The shortcoming of another prior art is caused by the mode that mimic channel is coupled, this causes for the full width of cloth scale (full amplitude scale) of the maximum that can use this converter, each operational amplifier in signal path has different DC offset errors, wherein for the input signal that remains on the analog to digital converter mid point is used, described DC offset error must make zero.And the DC offset error can be so that be presented on the center that waveform on the display is not positioned at the screen waveform portion in vertical direction, causes thus the operator to be used for analyzing and to determine that not expecting appears in the waveform of their check results unusual.Therefore error of the prior art (error nulling) process that makes zero is insecure, particularly when high-gain, because noise causes DC base measurement out of true, makes that this process is unreliable.

Owing to need utilize the whole dynamic range of used instrument, the intensive simulation of existing defectoscope front end realizes causing further problem,, it produces the problem of various gain linearity calibrations.

Ultrasonic inspection equipment of the prior art is in U.S. Patent No. 5,671, describes to some extent in 154, and it provides the background information that is used for present device and method.

Summary of the invention

Must, the purpose of this invention is to provide a kind of equipment and method that the ultrasound wave object is checked that be used for, it is avoided or improves aforesaid drawbacks of the prior art.

Further aim of the present invention provides ultrasonic inspection equipment and the method that the simpler circuit of a kind of usefulness is realized.

Further aim of the present invention provides a kind of ultrasonic inspection equipment and method that needs short and better simply calibration and adjustment process before use.

Further purpose of the present invention provides a kind of ultrasonic inspection equipment and method that electronics checkout facility and method are provided, and described electronics checkout facility is more accurate with the method transmission, more readability and consistent check result.

Aforementioned and other purpose of the present invention realizes with equipment by the following method, described method and apparatus expansion A/D converter circuit dynamic range, and eliminate needs and complicacy that is associated and performance limitations to variable gain amplifier (VGA) circuit.

According to an aspect of the present invention, equipment of the present invention and method are presented as a plurality of A/D circuit, and described A/D circuit comprises a plurality of being coupled to receive the passage of single analog input signal, and each passage has the device that analog input signal is converted to digital signal.

Another aspect of the present invention comprises: adjust each sampling number to compensate the device in all time lags (timingskew) source, described time lag source comprises the propagation delay of each prime amplifier and any other time lag source of disclosing by check A/D converter output data; Be used to prevent input phase saturated of each passage prime amplifier, in case the stop signal distortion effect is to the device to the input of other passage; The frequency response that is used to adjust each passage is with coupling basically, and the device of adjusting the whole frequency responses of this equipment; Be used for surveying one or more passages and overflow the device of situation with passage of higher gain; With the device that is used for a plurality of passages are merged into continuous output stream.

According to a further aspect in the invention, multichannel converter circuit of the present invention comprises, be used for by on each aspect of analog signal path, injecting DC signal from D/A converter, thereby eliminate the device of the signal bias error in each passage with (nullout) offset error that makes zero.

According to a further aspect in the invention, the device that is used to merge a plurality of passages operationally is used for being overflowed by passage the result's that the situation sniffer generates function.And operationally when the passage situation of overflowing was detected on any passage with higher gain, output had the passage result than low gain to the device that is used to merge a plurality of passages.

According to a further aspect in the invention, the device that is used for mating basically each analog channel frequency response is provided for the amplitude matching error that minimizes between the passage, particularly at high frequency.

According to a further aspect in the invention, each A/D converter circuit comprises and being used for by using D/A converter that the change reference voltage is to adjust the device of full scale range.This is used for optimization signal amplitude coupling.

According to a further aspect in the invention, a plurality of A/D converter circuit of the present invention comprises and is used for device that the result and the different gains of each passage are mated.

According to a further aspect in the invention, thereby also comprising the sampling clock that is used in time adjusting a passage, a plurality of A/D circuit of the present invention the sampling number of each passage is adjusted, the device in any other time lag source of disclosing with the propagation delay that compensates each prime amplifier passage with by check A/D converter output data with respect to the position of the rising edge of other channel clock circuit part.

According to a further aspect in the invention, passage overflows the situation sniffer and comprises that further all amplifiers of signal path that are used in order to ensure the amplifier from first amplifier to A/D converter inside have time enough to turn back to the range of linearity of their operations, prolong the device from the spill over duration of A/D converter.

According to another aspect of the invention, the device that is used to merge a plurality of passages further comprises and is used for adjusting, one or more data bit positions that have than the result of the passage of low gain of convergent-divergent for example are so that coupling has one or more passage results' of higher gain device.This can be by for example utilizing shift register, multiplexer etc. or utilizing any way to be shifted and finish.

In accordance with a further aspect of the present invention, being provided for analog signal conversion is the method for digital signal, and it comprises that for example will import simulating signal assigns to bigger and less signalling channel; Convergent-divergent input signal on bigger and less signalling channel makes less signalling channel have higher resolution with comparing than the large-signal passage; Utilize the bigger and less signalling channel of A/D converter sampling of separating; And one of them result of the bigger and less signalling channel of output, as definite than large-signal passage efficient function whether.

Method of the present invention also comprises and will merge the result after obtaining merging than the result of large-signal passage and the result of less signalling channel; And the result after the output merging.

Other features and advantages of the present invention will become obvious according to the description of with reference to the accompanying drawings the present invention being carried out.

Description of drawings

Fig. 1 is the block diagram of the basic configuration of ultrasonic inspection equipment.

Fig. 2 is the basic waveform figure that is used for device shown in Figure 1.

Fig. 3 is the oscillogram that ultrasonic pulse negative edge feature is shown.

Fig. 4 provides the block diagram of the contrast arranged side by side of defective locations in waveform demonstration and the target object.

Fig. 5 is the continuity of Fig. 4.

Fig. 6 shows the circuit block diagram that ultrasonic inspection equipment is realized in the prior art.

Fig. 7 is the circuit diagram according to the digital intensive realization of ultrasonic inspection equipment of the present invention.

Fig. 8 a and 8b are another block diagrams of another realization of the present invention.

Fig. 8 c is corresponding to Fig. 8 b, but comprises the DC migration of pure digi-tal.

Fig. 8 d and 8e be corresponding to Fig. 8 b, but utilize amplitude comparator to replace overflow indicator, and Fig. 8 e adds digital baseline correction.

Fig. 8 f and 8g be corresponding to Fig. 8 b, but add baseline correction in each passage.

Fig. 8 h is corresponding to Fig. 8 b, but comprises delay circuit, is used to handle the input signal of quick conversion (slewing).

Fig. 9 shows the circuit block diagram of the optional embodiment that is used for fore-end that Fig. 7 paints.

Figure 10 is the signal graph that is used for explaining some notion that is applicable to Fig. 8 d, 8e and 8h circuit operation.

Figure 11 is the block diagram of the hybrid circuit that is associated with Fig. 8 d.

Embodiment

Beginning provides the background information about the variety of issue of general environment and the present invention's solution earlier with reference to Fig. 1 and 2.

In Fig. 1, ultrasonic emitting-receiving element 10 is during predetermined, directly or by such as water or quartzy delay material, to being coupled to such as probe on the target object 14 of steel or transducer 12 emission electric impulse signal 10a.As shown in Figure 2, probe 12 is converted to start pulse signal 12a by target object 14 ultrasonic waves transmitted pulse 10a.The ultrasonic pulse 10a that is applied on the target object 14 is reflected by the basal surface 14a of target object 14 subsequently, and is received by probe 12.Probe 12 is converted to electric signal with reflection wave, and described electric signal is used as electric echo signal 10b and offers ultrasonic emitting-receiving element 10.Ultrasonic emitting-receiving element 10 amplification signal 10b, and amplifying signal 11 is transmitted into signal processing apparatus 16 as echoed signal 11.Just as used herein, term probe or transducer comprise the embodiment that utilizes different transmitter and receivers to realize transducer.

Echoed signal 11 comprises corresponding to the basal surface echo 11a of the ripple that is reflected by basal surface 14a and the flaw echo 11b that is caused by the defective 14b in the object 14.In addition, the frequency of ultrasonic echo pulse 11 is mainly determined by the thickness that is combined in the ultrasonic oscillator in the probe 12 or other characteristic.The frequency of the ultrasonic pulse 10a that is used to check is set to tens KHz to tens MHz.Therefore, the signal waveform frequency range that is included in basal surface echo 11a in the echoed signal 11 and flaw echo 11b covers the wide region from about 50KHz to tens MHz.

16 pairs of echoed signals 11 that receive from ultrasonic emitting-receiving element 10 of signal processing apparatus are carried out various signal Processing, and signal processing apparatus 16 shows that on display unit 18 exist/there is not and represents in some cases the output result of target object 14 thickness in the expression defective.For echoed signal 11 is carried out signal Processing and shown this echoed signal, the trigger pip S synchronous with pulse signal 10a is provided to signal processing apparatus 16 from ultrasonic emitting-receiving element 10.

In the defect inspection equipment of arranging as mentioned above, except basal surface echo 11a and flaw echo 11b, also comprise the noise of some from the echoed signal 11 of ultrasonic emitting-receiving element 10 outputs.When the amount of noise in being included in ultrasonic pulse 11 was very big, the reliability of check result was greatly diminished.Noise is divided into electrical noise and material noise roughly.

Electrical noise comprises the external noise that causes by the stube cable of electromagnetism or electrostatic wave being sneaked into probe 12, ultrasonic emitting-receiving element 10, for example cable 13 etc., and by being combined in the internal noise that amplifier in ultrasonic emitting-receiving element 10 etc. generates.

Reduce the noise be included in the echoed signal 11 for extremely important so that pinpoint accuracy is carried out ultrasonic examination.Usually, analog filter is used for reducing the noise component that is included in echoed signal 11.For example, BPF (bandpass filter) is used for by the frequency component with respect to the ultrasonic echo of the electrical noise with wideband component.And LPF (low-pass filter) or BPF are used for the material noise, and the frequency distribution that identifies flaw echo 11b (Fig. 2) is lower than the frequency distribution of the echo that signal dispersion produces.By this way, when using analog filter, the noise component that is included among the echoed signal 11b can be reduced to the level that is equal to or less than the level of pre-determining.

Usually be known that flaw echoes frequency distribution based target object 14 the ultrasonic attenuation feature and change.Therefore, when BPF will be used to material noise by expression such as scatter echo, the wave filter expectation with optimal characteristics was used according to target object 14.Yet, because the frequency of analog filter can not easily change by feature, so must prepare to have the wave filter of different frequency by the more more number of feature, described different frequency is by the different ultrasonic attenuation features of feature corresponding to the various materials that are associated with target object 14.By this way, when different wave filters are used according to the material characteristics of target object 14, with respect to the cost of total system and complexity and when considering operability or advantage economically, practical difficulty occurs.

In some cases, flaw echo 11b can be in close proximity to the front surface 14c of target object 14, and described object is known from experience on the negative edge that places it near transponder pulse 10a.For this reason, in order not disturb the flaw echo 11b that returns, expectation transponder pulse 10a negative edge (being enlarged into negative edge 10at in Fig. 3) end can sink to zero base line 10ab as quickly as possible.7a Time Created that arrives zero base line is the deciding factor of the nearly surface resolution of defectoscope.

The gain of considering ultrasonic emitting-receiving element 10 can be adjusted high to 110dB (desired as European standard EN 12668-1), if gain level is set up too high, a small amount of lubber line error in ultrasonic emitting-receiving element 10 before the gain amplification stage will cause the mistake in output place of gain amplification stage.

The lubber line error that obtains in input to signal processing apparatus 16 can:

(a) cause dynamic range to reduce, because the side-play amount of the signal maximum perpendicular displacement on screen will minimizing baseline, this will make instrument reduce for the sensitivity of detecting defects echo, perhaps

(b) if enough high in amplitude, cause one or more gain amplification stages saturated, stoped echoed signal to be detected thus fully.

Usually, above-mentioned lubber line error problem is solved one of in two ways.According to first method, for the low-frequency content of filtering transponder pulse 10a negative edge 10at, HPF is used in the signal path of ultrasonic emitting-receiving element 10 inputs.The negative edge 10at of transponder pulse 10a can improve by the HPT shown in contiguous dotted line 7c.

Yet the validity of HPF solution is restricted in several modes.At first, HPF cutoff frequency (f HPF-3dB) must be high as much as possible, so that minimize the low-frequency content of transponder pulse 10a negative edge 10at.For example, if the stimulating frequency of probe 12 is that 10MHz and f HPF-3dB are 5MHz, then the influence of not expecting to the receiver baseline will significantly reduce.

Unfortunately, right and wrong are not with ordinary for probe 12 uses the stimulating frequency that is low to moderate 500kHz, and this will require f HPF-3dB below 500kHz.The HPF solution has been lost its a lot of validity in this frequency range, because a large amount of transponder pulse 10a negative edge 10at low-frequency content of not expecting are allowed to by HPF and bring lubber line error.

Second point, in order to prevent the infringement of pair amplifier circuit, the exomonental amplitude peak that is applied to ultrasonic emitting-receiving element 10 first amplifer stage (not shown) is limited (clamp) at several volts.The gain that will cause operating on the saturated level of amplifier ultrasonic emitting-receiving element 10 when pulse producer is lighted each time is very common.If wave filter no show critical damping is then walked out filter response after saturated and will be made the negative edge of transponder pulse 10a become poorer when not using filtering.For the instrument of each manufacturing, have in a large number by tuning wave filter to guarantee that critical damping is possible; Yet, when the manufacturability of considering filter assembly and temperature drift, practical difficulty appears.

In case it is saturated to be to be further noted that amplifier enters, will spend the plenty of time to make amplifier turn back to the linear operation zone.This just causes in order to make transponder pulse 10a negative edge turn back to zero base line, and the situation that is maintained at (promptly within linear opereating specification) below the saturated level such as the fruit amplifier input signal will spend the more time.

The optional method that is used to solve the lubber line error problem is the input that the transponder pulse 10a of clamp is directly coupled to ultrasonic emitting-receiving element 10.This method has been avoided one of them the problems referred to above, because do not use HPF or BPF wave filter.

Directly the validity of coupling solution is subjected to the restriction of two aspects.At first, it is of no use for the low-frequency content that reduces transponder pulse 10a negative edge 10at.Secondly, the DC component of lubber line error and the amplifier offset error of ultrasonic emitting-receiving element 10 are by signal path and be exaggerated.This can cause the various dynamic ranges and the saturation problem that further describe.

Usually, defectoscope provides to have permitted a user to the defectoscopy situation selects optimum setting, utilizes wave filter or comes operating instrument by direct coupling.

Referring now to the detection of Fig. 4 description to the defective of close object 14 back surfaces.In some cases, defective 14d can will make flaw echo 11b closely near rear wall echo 11a very near the far away surperficial 14a of target object 14 like this.In order to realize correct inspection (according to a lot of regular checking processes), as seen the peak value of rear wall echo 11a must remain on the waveform oscilloscope 18 always.Such reason is: 1) the little defective 2d that is caused by poriness or material contamination in the target object 14 can produce flaw echo, described flaw echo is not large enough to and can sees from waveform oscilloscope 18, but can reduce to arrive the echo amplitude of rear wall 14a, make the amplitude of flaw echo 11b and rear wall echo 11a reduce thus, with 2) probe 12 will be coupled to the surperficial 14c of target object 14 discontinuously improperly, reduces the amplitude of rear wall echo 11a thus.Both of these case will make that the echo of defective 14d can not be on waveform oscilloscope 18 as seen.Yet the minimizing of rear wall echo 11a will indicating target object 14 materials or probe 12 coupling problems.If the peak value of rear wall echo 11a is allowed to surpass waveform oscilloscope 18 top visible parts, then the minimizing of peak amplitude can not be on waveform oscilloscope 18 as seen.The people who implement to check is provided with zone on the horizontal time axis that rear wall echo 11a can be allowed to by adjustment rear wall echo door 6d (referring to Fig. 4), sets up rear wall echo 11a detecting parameter.Threshold value on the vertical size axle also is minimum acceptable echo amplitude setting.Usually, when rear wall echo 11a falls beyond these parameters, will report to the police.

This measuring method has been brought some problems.

Echo amplitude difference possibility huge (arriving several amplitude orders of magnitude greatly) between flaw echo 11b and the rear wall echo 11a.But the several method that describes below (a, b, c and d) can be used for guaranteeing the peak value of flaw echo 11b and rear wall echo 11a and all remains on the waveform oscilloscope 18 as seen:

(a) probe 12 is connected to two parallel receivers and A/D converter passage (A and B).The gain of passage A is adjusted by the people who implement to check so that the echo amplitude of optimization defective 14d, make its can be clearly on waveform oscilloscope 18 as seen.For foregoing reason, the gain of channel B is adjusted, and remains on the waveform oscilloscope 18 as seen with the peak value of guaranteeing rear wall 11a echo.

The output of the numeral of passage A and BA/D converter is combined in such a way, promptly except the zone of rear wall echo door 6d, and whole outputs of the whole leveled time yardstick display channel A of waveform oscilloscope 18.The time point of the switching from passage A to channel B takes place in the leftmost side indication of rear wall echo door 6d.

Unfortunately, there is shortcoming in this two passage methods.Usually, by probe 12 is moved realization inspection along target object 14 surfaces in scanning motion, because the existence or the position of defective all were unknown before it is detected out in the target object.If target object in scanning area front surface 14c and rear surface 14a between do not have constant thickness, then in order not miss the detection to rear wall echo 11a, rear wall echo door 6d is adjusted needs enough wide, so that comprise the variation on this thickness.

Therefore, if closely rear wall flaw echo 11b is very near rear surface 14a, then it can not be detected, because rear wall flaw echo 11b will occur in the rear wall echo door 6d zone.This makes surperficial 14a far away produce the influence of not expecting to nearly surface resolution.And the quantity of receiver hardware is the twice near the required receiver hardware quantity of single passage scheme.

(b) except passage of needs, two continuous impulse reception measurement round-robin methods are similar with the notion of A/D converter passage method to two parallel receivers.Above description in (a) part be applied to two continuous impulses and receive the round-robin methods of measuring.And, not in two parallel channels that are set to different gains, to handle flaw echo 11b and rear wall echo 11a, echo is processed in same passage, then another reception of impulse circulation after the reception of impulse circulation, but each circulation has different gains.

Continuous impulse receives and measures the exclusive shortcoming of round-robin method is that flaw echo 11b separates (referring to Fig. 2) by additional recurrent interval To with rear wall echo 11a in time.Therefore, measuring error more likely takes place when probe 12 is moved, because its position may change between the measured time at flaw echo 11b and rear wall echo 11a.

(c) time-varying gain (TVG) is the single channel scheme, and wherein the amplifier gain of ultrasonic emitting-receiving element 10 is dynamically changed, with the amplitude (owing to the reason of having described) of optimization flaw echo 11b and rear wall echo 11a.

The same with the A/D converter passage method with two parallel receivers, the TVG method has the same shortcoming that is caused by surperficial 14a far away for nearly surface resolution.

But also there is other shortcoming that is associated with the TVG method.Therefore, Fig. 5 shows desirable TVG curve 6e, and described TVG curve changes to gain 6h immediately from gain 6f, does not introduce additional nearly surface resolution error from analog TV G amplifier thus.Described in above-mentioned method, will still keep near the error that the defective with target object rear wall of non-constant thickness is associated with measurement.

Unfortunately, the analog TV G amplifier curve 6e (particularly instantaneous inclination (instantaneous slope) 6g) that can not realize ideal.Analog TV G amplifier and their external signal of control have the response time of limiting gain rate of change 6g, cause the influence of not expecting to nearly surface resolution that is brought by surperficial 14a far away thus.Because for time interval 6m is provided for change in gain, the back side 14c of the necessary wide object 14 of defective 14d is so nearly surface resolution descends.According to relevant echo in fact, flaw echo 11b must take place before time interval 6m begins, and rear wall echo 11a necessarily can not take place before time interval 6m finishes.

The other problem that is associated with the TVG method is to be caused by the various DC offset errors source in ultrasonic emitting-receiving element 10 receiver sections.These sources comprise the input DC offset error of amplifier IC and the DC component of lubber line error.

The DC offset error that the existing defectoscope of some of this assignee exists is gaining each time by from a horizontal adjustment during to next level, is provided with in each gain to be compensated.The DC offset error is compensated by this way, to consider the influence of the drift etc. on temperature, long-time stability, the DC offset error.The compensation method utilization is injected DC null value (null) signal along several D/A converters in receiver signal path, and described DC signal value of zero will guarantee that baseline remains on the center of A/D converter full scale range, and is in the optimal location on the waveform oscilloscope 18.Open instrument each time, perhaps gain setting is changed, and algorithm moves in the microprocessor of carrying out the lubber line error reading, calculate required DC error correction value, and DAC is set to this value.

With the speed that TVG need move, be unpractiaca for each gain is provided with the above-mentioned DC offset compensating method of execution.Otherwise the DC offset correction is that the mid point gain is provided with, thus with the error between the terminal point separately.For example, if the TVG scope is set to move between 20 to 60dB, then the DC offset correction is set to compensate the error at the 40dB place.The problem of this technology is, it is incorporated into error in the echo amplitude, and this does not expect accurate flaw detection and dimensional measurement.

(d) logarithmic amplifier is used to cover required huge dynamic range, and echo is displayed on the waveform oscilloscope 18 with logarithmically calibrated scale.Logarithmically calibrated scale provides very high dynamic range, thereby makes that the peak value of low amplitude flaw echo and much higher amplitude rear wall echo can both be on waveform oscilloscope as seen.

Unfortunately, the consequence that some is not expected takes place when using counting method.Therefore, concerning given rear wall echo amplitude and changes in amplitude, and compare for the receiver that uses linear amplifier, the vertical change of echo waveform peak value is more difficult being noted on waveform oscilloscope.This just makes as previously described the peak amplitude that passes through to observe the rear wall echo change to come the detecting defects difficulty more that becomes.

And the output of logarithmic amplifier can only provide revised waveform.Therefore, the position of negative echo lobe can not be identified because itself or be removed by the half-wave correction, perhaps be converted into positive lobe by the all-wave correction.The exact position of positive negative echo lobe is extremely important for the thickness of accurate measurement target object 14, because a lobe may be more visible than other lobe.Also need the polarity of echo lobe to determine when the paraphase of generation echo.The paraphase of ultrasonic echo occur in when sound wave when low acoustic impedance material passes to high acoustic impedance materials.

And all wave filters must be positioned in before the logarithmic amplifier part, because wave filter needs linear signal to come proper operation (logarithmic amplifier is a non-linear device).If filter circuit is positioned in before the high-gain logarithmic amplifier part, then receiver will have the much higher sensitivity to noise, because the PCB cabling (traces) that need be used for filter assembly is linked together is to the electromagnetic noise sensitivity, and the internal noise that is generated by filter amplifier will be amplified the biglyyest.These problems of logarithmic amplifier improve in the present invention, because the full dynamic range of sampled data is provided at each sampling clock on the cycle, makes it can be used as linear scale or logarithmically calibrated scale thus and are presented.Therefore, the present invention makes the operator can command system, and for example previously described FPGA selects and development linearity or the output of logarithm system in order to show on display 18, perhaps stores these outputs to be used for the analysis of back.

The present invention is intended to improve or avoid shortcoming of the prior art, and in fact, it is equal to the A/D converter of 24 of 100MHz substantially, and the big input voltage work of described A/D converter utilization does not have other shortcoming of DC skew, lubber line error and prior art.Notice that the following fact is important, although i.e. the present invention utilizes the performance of the A/D converter that is equal to 24 of 100MHz substantially to realize, as mentioned above, it can also be respectively realized with other sample frequency and resolution except that 100MHz and 24.Its utilization operates in three (or more) A/D converters in the respective number passage.This direct inventor recognizes that the final development of multi-functional operation A/D converter will allow to use the A/D converter of lesser number.

Block diagram among Fig. 6 shows the more detailed form that has been used to realize the ultrasonic inspection system in the circuit of prior art.This intensive mimic channel is used to the signal from transducer 12, it is presented to a series of parallel amplifier/attenuators 28,30,32,34 and 36 that provide by the switch 24 that can select to import as one, described amplifier/attenuator have respectively 14dB, 0dB ,-8dB ,-14dB and-gain separately of 20dB.Switch 24 is gone back the input of receiving gain calibrating device 20, and its signal is directly offered attenuator 32,34 and 36, and offers amplifier 28 and 30 via switch 26.

Variable gain amplifier (VGA) 40,42 and 44 receives their inputs respectively from amplifier 28,30 and switch 29, switch 29 provides selected one of them the output 31 that constitutes attenuator 32,34 and 36 outputs.The output of VGA is provided for switch 46, described switch also receives from the signal of gain calibration device 22 and one of imports as it, and selectively these signals being offered a series of Hi-pass filters 50,52,54,56,58,60,62 and 64 by bus 48, their output is switched to low-pass filter 70,72,74,76,78,80,82 and 84 by switching network 66.Like this, by controlling to the selection of wanting signal by switch 66 and 67, from VGA 40,42 and 44 or can be fed from the signal of gain calibration device 22, it is provided to further downstream VGA 86, the output of VGA 86 is further provided amplifier 90 by switch 92.

The output of the output of amplifier 90 or gain calibration device 94 finally is fed to modulus (A/D) converter 100 of 100MHz10 position then.

Field programmable gate array (FPGA) 106 will be surveyed and compressor circuit 104 with the measurement gain in conjunction with real-time sampling Data Control and memory circuit 102, to be provided to the output of digital signal processor and control 110, its setting of also controlling FPGA 106 is to obtain the output of the appropriate analog to digital converter of handling 100, time-varying gain control is provided, and produces the signal that can on display 18, show.

Consider introductory discussion, it is evident that, calibrate various mimic channels preventing inconsistency and variation, and the task of avoiding DC skew and drift and analogue means temperature effect is brought a large amount of challenges to the deviser and the user of circuit in the prior art owing to the different spectral response of a large amount of high passes and low-pass filter.

Roughly relatively illustrating of block diagram of the present invention shown in Figure 7 seldom used the mimic channel that easily goes wrong among the present invention, it utilizes ternary A/D passage, avoided a lot of shortcomings and complexity in the prior art like this.

In the block diagram of Fig. 7, when switch 114a was closed, transducer 12 made its output 13a directly only be offered two prime amplifiers 110 and 112, and latter's amplifier is presented the 3rd amplifier 122.The signal of these amplifiers is handled in frequency response fine setting and filter module 116,118 and 120 respectively, and next is provided for differential amplifier driver 126,128 and 130 along three passage A, B, C.Directly offered A/D converter 132,134 and 136 respectively then along this three-aisled simulating signal, their numeral output is provided for field programmable gate array 140 then successively, and described field programmable gate array 140 combines control and surveys and synthetic A sweep compressor circuit 152 with memory module 142, time-varying gain 146 and measurement door.This FPGA140 and DSP 160 collaborative works, DSP 160 offers display 18 with its signal.

Embodiment among Fig. 7 (its function and feature are gone through about the description of Fig. 8 a and 8b below) has saved most of mimic channels, and overcome the shortcoming of prior art, comprise and use analog high-pass and low-pass filter, booster amplifier and calibrating device and various VGA circuit thick and fast, according to the circuit of Fig. 7,8a and 8b, all these shows as unnecessary.

Therefore, as Fig. 8 a and 8b further shown in, the present invention is equipment and the method that is used for expanding the A/D converter circuit dynamic range of using at defectoscope, thickness or corrosion measurement instrument, and it has been eliminated for the needs of variable gain amplifier (VGA) and complexity that is associated and performance limitations.Equipment of the present invention and method are utilized three A/D converters, and they are sampled to the form of three different scales of same input signal on different passages.The sampling number of each passage is adjusted, and to compensate the propagation delay of each prime amplifier passage, minimizes the signal skew timing errors (skew error) between each A/D converter sampled data output.Scale is that to make that maximum gain passage (C) has higher 32 times than medium gain passage (B), and than the high 1024 times resolution of least gain passage (A).The passage of high-resolution is monitored data and overflows, the selected conduct output of passage that has the highest resolution data and do not overflow.Selected output is merged, to produce seamless output stream.The output that obtains is that its quantization step is bigger to large-signal, and the data stream little 32 or 1024 times to small-signal.Eliminated traditional VGA control analog input signal level by the level of dynamic range provided by the invention thus, remained on or near embodiment the endscale value of A/D converter input with crest voltage level with analog input signal.

When sampling with circuit shown in Fig. 8 a and the 8b, be divided into two passage 19a and 19b from the input signal of transducer 12, have and be exclusively used in each buffer separately of passage separately.Like this, each buffer memory amplifier 110 and 112 utilizes the 0.1 (gain of gain 20dB) and 3.2 (10.1dB) amplification input signal 13a on passage separately respectively.The output of buffer memory amplifier 112 is connected to the input of buffer memory amplifier 122, has the third channel of 102.4 (40.2dB) gain with generation.Each passage is sampled by one of them of three essentially identical A/D converters 132,134 and 136.Three passage A, B, C utilize the time delay between them and are sampled, with the input signal skew timing errors that propagation delay caused of compensation by all amplifiers in the analog signal path.Time delay is controlled by the clock CLKA, the CLKB that drive A/D converter, the rising edge of CLKC, and described clock is adjusted with calibration algorithm.

In the embodiment that is realized by reduction, sampling timing adjustment is divided into two parts.

A) coarse adjustment: utilize a FIFO and the control circuit that is used for each A/D passage, data are delayed the selectable integer clock period.

B) fine tuning: four phaselocked loops (PLL) of operation with respect to 0,90,180,270 phase angles of clock are arranged.By being that each A/D independently selects PLL output, the step-length that the clock timing of each A/D can 1/4 clock period and being adjusted.

If the translation data of maximum gain passage (C) is effective, then its result does not pass through with being had modification, as the output 132OUT (Fig. 8 b) of triple channel A/D converter circuit.If the translation data of maximum gain passage (C) is overflowed, then its result is dropped, and, if the translation data result of medium gain passage (B) is not overflowed, then it passes through, scaled with to buffer memory amplifier 112 gain proofread and correct and be used as output 134OUT.If the translation data of medium gain passage (B) is overflowed, then its result also is dropped, and the translation data result of least gain passage is scaled so that signal path gain is proofreaied and correct.This scalar gain is calculated as:

The gain of the gain of the gain of buffer memory amplifier 112+buffer memory amplifier 122-buffer memory amplifier 110, it is used as output 136OUT then.

In the embodiment shown in Fig. 8 a and the 8b, triple channel A/D converter circuit of the present invention can: eliminate the signal bias error in whole three split tunnels; By use three independently each buffer memory amplifier channel that is set to different gains come the convergent-divergent input signal; On adjustable sampling number separately, will be converted to digital signal for each the simulating signal input of three split tunnels for the compensated input signal skew timing errors; At least detection channels overflows situation in having the passage of higher gain; Merge the A/D converter output of three passages in real time.

As above mentioned, be directed to two signal clamped amplifier passages, wherein the big predetermined factor of gain of the ratio of gains first passage 110 of second amplifier 112 in two amplifier channels from the analog input signal 13a of transducer 12.It is 32 amplifier 122 that the output of channel B amplifier 112 is connected to downstream filters 118 and gain, to generate channel C.For example, passage A has 0.1 gain, and channel B has 3.2 gain, and channel C has 102.4 gain.Like this, compare each other, passage A and B difference are 32 gain factor, and channel C and B difference are 32 gain factor, and passage A and C difference are 1024 gain factor.

Be used for the output that level that the clamping voltage threshold value of amplifier 110 and 112 is set up obtains and exceed the A/D converter 132,134 of each passage A, B and C and effective input range of 136 slightly.Clamp circuit 111a, 111b and 113 also limit the input voltage to the gain channel amplifier, and be saturated to prevent that them from entering.

Prevent amplifier saturated be very important because in case enter saturatedly, amplifier will turn back to its linear operation zone the expensive time.Become saturated by the amplifier in the passage that prevents to gain, the time span of the A/D converter of higher gain under the situation of overflowing is minimized, and makes that thus higher resolution output data can comparatively fast be used.Clamp circuit in the prime amplifier 112 also is used to input signal 19a to keep constant input impedance, and no matter the input signal level is high to the signal level that is higher than the 110 maximum inputs of passage A prime amplifier.If constant input impedance is not held, the then input signal distortion that will become.

The inventor recognizes that amplifier 122 does not need clamp 113 to remain on the constant input impedance of transducer 12 on its signal amplitude opereating specification, because amplifier 122 is isolated with transducer 12 by amplifier 112.For this reason, provide if desired such as lower-wattage or than other advantage of low circuit complexity, then other amplifier circuit configuration can be used to amplifier 122.

In the embodiment that is realized by reduction, channel C amplifier 122 is allowed to saturated and uses fast quick-recovery OpAmps.Preferably, clamp can be added so that generate less noise.

The output of each gain channel amplifier 110,112,122 is connected respectively to frequency response fine setting and filter circuit 116,118 and 120.Control signal 116a is adjusted in frequency response, 118a, 120a are respectively applied for the frequency response that makes passage A, B and C and as far as possible closely mate.This need guarantee that interested all signal frequencies and same gain keep tight as far as possible.The calibration algorithm response that is used to adjust frequency, as mentioned above.This frequency trim method can be used for two or more analog to digital converter passages.

Anti-aliased (anti-aliasing) filter function that is used for passage A, B and C is distributed in frequency response fine setting ﹠amp respectively; Wave filter 116,118 and 120 and differential amplifier 126,128 and 130 in.

Intrinsic DC skew is compensated by injecting DC signal 112a, 122a, 126a and 128a in the amplifier of each passage, appears at DC offset error on the whole analog signal path with balance.Calibration algorithm is used to realize this compensation.Should be noted that this DC offset compensating method has following two restrictions:

1) on very fast pulse producer/receiver repetition rate (Fig. 2 " arriving "), " to " do not have between the cycle the sufficient time to can be used for realizing that the DC offset drifts in time compensates needed DC offset correction process.Having limited the DC offset calibration does not so only take place when this instrument is measured.

2) be provided with in very high gain, remaining on little DC offset error after the balance will be in the sampled data of storage and therefore be presented in the waveform on the display and produce significantly skew.

In order further to improve the influence that appears at the DC offset error on the whole analog signal path, comprise the influence of describing in top the 1st and the 2nd, present embodiment comprises pure digital DC offset compensating method, and its block diagram has been shown among Fig. 8 c.

With further reference to Fig. 8 c, the output of A/D converter 136 is provided for baseline trapping module 146 during interval 10c shown in Figure 3.Sampled point from interval 10c is used to monitor baseline, because they in the time zone of relative " peace and quiet ", promptly occur in before the pulse producer igniting and zone afterwards will appear in the ultrasound wave response signal of essence amplitude.In the present embodiment, baseline trapping module 146 utilizes 256 integer sampled point and calculating mean values that symbol is arranged; Yet, can use the sampled point of different numbers.The integer output of baseline trapping module 146 that can allow symbol by control signal 149 when multiplexer 147 is during by baseline corrector module 148, and signal 147a is deducted from the integer signal 145a that symbol is arranged to remove lubber line error.Register 150 attempts to allow selectable bias control value to be used, and described bias control value can be generated by software algorithm or unshowned hardware unit.

The A/D converter 132,134 and 136 of three passages is high-speed converters of 14, provide the sampling timing with sampling clock CLKA, CLKB, CLKC for them, described sampling clock is to utilize the respective delay control element that is included in the FPGA circuit, derives from the oscillator module 131 of 100MHz.Postpone control element and allow in time adjust the position of the sampling clock of a passage, make the sampling number of each passage be adjusted with the propagation delay that compensates each prime amplifier passage and any other time lag source of disclosing by inspection A/D converter output data with respect to the rising edge of other channel clock circuit part.Calibration algorithm is used to realize this compensation.

As previously mentioned, in the embodiment that is realized by reduction, sampling timing adjustment is divided into two parts.

1) coarse adjustment: utilize a FI FO and the control circuit that is used for each A/D passage, data are delayed the selectable integer clock period.

2) fine tuning: four phaselocked loops (PLL) of operation with respect to 0,90,180,270 phase angles of clock are arranged.By being that each A/D independently selects PLL output, the step-length that the clock timing of each A/D can 1/4 clock period and being adjusted.

The inventor considers by using aforesaid meticulous simulation adjustment to adjust the optional method of sampled data timing in conjunction with rough numeral.Adjustable signal delay component will be used to adjust the timing rather than the digital dock timing method of adjustment recited above of simulating signal.This delayed analog signal can be finished by using following wherein any one method.

1) have the lag line of tap, tap is selected for to adjust by switch and postpones.

2) delay filter element is switched to as required or switches and signal path.

3) utilize variable element, such as the adjustable delay of the all-pass delay filter structure that utilizes the Control of Voltage assembly.Delay can be by DAC control to provide very fine control.The inventor recognizes that this method provides best adjustment resolution.

The method of coming the calibration system gain by the full scale range of adjusting A/D converter 132,134 and 136 also is provided.This is to finish by the reference voltage (not shown) that utilizes the D/A converter (not shown) to adjust each A/D converter.Calibration algorithm is used to realize this function.

A/D converter 132,134 and the output of 136 numeral are connected to digital multiplex circuit 135.The spill over that is used for two higher gain A/ D converters 134 and 136 is connected to channel selecting logical circuit 137.Provide the time in order to walk out in A/ D converter 134 and 136 inputs for all amplifier circuits before saturated, channel selecting logical circuit 137 also prolongs the duration from the spill over of A/D converter 134 and 136.This circuit 137 is selected output data bus from the highest-gain passage A/D converter that does not overflow as yet.If whole three A/D converter passages all overflow, then the output data bus of lowest gain passage A/D converter is selected, because it will be first passage of walking out the situation of overflowing.

Channel selecting logical circuit 137 and be connected to index generator circuit 139 from the spill over of A/D converter 132.The index that selected A/D converter data among these circuit 139 calculating and the RAM 141 accompany.Floating-point change-over circuit 143 adds accurate position to the A/D conversion that is used for small-signal effectively, and is large-signal hold in range capacity.Floating-point converter 143 has also reduced the figure place that sampled data RAM needs.Sampled data RAM has 18, and wherein 14 are used to mantissa, and 4 are used to index.When sampled value was stored, selected A/D converter value was stored in the mantissa, and 0,5 or 10 exponential quantity is stored in the index numerical range with designation data.Index also can be set to 15, all is under the situation of overflowing to indicate whole passages.And when data were read from sampling RAM 141, index was used to data locking in mantissa, to make up 24 the integer outputs of floating-point to integer converter 143.This is final output 145 of the present invention.This output can be by following formulate:

Output 145=2 ^Index* mantissa=24 integer

Although about utilizing three signal processing channels, each passage is described in conjunction with the embodiment of its analog to digital converter separately in the present invention, this direct inventor also attempts to use fewer purpose analog to digital converter or even single analog to digital converter.Like this, if the analog to digital converter that for example is operated on the 200MHz can be used, two passages so wherein can be handled by single analog to digital converter, and described analog to digital converter produces two continuous quick samplings of same signaling point.For this reason, first sampling of signal can be acquired, and the amplification form of same signal is delayed (using the analogue delay time) one section time delay that approximates the 200MHz analog to digital converter clock period greatly simultaneously.The amplifying signal that is delayed is then sampled by same A/D converter.And analog comparator can be used to the signal amplitude of comparison prime amplifier output place, arrives one of them analog to digital converter with amplitude range and this signal of control guiding of determining them, and described analog to digital converter can not overflow in response to this signal amplitude.

And, when three passages have been utilized, for the purpose of the whole dynamic range that increases detection system and/or for given analog to digital converter with opposing any one because the saturated and interim purpose that the substitutes analog to digital converter that overflows temporarily, utilize four or more hyperchannel also within notion of the present invention.

By about the detailed description to the aforementioned expansion of the present invention, a kind of embodiment can be a two-channel system form of utilizing a pair of 16 supper-fast analog to digital converters, the application enough of the present invention of its clock speed.Notice that further full dynamic range is not all always to be required, and may need to be less than full dynamic range such as the special user in every kind of application, therefore can utilize in a plurality of analog to digital converter passages only one of them.In the two-channel system that passage switches, might provide a part of advantage of the three-channel system that only utilizes two passages therein between low gain and high-gain.

Very near the problem of the defect echo of target object rear wall, the inventor recognizes with respect to above-mentioned, if two passages all are stored, and carry out passage change in aftertreatment, then can address this problem.This will be " following the tracks of the rear wall attenuator " solution.Can also use two or split screen display window, one is used for display defect and another demonstration rear wall.Will eliminate like this following the tracks of the needs of rear wall and adjustment display.A fraction of received signal will be shown twice--the once high-gain in defect part, the low gain in rear wall section again.If the position of door is calculated words in aftertreatment, then this method can only support to survey the defective warning door of the defective of very close rear wall.

So that the data stream of set fits within the notion that does not have step (steps) or transition (jumps) together, should be noted that can be by using factory to adjust or adjusting working time and realize this with respect to aforementioned independent adjustment channel frequence response.Notice that further in three-channel system, it is enough only providing the frequency response fine setting to two passages wherein.

The present invention can also be selected to realize in its signalling channel before the saturated conditions full recovery with the output data that prevents analog to digital converter by the duration that prolongs super scope (over range) indicator signal.This can take one or more following kind forms.

1. in current embodiment, the time is added to the end of super range indicator position from analog to digital converter.This feature is realized in channel selecting logical one 37, shown in Fig. 8 b.It can comprise receive spill over as an input and displacement form thereof as another input with door.

2. digital comparator is used to have next passage than low gain, with survey analog to digital converter when walk out seriously saturated, even analog to digital converter is still indicated super scope.Adding delay to this " seriously saturated " detector can compare with delay is provided on super range indicator.

3. the data from analog to digital converter output are compared with next value than the low-gain channel, to verify this data.This value must be within the specialized range from the value of next passage.

4. analog to digital converter is used, and it slowly indicates it to walk the excess of export scope.

Should further notice, analog to digital converter may be higher than on the input voltage of super range of voltages saturated.Why Here it is provides that to walk out saturated delay be useful, and the delay of walking the excess of export scope is unwanted.Super scope and saturated between voltage range in, analog to digital converter can operate as normal and is not needed release time.In the embodiment that is realized by reduction, the super range indicator of analog to digital converter has been used as saturated indicator, and will introduce unwanted delay sometimes.This undesired delay seldom, without any technical meaning.

The inventor also attempts to use analog to digital converter to finely tune the analog to digital converter reference voltage, is used to finely tune the effect of gain.This method is used to the scope of extending user gain control, and these are different with the passage coupling.

The inventor also attempts for not making the medium of source signal distortion and high-gain passage use prime amplifier.The amplifier of at least 20 volts peak output areas with utmost point low-noise performance is preferably set up or utilized to this method.Described method also is preferably used for Mixed Design, and wherein the attenuator step is used in input, but this method does not have very big dynamic range.In any case concerning the market segmentation cheaply, Mixed Design will be preferred.

In the description in front, reference is made in the various technology considerations about the analog to digital converter that becomes saturated circuit arrangement or the super scope of indication.After initial discussion, provide several optional solution of representing the further embodiment of the present invention to following problem.

Under common operational circumstances, the channel gain that is used for the circuit represented at following bracket is suitable for.

Passage A gain * 32 ≈ channel B gains [Fig. 7]

Channel B gain * 32 ≈ channel C gains [Fig. 7]

When passage is driven to when saturated, it will be indicated by the output signal of overflowing of the analog to digital converter of passage, makes channel selecting logical one 37 can select optimal channel to come received signal thus.As previously described, optimal channel is to have highest-gain and the passage under overflow status not.Be respectively passage A, channel B and channel C from minimum to the highest gain.Referring to Fig. 8 b, 8c, 8d and 8e.

Any or all above-mentioned situations are not genuine for the signal of very quick switching rate (slew rate), rising edge (leading edge) such as the pulse producer pulse, because this edge is very fast, so that the amplifier of all three passages almost is driven to simultaneously is saturated.

Because the slew rate limit of amplifier and wave filter, analog to digital converter is unsaturated at once, and all three passages move to saturated with same speed substantially.If from the A/D sampling, and their output is being transformed into their end value, then Cuo Wu reading will be noted.For example, when all three passages when being about 1/2 full scales (corresponding to A/D output valve (with sexadecimal) 2FFFC), they will not correspond to correct input range.Wherein the passage reading that overflows of neither one indication will be as follows:

Passage A=2FFF is at input indication-5V

Channel B=2FFF is at input indication-0.15V

Channel C=2FFF is at input indication-0.005V

Therefore, the embodiment of Fig. 8 b and 8c is with selector channel C, because it is the passage that has highest-gain and be not in overflow status as yet.Top passage reading indication passage A is-5V or lower; Therefore, the signal of-0.005V (supposing the input in channel C) will be displayed on the display, and this will be incorrect.

Shown in Fig. 8 d and 8e, optional embodiment does not need to use the output signal of overflowing from any analog to digital converter 132,134 and 136.But amplitude comparator 801,802 and 803 is used to indicate the digital output data of each analog to digital converter when to be complementary with predetermined number respectively.When the digital output data of predetermined number and each analog to digital converter mated, amplitude comparator 801,802 and 803 was provided to the output signal of channel selecting logical one 37.Amplitude comparator 801 also its output signal offers index maker 139.The performance that should be noted that present embodiment can also be by only using amplitude comparator 801 and 802 to realize respectively for passage A and B.

Because the fact that the digital output signal of channel modulus converter can be associated with the signal level along arbitrfary point on the input signal path, the major advantage of " amplitude comparator " method is that it can be used to survey and falls into any interested signal level within the analog to digital converter full scale and be within its Measurement Resolution ability.The saturated conditions of amplifier is an example of interested signal level in the input signal path.

With reference to Figure 10, when handling very fast signal along (being fast switching rate), following logic is true.Be to be understood that, below shown in value be 14 integers that symbol is arranged.

A) [if passage A＞=100] or [passage A＜=3EFF], then channel B and channel C amplifier may be to be driven excessively (over driven).

B) if [channel B＞=100] or [channel B＜=3EFF], then the channel C amplifier may be to be driven excessively.

Logic above utilizing a) and b), the channel selecting problem of mistake can prevent by following rule is attached in the channel selecting logical one 37 according to the priority shown in following:

If a) [passage A＞=100] or [passage A＜=3EFF] then use the data from passage A, promptly passage A has the right of priority that is higher than channel B

B) if [channel B＞=100] or [channel B＜=3EFF] then use the data from channel B, promptly channel B has the right of priority that is higher than passage A

C) if [passage A＜100 and＞3EFF] and [channel B＜100 and＞3EFF] then use the data from channel C, promptly channel C has the right of priority that is higher than passage A and B

Should be noted that the hexadecimal value that uses among top and Figure 10 is selected as example, and not necessarily leave no choice but use this value in the practical embodiments.

Fig. 8 d further has been shown in broken lines the channel mixer 135 ' that is used as MUX 135 replaceable modes.In order to minimize the influence of mismatch signal between the passage, channel mixer 135 ' is used for mixing three A/D converters and has highest-gain but the output of undersaturated two A/D converters.

Approximate circuit and the signal that is included in the channel mixer 135 ' that be equal to of Figure 11; Yet it shows the part of passage A and B, and more will to need to be added to meet be the needed input of RAM141 to multiple output circuit.

Just as used herein, " mixing " is meant merging or is associated, make that the composition or the separatrix of separating are not easily distinguished.Like this, channel mixer 135 ' is to obtain output valve and calculate the device of Compromise Values as its output from two adjacent A/D converter passages.Need ratio to control the ratio of two used inputs.

Figure 11 shows the details than rate control circuit.

In this example, the ratio controlling value is limited in 0 to 1 scope.

(input A) * ratio+(input B) * (1-ratio)=output

For the purpose of circuit reduction, ratio control can further be limited to can not comprise 0 and/or 1 little discrete value set.Numeral 0 and 1 produces and one or the identical output of other input; Some other circuit can be handled this situation.

Can support following rate value by the very simple mixer that two totalizers and three multiplexers combine: 0,0.25,0.5,0.75 and 1.This is divided into the unusual of four kinds of separation brokenly with channel selecting; Each is 1/4th of an amplitude.

Like this, according to the amplitude of Fig. 7 input signal 19a, the channel selecting logical one 37 of Fig. 8 d is selected the passage of activation.When this system is used to produce very when making the application of input signal amplitude of threshold value of system's switching channel, can observe, when system changes passage, little jumps over or malfunctioning may appearing in the output, because the gain of two passages, frequency response and/or phase place out of true coupling.This may show it itself is rising or the decline of not expecting in the amplitude output signal.

With reference to Fig. 8 d, the low-gain channel is passage A, and the high-gain passage is a channel B.Depend on the output that is comprised in amplitude comparator 1102 and 1108 (Figure 11) in the channel mixer 135 ' (Fig. 8 d), how mixer 1111 (Figure 11) measurement is near saturated channel B.When input signal 19a (Fig. 7) increased, channel B was near the preset value of saturated and amplitude comparator 1108.When reaching the latter, mixed function is by being called in channel mixer 135 ', and described channel mixer 135 ' will be from the data of A/D converter 134 and data mixing from A/D converter 132.Mixed function is variable, perhaps has from two steps that data source is weighted of A/D converter separately.When channel B arrives when saturated, the mixed weighting ratio is changed, thereby uses bigger weight and use less weight to channel B to passage A.As an example: from low input-signal 19a (Fig. 7) amplitude, mixture ratio will be channel B 100% and passage A 0%; When channel B moves closer to when saturated, mixing will change into channel B 50% and passage A 50%; When channel B is saturated, mixing be passage A 100% and channel B 0%.Mixing ratio can be by passage A or B or their combination extraction.Mixing ratio can change in several steps, perhaps smoothly adjusts pro rata with the channel signal amplitude.

The use of channel mixer 135 ' makes passage A operation more unlikely is not operated the person and observes with input signal 19a (Fig. 7) voltage threshold that the channel B operation separates.This mixed function can be used to all passage tr pts.This method can be used in combination with any other method that control channel is selected.

Fig. 8 h provides another kind of solution, provided the additional clock period to respond to spill over before being provided for MUX 135 in the output sampled data, it is to the output sampled data of analog to digital converter 132,134 and 136 and overflow (OF) signal and added delay element.Although not shown, can use the additional clock period more than one.Postpone to prevent that channel selecting logical one 37 selector channel have had enough time responses up to spill over, prevent the previously described problem that causes by quick switching rate input signal thus.

In each passage, carry out following operation in order to make spill over, overflow and the spill over that postpones is provided for and door:

A) under the situation that does not have to postpone, open, make it be provided for the time that MUX 135 is when analog to digital converter output sampled data before, take place and

B) for return the delay sampling data that just are provided for MUX 135 input from overflow status and carry out synchronously, close having under the situation of delay.

Should be noted that the delay except that a clock period also can be used to this optional embodiment.

This method is to realize by insert the data delay in a sampling clock cycle between the input of each digital signal output of analog to digital converter 132,134 and 136 and MUX 135.The data delay of 1 sampling clock also be inserted into each analog to digital converter spill over and and the input of door between.The output with door 809 of passage A is provided for the input of index maker 139.Channel B and C be provided for channel selecting logical one 37 respectively with outputs door 812 and 815.

The performance that should be noted that this optional embodiment also can realize by only utilizing the delay among channel B and the C.

The inventor also considers by only utilizing the variable gain mechanism in each channel analog signal path, such as variable gain amplifier, makes the gain of each passage satisfy the method for predetermined level basically.Gain level can be set to predetermined level by calibration process.The predetermined level of considering for present embodiment is that those guarantee the accurate as far as possible level of gain scale between passage A, B and the C.The accompanying drawing that is not associated with this optional embodiment.

In the description in front, with reference to the baseline corrector 148 shown in Fig. 8 c.As described below, digital DC skew is adjusted and can be carried out in the output of any one analog to digital converter, rather than only carries out in mixing output, shown in Fig. 8 c.Therefore, referring now to Fig. 8 e, 8f and 8g, note following item:

A) the baseline correction system (BLCS) 804 shown in Fig. 8 f is identical to 150 with the project 146 shown in Fig. 8 e.

B) the baseline correction system (BLCS) 805,806 and 807 that is used for passage A, B and C has the content identical with BLCS 804 respectively.BLCS 805,806 and 807 is the forms that repaint of BLCS 804, and is intended to improve the outward appearance of Fig. 8 g.

C) shown in Fig. 8 g, BLCS 805,806 and 807 is inserted between the input of the digital signal output of analog to digital converter 132,134 and 136 and MUX 135.

With further reference to Fig. 8 g, during the interval 10c shown in Fig. 3, A/D converter 132,134 and 136 output are provided for BLCS 805,806 and 807.Sampled point from interval 10c is used to monitor baseline, because they are in the time zone of " peace and quiet " relatively--promptly occur in before the pulse producer igniting and zone afterwards will appear in the ultrasound wave response signal of essence amplitude.In the present embodiment, BLCS 805,806 and 807 each all utilize 256 sampled points and calculating mean value; Yet, can use the sampled point of different numbers.Multiplexer in the BLCS 805,806 or 807 can be enabled by they control signals (ME) separately and offer baseline corrector module input B with the output that allows each BLCS, shown in Fig. 8 f.Input B is deducted from the output of A/D converter 132,134 and 136 then, to eliminate lubber line error.The register that is included in BLCS 805,806 and 807 plans to allow optional bias control value to be used, and described bias control value is produced by software algorithm or unshowned hardware unit.

The inventor has also considered shown in Fig. 9 and optional embodiment that be described below, it will be determined and the control system gain by utilizing with one or more gain reading A/D converters and the corresponding to signal path A/D converter of automatic gain control (AGC) circuit, realize advantage of the present invention, particularly high dynamic range.Although do not have shown in Figure 9ly, the input signal 10b of Fig. 1 is connected to the input 200 of Fig. 9.

According to the aspect of optional embodiment, the data reconstruction device of catching in the logic module 210 is used for the computing system gain and presents the appropriate signals amplitude on display, perhaps it is provided as the input to other device.Catch in the FPGA 140 that logic module 210 will be positioned in Fig. 7, and the circuit in its left side will be basically with whole replacements of Fig. 9.Some circuit among the FPGA 140 will be to be modified or to remove the appropriate mode of each optional embodiment.

According to optional embodiment on the other hand, combine with the output valve of gain reading A/ D converter 225 and 226, be each sampled point computing system gain by the output valve of utilizing signal A/D converter 209.Sampling rate is substantially the same, and synchronous to A/D converter 209,225 and 226.The degree of accuracy that system-gain calculates is basically by the degree of accuracy of gain calibration system, the transfer characteristic of multiplexer and the degree of accuracy decision of aforementioned three A/D converters.The inventor considers, being offset the calibration of making zero for zero multiplication (explained later) and DC can be by each passage needs.

As can from Fig. 9, further finding out, the circuit of optional embodiment comprises four parallel input gain passages 201,205,207 and 211, its each output is provided for one of four gain control multipliers 202,206,208 and 212 respectively, its output is provided for totalizer 203, and amplifier 204, A/D converter 209 and the last logic 210 of catching are followed in totalizer 203 back.Agc circuit 227 receives input from monitor signal 213,214,215 and 216, and provides outputing gain control signal 217,218,219 and 220 to multiplexer 202,206,208 and 212 respectively.The inventor recognizes that number of active lanes can be greater or less than four, and this depends on the required dynamic range of application that this optional embodiment is applied to.

Prevent the saturated influence of not expecting of signal that may on the signal path diverse location, take place be this optional embodiment crucial aspect.Signal path is from importing 200, to the end of input of A/D converter 209.Saturation signal in the present embodiment is considered to from the signal path that the output of prime amplifier 201,205,207 and 211 begins its absolute value of amplitude greater than 1 volt arbitrary signal.Three kinds of following situations can cause saturation signal to appear in the signal path.

1. the amplitude absolute value of input signal 200 is greater than the 10V peak value.

2. the amplitude absolute value of input signal 200 is less than or equal to 10 volts peak, and has enough peak values and make the output of prime amplifier 205,207 or 211 greater than 1 volt.

3. the amplitude absolute value of input signal 200 is less than or equal to the 10V peak value, and the enough Gao Deke of output summation of the multiplier 202,206,208 of totalizer 203 outputs place and 212 cause at the signal of A/D converter 209 inputs saturated.

For situation 1, the target of this optional embodiment is not to prevent that the signal on the signal path is saturated, because a lot of defectoscope checking process needs its peak amplitude absolute value always to appear on the display much larger than the pulse producer signal of 10V; Therefore, the pulse producer signal must be allowed on signal path saturated.

For situation 2, provide among this optional embodiment by using agc circuit 227, by gain control signal 218,219 and 220 being set to basically zero, prevent the device of the saturation output signal of prime amplifier 205,207 and 211 basically by gain multiplier 206,208 and 212.The inventor recognizes that commercial available multiplier assembly does not have the perfect performance feature.Therefore, multiplier 206,208 and 212 is not needed to provide the infinite attenuation that is associated with theoretic zero multiplication.206,208 and 212 needs of multiplier provide enough decay that the maximum peak amplitude of saturation signal is remained on and will cause under the level of the influence of not expecting the input signal of A/D converter 209.The maximum saturation signal level that allows can be set up such as EN12668-1:2000 according to the recognized industry standard that for example is used for detector device.It should be noted that output summation to multiplier 206,208 and 212; Therefore must consider maximum is allowed the calculating of saturation signal level.

For situation 3, originally provide among optional embodiment by using agc circuit 227 to guarantee that the output of multiplier 202,206,208 and 212 has enough low amplitude, so that prevent from after output is by totalizer 203 summations and 204 amplifications of quilt+15dB amplifier, to appear at the device of the input of A/D converter 209 greater than the signal of 1V.

According to optional embodiment on the other hand, passage A, B, C and D must have the propagation delay that equates basically and equal and comprise the frequency response of totalizer 203 inputs, so that prevent the distortion in summation output place.

According to optional embodiment on the other hand, all by multiplier multiplicand signal gain A, gain B, gain C and gain D control, they are represented with project 217,218,219 and 220 respectively in Fig. 9 in the gain of each passage.Automatic gain control circuit 227 utilizes monitor signal 216,215,214 and 213 to monitor the output of each gain amplifier, and adjusts gain thus.Multiplier 202,206,208 and 212 gain are controlled as follows, promptly provide from the level and smooth conversion of a multiplier to another multiplier, prevent to cause the unexpected change in gain of distorted signals or malfunctioning (glitche) thus.

According to optional embodiment on the other hand, if prime amplifier 205,207 or 211 is saturated, be prevented from making input signal 200 distortions by the clamp circuit that uses the front to describe at the invention of Fig. 7.Each clamp circuit is by preventing input signal 200 distortions for prime amplifier 205,207 and 211 keeps constant input impedance.

According to optional embodiment on the other hand, A/ D converter 225 and 226 pairs are sampled by the summation gain signal that totalizer 223 and 224 offers it respectively.For convergent-divergent they so that be complementary with the sensitivity of gain signal 218 and 220, gain signal 217 and 219 each all be divided into 10 parts.

According to optional embodiment on the other hand, when the signal amplitude of input 200 approaches zero, gain monitor signal 213,214,215 and 216 amplitude also will approach zero, cause automatic gain control circuit 227 gain signal 217,218,219 and 220 to be increased to their 1 volt of maxgain value thus.When the signal amplitude of input 200 increases, for being provided before arriving saturated conditions, the level and smooth gain of interchannel shifts, and the multiplier with non-zero gain multiplicand gradually changes.When input 200 amplitude makes that D_Monitor signal 213 reaches the predetermined just amplitude under saturated, automatic gain control circuit 227 D220 that will gain is reduced to zero, when it takes place with box lunch, prevent that saturation signal is by passage D multiplier 212 and cause saturated substantially signal.When gain D was set to zero, input 200 will be passed through passage A, B and C, reached the predetermined just amplitude below saturated up to C_Monitor signal 213, made the above-mentioned automatic gain control and treatment that is used for passage D begin to be used for channel C thus.Along with the signal amplitude continuation increase of input 200, this process is carried out channel B, is passage A then, prevents that finally saturated substantially signal is by channel B, C and D.

The response time of agc circuit 227 has set up the maximum of input signal 200 and can accept time rate of change, because gain is adjusted and must be occurred in input signal 200 and reached before the moment that will cause the amplitude that unallowed signal takes place.If optional embodiment must be with the signal work of its time rate of change faster than 227 response times of agc circuit, then between the input of the output of prime amplifier 201,205,207 and 211 and multiplier 202,206,208 and 212, introduce delay circuit.Monitor signal 216,215,214 and 213 is connected respectively to the input of each delay circuit.Delay circuit provides greater than the agc circuit time delay of 227 response times.In order not cause the distorted signals of unacceptable degree, relative propagation delay between the delay circuit of each passage and frequency response error must be minimum.

The inventor recognizes that the purpose of optional embodiment can realize that described automatic gain control circuit 227 is realized to be different from the described alternate manner of the foregoing description by controlled variable and the sequence that is used for automatic gain control circuit 227.And the inventor recognizes that these other embodiment can finish the identical net result about gain control basically.

Run through whole instructions and claims, with reference to " echo " signal.Just as the skilled person will recognize, in specific environment or application, the transmitter and receiver assembly of transducer 12 is physically separated, and receiver is positioned in just on detected object opposite.Therefore, terminology used here " echo " also about and comprise that wherein so-called echoed signal is by just at the embodiment of detected object.

In the description in front, the present invention has carried out special description about embodiment, and wherein, flaw detection is to utilize to operate in specially under the echo principle and/or with reference to handling by the right single transducer element of hyperacoustic emittor/receiver of material to move.Yet, should be noted that the present invention is applicable to with being equal to utilize transducer element array, such as the detector device of ultrasonic phased array row probe.Under the situation of utilizing the discrete component ultrasonic transducer, all be provided for the input of receiver channel for the response signal of each element of transducer of the phased array ultrasonic probe that is used to receive, be used for regulating and ensuing digitizing by analog to digital converter.In other words, in the claim to the ultrasonic phased array row type that (singulative) is considered to also belong to probe of quoting of " transducer ".This transducer array is considered to identical, perhaps is equal to the discrete component transducer at least.The structure of this ultrasonic phased array array apparatus is described or quotes in U.S. Patent No. 4,497, and in 210 and 6,789,427, the content of these patents is incorporated herein by reference.

Although the present invention is described about its specific embodiment, yet much other distortion and modification and other use will be tangible for a person skilled in the art.Therefore, preferably, the present invention is not subjected to special disclosed restriction here, but is only limited by appended claim.

Claims (65)

1. object check system comprises:

Transmit and receive part, the echoed signal that is used to generate detection signal and receives response;

Transducer is used for detection signal is converted to ultrasonic signal, ultrasonic signal is applied to wants detected target object, receives the ultrasonic echo signal, and produces echoed signal for transmitting and receiving part;

With the signal processing circuit that transmits and receives the part coupling, be used for receiving and handling echoed signal, this signal processing circuit comprises at least three signal processing channels, and each passage zooms to echoed signal in various degree, and each passage has analog to digital converter separately; With

Select the selection circuit of the output of described analog to digital converter, described analog to digital converter provides the maximum amplification of the echoed signal of not overflowing.

2. system according to claim 1 comprises being used to show the display that is produced and represented the sweep signal of echoed signal by signal processing circuit.

3. system according to claim 1 further is included in the frequency filter separately in one of them signalling channel.

4. system according to claim 1 further comprises the frequency tuning circuit separately that is used for one of them described signal processing channel, and this frequency tuning circuit separately mates the frequency response of wave filter mutually.

5. system according to claim 1, comprise first, second and the 3rd signalling channel at least, described passage comprises first, second and the 3rd prime amplifier respectively, and described prime amplifier provides first, second and the output of the 3rd convergent-divergent of echoed signal respectively.

6, system according to claim 5, wherein the output of second prime amplifier is provided as the input of the 3rd prime amplifier.

7. system according to claim 5, wherein DC offset adjusting circuit separately is in one of them signal processing channel.

8. system according to claim 5, wherein each passage all comprises differential amplifier driver separately.

9. system according to claim 8, wherein one of them amplifier-driver is provided with the DC offset adjusting circuit.

10. system according to claim 5, wherein the output of first, second and the 3rd prime amplifier be such so that second output greater than first output, and the 3rd output is greater than second output.

11, system according to claim 5, comprise first, second and the 3rd analog to digital converter, each analog to digital converter has clock input separately, this clock input utilize activate its clock along between the phase place adjustment and the phase mutually synchronization, to compensate the signal path delay in each passage.

12. system according to claim 5 comprises the clamp circuit that is used for prime amplifier.

13, system according to claim 5, wherein each analog to digital converter has the output of overflowing separately, and described selection circuit comprises the channel selecting logical circuit, and described channel selecting logical circuit receives the output of exporting and selecting to provide the described analog to digital converter of the maximum amplification of not overflowing of overflowing separately.

14. system according to claim 13 further comprises the index maker, is used for the output of the selected analog to digital converter output of convergent-divergent, and same output is stored in the random access memory.

15. system according to claim 5 comprises display.

16. system according to claim 3, its median filter is an antialiasing filter.

17. system according to claim 5 comprises the DC off-centre circuit, described circuit is applied to digital DC offset correction and is positioned at described selection circuit signal location place afterwards.

18. system according to claim 17, wherein the DC off-centre circuit comprises and is coupled in first, second and the 3rd analog to digital converter at least one of them producing the baseline capture circuit of correction signal, and described baseline capture circuit comprises the baseline corrector that can deduct correction signal from the output signal by one of them derivation of first, second and the 3rd analog to digital converter.

19. system according to claim 11 comprises fifo circuit, described fifo circuit makes it possible to the clock period by selectable integer number, with respect to clock input of other clock input delay.

20. system according to claim 5, comprise the delayed analog signal module, described delayed analog signal module is so that can be by synchronous mode from the output of first, second and the 3rd prime amplifier, postpones effectively from first, second and one of them of the 3rd prime amplifier or the output of more derivation.

21. system according to claim 20, wherein the delayed analog signal module comprises the lag line with tap, and wherein Qi Wang tap is selected to obtain the delay of expectation by switch.

22. system according to claim 20, wherein the delayed analog signal module comprises the delay filter element, its can switch as required into or switch and signal path.

23. system according to claim 20, wherein the delayed analog signal module comprises adjustable variable element, its by voltage-controlled component responds in the digital to analog converter Be Controlled.

24. the spill over separately that circuit is coupled to be provided by a plurality of described analog to digital converters is separately wherein selected by system according to claim 1.

25. system according to claim 1, wherein select circuit to be coupled to a plurality of amplitude comparators, described a plurality of amplitude comparator is coupled to a plurality of described analog to digital converters separately separately, wherein each described amplitude comparator is constructed to, with its separately the output of analog to digital converter compare with predetermined reference separately, described selection circuit determines in advance whether one or more described analog to digital converter is just trending towards false readings in response to described amplitude comparator.

26. system according to claim 1, comprise the baseline correction system separately that is associated with separately one or more described analog to digital converter, described baseline correction system is coupled to multiplexer respectively, described multiplexer with selected one of them channeling conduct so that handle.

27. a method that is used for the ultrasound wave object detection comprises the steps:

Provide detection signal to generate ultrasonic signal to transducer, described ultrasonic signal can be propagated in target object that will be detected and be reflected;

Receive the ultrasonic echo signal, and processed echoed signal is wanted in generation;

Handle echoed signal at least three signal processing channels, described echoed signal is scaled in various degree in each treatment channel, and utilizes the analog to digital converter separately in each treatment channel subsequently and be converted into numeral output; With

Selection is from the output of described analog to digital converter, and it provides the maximum amplification of the echoed signal of not overflowing.

28. method according to claim 27 comprises the sampling number separately of adjusting each analog to digital converter, with compensation time lag source, described time lag source comprises the signal propagation delays in each signalling channel.

29. method according to claim 27 comprises preventing the saturated of the prime amplifier input phase that is associated with passage, in case the stop signal distortion effect is to the input of other passage.

30. method according to claim 27 is included in and finely tunes frequency response separately in one of them passage, so that three passages have the frequency response of coupling basically.

31. method according to claim 27 comprises that the passage of surveying in the one or more passages with higher gain overflows situation.

32. method according to claim 27 comprises that the output with analog to digital converter merges in the continuous output stream.

33. method according to claim 27 comprises by each point at analog signal path and injects DC signal from digital to analog converter, eliminates the signal bias error in each signalling channel.

34. method according to claim 27 further comprises by using digital to analog converter, changes the reference voltage that is applicable to analog to digital converter in each signalling channel, to adjust its full scale range.

35. method according to claim 27 comprises the activation marginal position of adjustment to the clock input of analog to digital converter, to guarantee that each analog to digital converter is in same point up-sampling echoed signal.

36. method according to claim 27 comprises that the digital output data amplitude that the analog to digital converter by the different passages that match with the gain level separately of analog to digital converter is obtained carries out convergent-divergent.

37. an object check system comprises:

Transmit and receive part, the echoed signal that is used to generate detection signal and receives response;

Transducer is used for detection signal is converted to ultrasonic signal, ultrasonic signal is applied to wants detected target object, receives the ultrasonic echo signal, and produces echoed signal for transmitting and receiving part;

With the signal processing circuit that transmits and receives the part coupling, be used for receiving and handling echoed signal, this signal processing circuit comprises at least one signal processing channel, and each passage all comprises prime amplifier separately, and described prime amplifier zooms to different degree with echoed signal;

Be coupled to the analog to digital converter of prime amplifier by amplifying circuit, its mode for only at least the unsaturation of one of them prime amplifier output pass to analog to digital converter; With

Automatic gain control circuit, it is coupled to the output of prime amplifier, and can survey the output amplitude of prime amplifier, so that the gain setting to multiplier circuit to be provided, described multiplier circuit is selected to guarantee that unsaturation output is provided for analog to digital converter.

38. according to the described system of claim 37, comprise and catch logical circuit that it is coupled to and receives from the output of analog to digital converter and additional output, described additional output is derived by automatic gain control circuit.

39. according to the described system of claim 38, wherein additional output is produced by at least one analog to digital converter, described analog to digital converter is provided at catches between logical circuit and the automatic gain control circuit.

40. an object check system comprises:

Transmit and receive part, the echoed signal that is used to generate detection signal and receives response;

Transducer is used for detection signal is converted to ultrasonic signal, ultrasonic signal is applied to wants detected target object, receives the ultrasonic echo signal, and produces echoed signal for transmitting and receiving part;

With the signal processing circuit that transmits and receives the part coupling, be used for receiving and handling echoed signal, this signal processing circuit comprises at least two signal processing channels, and each passage zooms to echoed signal in various degree, and each passage has analog to digital converter separately;

Select the selection circuit of described analog to digital converter output, described analog to digital converter provides the maximum amplification of the echoed signal of not overflowing; With

Channel mixer, it is in response to selecting circuit, and operationally mixes the output of described analog to digital converter, to produce the modulus output that mixes.

41. according to the described system of claim 40, wherein select circuit to be coupled to a plurality of amplitude comparators, described a plurality of amplitude comparator is coupled to a plurality of described analog to digital converters separately separately, wherein each described amplitude comparator is constructed to, with its separately the output of analog to digital converter compare with predetermined reference separately, described selection circuit determines in advance whether one or more described analog to digital converter is just trending towards false readings in response to described amplitude comparator.

42. according to the described system of claim 40, wherein each analog to digital converter all has the output of overflowing separately, and described selection circuit comprises the channel selecting logical circuit, and described channel selecting logical circuit receives the output of exporting and selecting to provide the analog to digital converter of the maximum amplification of not overflowing of overflowing separately.

43. according to the described system of claim 40, further comprise the frequency tuning circuit separately that is used for one of them described signal processing channel, this frequency tuning circuit separately mates the frequency response of wave filter mutually.

44. according to the described system of claim 40, comprise first and second analog to digital converters, each all has clock input separately, this clock input utilize activate its clock along between the phase place adjustment and the phase mutually synchronization, to compensate the signal path delay in each passage.

45., further comprise the index maker, be used for the output of the selected analog to digital converter output of convergent-divergent, and same output is stored in the random access memory according to the described system of claim 40.

46. according to the described system of claim 40, comprise the DC off-centre circuit, described DC off-centre circuit is applied to digital DC offset correction and is positioned at described selection circuit signal location afterwards, wherein this DC off-centre circuit comprises the baseline capture circuit, described baseline capture circuit is coupled to first or second analog to digital converter, and one of them is individual with the generation correction signal, and comprises the baseline corrector that can deduct correction signal from the output signal by first or second one of them derivation of analog to digital converter.

47. according to the described system of claim 40, comprise at least the first and second signalling channels, it comprises first and second prime amplifiers respectively, described prime amplifier provides first and second convergent-divergents output of echoed signal respectively, wherein the delayed analog signal module comprises the lag line with tap, and wherein Qi Wang tap is to be selected to obtain the delay of expectation by switch.

48. a method that is used for the ultrasound wave object detection comprises the steps:

Provide detection signal to generate ultrasonic signal to transducer, described ultrasonic signal can be propagated in target object that will be detected and be reflected;

Receive the ultrasonic echo signal, and processed echoed signal is wanted in generation;

Handle echoed signal at least two signal processing channels, described echoed signal is scaled in various degree in each treatment channel, and utilizes the analog to digital converter separately in each treatment channel subsequently and be converted into numeral output; With

Selection is from the output of described analog to digital converter, and it provides the maximum amplification of the echoed signal of not overflowing; With

In response to described selection step, mix the output of described analog to digital converter, to produce the modulus output that mixes.

49, according to the described system of claim 48, comprise the sampling number separately of adjusting each analog to digital converter, with compensation time lag source, described time lag source comprises the signal propagation delays in each signalling channel.

50., comprise preventing the saturated of the prime amplifier input phase that is associated with passage, in case the stop signal distortion effect is to the input of other passage according to the described system of claim 48.

51. according to the described system of claim 48, be included in and finely tune frequency response separately in one of them passage, so that passage has the frequency response of coupling basically.

52., comprise that the passage of surveying in the one or more passages with higher gain overflows situation according to the described system of claim 48.

53. according to the described system of claim 48, comprise, eliminate the signal bias error in each signalling channel by inject DC signal at each some place of analog signal path from digital to analog converter.

54. according to the described system of claim 48, further comprise, change the reference voltage that is applicable to analog to digital converter in each signalling channel, to adjust its full scale range by using digital to analog converter.

55., comprise the activation marginal position of adjustment, to guarantee that each analog to digital converter is in same point up-sampling echoed signal to the clock input of analog to digital converter according to the described system of claim 48.

56., comprise that the digital output data amplitude that the analog to digital converter by the different passages that match with the gain level separately of analog to digital converter is obtained carries out convergent-divergent according to the described system of claim 48.

57. an object check system comprises:

Transmit and receive part, the echoed signal that is used to generate detection signal and receives response;

Transducer is used for detection signal is converted to ultrasonic signal, ultrasonic signal is applied to wants detected target object, receives the ultrasonic echo signal, and produces echoed signal for transmitting and receiving part;

With the signal processing circuit that transmits and receives the part coupling, be used for receiving and handling echoed signal, this signal processing circuit comprises at least two signal processing channels, and each passage zooms to echoed signal in various degree, and each passage has analog to digital converter separately;

Select the selection circuit of described analog to digital converter output, described analog to digital converter provides the maximum amplification of the echoed signal of not overflowing; With

Delay circuit is used to postpone the output of one of them analog to digital converter at least, allowing analog to digital converter before the described output of described selection processing of circuit, the rising edge of quick converted input signal is responded.

58. according to the described system of claim 57, wherein delay circuit provides delay, described delay is the multiple of clock period of being associated with this system.

59. according to the described system of claim 58, wherein delay circuit further postpone effectively analog to digital converter separately overflow output.

60. an object check system comprises:

Transmit and receive part, the echoed signal that is used to generate detection signal and receives response;

Transducer is used for detection signal is converted to ultrasonic signal, ultrasonic signal is applied to wants detected target object, receives the ultrasonic echo signal, and produces echoed signal for transmitting and receiving part;

With the signal processing circuit that transmits and receives the part coupling, be used for receiving and handling echoed signal, this signal processing circuit comprises at least two signal processing channels, and each passage zooms to echoed signal in various degree, and each passage has analog to digital converter separately;

Select the selection circuit of described analog to digital converter output, described analog to digital converter provides the maximum amplification of the echoed signal of not overflowing; With

Delay circuit, it makes effectively selects circuit to prevent to select analog to digital converter output of having overflowed, up to the analog to digital converter that overflows after saturated conditions recovers.

61. an object check system comprises:

Transmit and receive part, the echoed signal that is used to generate detection signal and receives response;

Transducer is used for detection signal is converted to ultrasonic signal, ultrasonic signal is applied to wants detected target object, receives the ultrasonic echo signal, and produces echoed signal for transmitting and receiving part;

With the signal processing circuit that transmits and receives the part coupling, be used for receiving and handling echoed signal, this signal processing circuit comprises at least two signal processing channels, and each passage zooms to echoed signal in various degree, and each passage has analog to digital converter separately;

Select the selection circuit of described analog to digital converter output, described analog to digital converter provides the maximum amplification of the echoed signal of not overflowing; With

Frequency tuning circuit separately is used for one of them described signal processing channel, and frequency tuning circuit separately makes the frequency response of passage mate mutually.

62. an object check system comprises:

Transmit and receive part, the echoed signal that is used to generate detection signal and receives response;

Transducer is used for detection signal is converted to ultrasonic signal, ultrasonic signal is applied to wants detected target object, receives the ultrasonic echo signal, and produces echoed signal for transmitting and receiving part;

With the signal processing circuit that transmits and receives the part coupling, be used for receiving and handling echoed signal, this signal processing circuit comprises at least two signal processing channels, and each passage zooms to echoed signal in various degree, and each passage has analog to digital converter separately;

Select the selection circuit of described analog to digital converter output, described analog to digital converter provides the maximum amplification of the echoed signal of not overflowing;

The prime amplifier that is associated with each passage; With

What be associated with each prime amplifier prevents saturated circuit, and described circuit prevents the saturated of each each input phase of prime amplifier effectively, so that prevent the input of distorted signals influence to other passage.

63. an object check system comprises:

Transmit and receive part, the echoed signal that is used to generate detection signal and receives response;

Transducer is used for detection signal is converted to ultrasonic signal, ultrasonic signal is applied to wants detected target object, receives the ultrasonic echo signal, and produces echoed signal for transmitting and receiving part;

With the signal processing circuit that transmits and receives the part coupling, be used for receiving and handling echoed signal, this signal processing circuit comprises at least two signal processing channels, and each passage zooms to echoed signal in various degree, and each passage has analog to digital converter separately;

Select the selection circuit of described analog to digital converter output, described analog to digital converter provides the maximum amplification of the echoed signal of not overflowing; With

Reference voltage circuit is applicable to each the described analog to digital converter in each signalling channel respectively, to adjust its full scale range.

64. according to the described system of claim 63, wherein reference voltage circuit comprises the digital to analog converter separately that is associated with each analog to digital converter separately.

65. a method that is used for the ultrasound wave object detection comprises the steps:

Provide detection signal to generate ultrasonic signal to transducer, described ultrasonic signal can be propagated in target object that will be detected and be reflected;

Receive the ultrasonic echo signal, and processed echoed signal is wanted in generation;

Handle echoed signal at least two signal processing channels, described echoed signal is scaled in various degree in each treatment channel, and utilizes the analog to digital converter separately in each treatment channel subsequently and be converted into numeral output; With

Selection is from the output of described analog to digital converter, and it provides the maximum amplification of the echoed signal of not overflowing; With

The sampled data of the echoed signal of full dynamic range can be handled in the cycle at each sampling clock, and this mode makes sampled data to be presented in linear scale with on logarithmically calibrated scale.

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