CN115776298A - Bidirectional multi-level conversion circuit - Google Patents
Bidirectional multi-level conversion circuit Download PDFInfo
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- CN115776298A CN115776298A CN202211623750.5A CN202211623750A CN115776298A CN 115776298 A CN115776298 A CN 115776298A CN 202211623750 A CN202211623750 A CN 202211623750A CN 115776298 A CN115776298 A CN 115776298A
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Abstract
The invention discloses a bidirectional multi-level conversion circuit, comprising: the first end of the first resistor is connected with a communication link signal, and the second end of the first resistor is connected with a power supply voltage; the first end of the second resistor is connected with a communication link signal and is connected with a power supply voltage through a second switching device; a first end of the fifth resistor is connected with the control end of the third switching device, and a second end of the fifth resistor is connected between the seventh resistor and the first switching device; a first end of the sixth resistor is connected with the control end of the third switching device, and a second end of the sixth resistor is connected with the power supply voltage; the seventh resistor is connected to the ground through the first switching device; the control end of the first switching element is connected with a communication link signal through a third resistor; the control end of the second switch device is connected with the power supply voltage through the third switch device, and the control end of the second switch device is connected with the first switch device through the seventh resistor. The invention has the advantages of better signal quality, no overhigh low level, no overhigh rising edge, higher communication speed and low cost, and solves the technical problems of a plurality of conversion chip circuits.
Description
Technical Field
The invention relates to the field of electronic circuits, in particular to a bidirectional multilevel conversion circuit for communication buses of I2C, SMI, PMbus and other open-drain structures.
Background
The rapid development and the rapid update of the electronic industry are also rapid, and many electronic products are developed in the direction of low power consumption, so that the lower the IO level of a part of chips is, the phenomenon that chips with different level voltages coexist is caused, and when different level voltages communicate with each other, a level conversion circuit is required.
When the buses such as I2C, SMI and PMbus perform bidirectional level conversion, a MOSFET-based conversion chip is a relatively common scheme, and is shown in fig. 1. When one side is in low level, the internal MOSFET is conducted, and the other side is pulled low; when both sides are high, the MOSFET is non-conductive and the level voltage is determined by its pull-up voltage. When the electronic system is complex, buses with multiple level voltages need to communicate in the system, or when the same voltage but a certain isolation is needed between different power rails, multiple conversion chips are needed for conversion, as shown in fig. 2.
When one of the conversion chips outputs low level, the corresponding MOSFET of each conversion chip is conducted, all the pull-up resistors are connected in parallel to pull up to a certain voltage, the sink current of IO outputting low level is increased, if the sink current is increased to the limit, the voltage of the low level is increased, and when the V of the circuit is increased to the limit, the MOSFET of each conversion chip is connected with the corresponding MOSFET of each conversion chip in parallel to output low level, so that the output voltage of each conversion chip is increased to the maximum OL Larger than VILmax of the terminal device, communication failure may result. At this time, the solution of the prior art is to increase the pull-up resistance, but the bus has a parasitic capacitance on the PCB, when the signal changes from low to high, the MOSFET becomes non-conductive, the charging of the capacitance can only be done by the pull-up voltage source, because the pull-up resistance changes greatly, the charging will become slow, and the waveform of the signal shown in fig. 3 will become as shown in fig. 4. Signals of such waveforms may not meet the requirements in terms of signal integrity, and if they do, they may only operate at low speeds, and if they do, they may not meet the requirements when the bus rate is higher, limiting the maximum communication rate of the bus
Disclosure of Invention
In this summary, a series of simplified form concepts are introduced that are simplifications of the prior art in this field, which will be described in further detail in the detailed description. This summary of the invention is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
The technical problem to be solved by the invention is to provide a communication bus for an open-drain structure of a plurality of conversion chips (I2C, SMI, PMbus and the like), which does not cause low level lifting or slow rising edge and can meet the requirement of high communication speed.
In order to solve the above technical problem, the present invention provides a bidirectional multilevel converter circuit, comprising:
a first resistor R1 having a first end connected to the communication link signal SCL and a second end connected to the supply voltage VCC;
a first end of the second resistor R2 is connected to the communication link signal SCL, and is connected to the supply voltage VCC through the second switching device T2;
a fifth resistor R5 having a first terminal connected to the control terminal of the third switching device T3 and a second terminal connected between the seventh resistor R7 and the first switching device T1;
a first end of the sixth resistor R6 is connected to the control end of the third switching device T3, and a second end thereof is connected to the supply voltage VCC;
a seventh resistor R7 connected to the ground GND via the first switching device T1;
a control end of the first switching device T1 is connected with the communication link signal SCL through a third resistor R3;
a control end of the second switching device T2 is connected to the supply voltage VCC through a third switching device T3, and a control end thereof is connected to the first switching device T1 through a seventh resistor R7;
the resistance of the fifth resistor R5 is greater than or equal to the resistance of the seventh resistor R7, whether the second switching device T2 is turned on determines whether the second resistor R2 works, and the second switching device T2 and the third switching device T3 are the same devices.
Optionally, the bidirectional multi-level conversion circuit is further improved, further comprising:
a fourth resistor R4 connected between the control terminal of the first switching device T1 and the ground GND;
alternatively, the bidirectional multi-level switching circuit is further modified, the second switching device T2 is turned on only when the first switching device T1 is turned on and the third switching device T3 is not turned on.
Optionally, the bidirectional multi-level conversion circuit is further improved, the first switching device T1 is an NPN transistor, and the second switching device T2 and the third switching device T3 are PNP transistors. .
Optionally, the bidirectional multi-level switching circuit is further improved, when the communication link signal SCL is at a low level, the base of the first switch device T1 is still low after voltage division is performed by the third resistor R3 and the fourth resistor R4, the first switch device T1 is not turned on, the base of the second switch device T2 is at a high level, the emitter and the base of the second switch device T2 cannot be forward biased, the second switch device T2 is not turned on, the second resistor R2 does not operate, and at this time, the pull-up resistor is the first resistor R1;
when the communication link signal SCL is a rising edge, when the voltage divided by the third resistor R3 and the fourth resistor R4 is greater than 0.5V-0.9V, preferably 0.7, the first switching device T1 is turned on, the base of the second switching device T2 is low, the second switching device T2 is turned on, the second resistor R2 operates, and at this time, the pull-up resistor is formed by connecting the first resistor R1 and the second resistor R2 in parallel;
when the communication link signal SCL is at a high level, the first switching device T1 is turned on, the third switching device T3 is turned on, the base voltage of the second switching device T2 becomes the supply voltage VCC, and the second switching device T2 is turned off.
Alternatively, the bidirectional multi-level conversion circuit is further modified, and during the rising edge, the on time of the second switching device T2 can be adjusted by changing the resistance values of the fifth resistor R5, the sixth resistor R6 and the seventh resistor R7.
Optionally, the bidirectional multi-level switching circuit is further improved, and a value range of the first resistor R1 is as follows: r1 is approximately equal to R PU n+1
R PU Assuming that the pull-up resistance of the bus when the chip does not need to be converted is determined by the requirements of the terminal equipment and the parasitic capacitance on the PCB;
the value range of the second resistor R2 is as follows: r1// R2 is approximately equal to R PU ；
The third resistor R3 and the fourth resistor R4 satisfy the following resistance value relation;
k is a specified coefficient.
Optionally, the bidirectional multi-level conversion circuit is further improved, and K ranges from 1/4 to 2/3.
The working principle of the invention is explained as follows:
referring to fig. 5, in each link, taking the end of the communication link signal SCL as an example for explanation, whether the second resistor R2 operates depends on whether the second switching device T2 (PNP transistor) is turned on, and whether the second switching device T2 is turned on depends on the conduction states of the first switching device T1 (NPN transistor) and the third switching device T3 (PNP transistor), and the second switching device T2 is turned on only when the first switching device T1 is turned on and the third switching device T3 is turned off. That is, when the communication link signal SCL is at the rising edge, the first switch device T1 will turn on first, and the collector voltage of the first switch device T1 approaches 0V.
Because R5 is more than or equal to R7 and the base of the third switching device T3 is provided with one more pull-up resistor R6, the base voltage of the third switching device T3 is a little higher than the base voltage of the second switching device T2 at the moment when the first switching device T1 is turned on, so the second switching device T2 is turned on before the third switching device T3. When the rising edge of the communication link signal continues to rise and the discharging of the parasitic capacitance of the third switching device T3 is completed, the third switching device T3 is turned on. After the third switching device T3 is turned on, the base voltage of the second switching device T2 becomes VCC, that is, the second switching device T2 becomes non-conductive. During the rising edge the second switching device T2 is only conducting for a short time, which can be adjusted by the resistance values of R5, R6 and R7.
The main design idea is that when the link is at a low level, if the pull-up resistor is too small, the driving capability of the IO outputting the low level may be insufficient, and at this time, the pull-up resistor should be large, so the second switch device T2 should not be turned on, the second resistor R2 does not function, only the first resistor R1 is a pull-up resistor, and the resistance value of the first resistor R1 is selected to be a little larger;
when the low level is to be changed into the high level, if the first resistor R1 has a too large resistance, the voltage on the link will rise too slowly, as shown in fig. 4, the signal integrity is not good, so that the pull-up resistor is small at this time, that is, the second resistor R2 operates by turning on the second switching device T2, and the pull-up resistor is actually a parallel connection of the first resistor R1 and the second resistor R2. When the link signal is stable at the high level, the second switching device T2 should not be turned on for the next low level to be pulled down. I.e. the second switching device T2 is conducting for a short time on the rising edge, so that the rising edge time decreases and the high level is reached more quickly.
The on-state control circuit of the second switching device T2 is composed of a third resistor R3, a fourth resistor R4, the first switching device T1, and the third switching device T3. When the SCL is at a low level, the base of the first switching device T1 is still low after voltage division is performed by the third resistor R3 and the fourth resistor R4, the first switching device T1 is not turned on, the base of the second switching device T2 is at a high level, the emitter and the base of the second switching device T2 cannot be forward biased, the second switching device T2 is not turned on, the second resistor R2 does not function, and at this time, the pull-up resistor is the first resistor R1. When the SCL is a rising edge, when the voltage divided by the third resistor R3 and the fourth resistor R4 is greater than 0.5V to 0.9V, the first switch device T1 is turned on, the base of the second switch device T2 is low, the second switch device T2 is turned on, the second resistor R2 functions, and at this time, the pull-up resistor is formed by connecting the first resistor R1 and the second resistor R2 in parallel. When SCL is high, the first switching device T1 is fully turned on, the third switching device T3 is also turned on, and the base voltage of the second switching device T2 becomes VCC, i.e., the second switching device T2 becomes non-conductive.
Setting the pull-up resistance of the bus to R when the conversion chip is not needed PU (RPU is determined by terminal equipment requirements and parasitic capacitance on PCB), R1 value of the invention is R1 ≈ R PU (n + 1). The value of R2 is that R1// R2 is approximately equal to R PU . The third resistor R3 and the fourth resistor R4 need to satisfy the two conditions
The value of K is primarily used to set the first switching device T1 threshold value V of conduction TH K is
The finger threshold is set at half VCC. K may be larger or smaller according to actual conditions, and if the number n of converters is larger, the value of the first resistor R1 is larger, and K may be smaller appropriately. The second switching device T2 and the third switching device T3 are required to be PNP triodes of the same type, so that it can be ensured that the third switching device T3 is turned on later than the second switching device T2.
The signal waveform provided by the invention is shown in fig. 7, compared with the waveforms shown in fig. 3 and 4, the signal quality is better, the low level is not too high, the rising edge is not too slow, the communication speed is higher, and the technical problems of a plurality of conversion chip circuits are solved at low cost.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention, are incorporated in and constitute a part of this specification. The drawings are not necessarily to scale, however, and may not be intended to accurately reflect the precise structural or performance characteristics of any given embodiment, and should not be construed as limiting or restricting the scope of values or properties encompassed by exemplary embodiments in accordance with the invention. The invention is described in further detail below with reference to the following figures and embodiments:
fig. 1 is a schematic diagram of a conventional MOSFET-based conversion chip.
Fig. 2 is a schematic diagram of another conventional MOSFET-based conversion chip structure.
Fig. 3 is a diagram illustrating a first waveform of the prior art.
Fig. 4 is a diagram illustrating waveforms of the prior art.
Fig. 5 is a schematic structural diagram of an embodiment of the present invention.
FIG. 6 is a schematic structural diagram of the second embodiment of the present invention.
Fig. 7 is a schematic diagram of waveforms according to the present invention.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and technical effects of the present invention will be fully apparent to those skilled in the art from the disclosure in the specification. The invention is capable of other embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the general concept of the invention. It should be noted that the features in the following embodiments and examples may be combined with each other without conflict. The following exemplary embodiments of the present invention may be embodied in many different forms and should not be construed as limited to the specific embodiments set forth herein. It is understood that these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of these exemplary embodiments to those skilled in the art.
The first embodiment;
referring to fig. 5, the present invention provides a bidirectional multi-level conversion circuit, including:
a first resistor R1 having a first end connected to the communication link signal SCL and a second end connected to the supply voltage VCC;
a first end of the second resistor R2 is connected to the communication link signal SCL, and is connected to the supply voltage VCC through the second switching device T2;
a fifth resistor R5 having a first terminal connected to the control terminal of the third switching device T3 and a second terminal connected between the seventh resistor R7 and the first switching device T1;
a first end of the sixth resistor R6 is connected to the control end of the third switching device T3, and a second end thereof is connected to the supply voltage VCC;
a seventh resistor R7 connected to the ground GND via the first switching device T1;
a control end of the first switching device T1 is connected with a communication link signal SCL through a third resistor R3;
a control end of the second switching device T2 is connected to the supply voltage VCC through a third switching device T3, and a control end thereof is connected to the first switching device T1 through a seventh resistor R7;
the resistance of the fifth resistor R5 is greater than or equal to the resistance of the seventh resistor R7, whether the second switching device T2 is turned on determines whether the second resistor R2 works, and the second switching device T2 and the third switching device T3 are the same devices.
The first embodiment;
referring to fig. 5, the present invention provides a bidirectional multi-level conversion circuit, including:
a first resistor R1 having a first end connected to the communication link signal SCL and a second end connected to the supply voltage VCC;
a first end of the second resistor R2 is connected to the communication link signal SCL, and is connected to the supply voltage VCC through the second switching device T2;
a fifth resistor R5 having a first terminal connected to the control terminal of the third switching device T3 and a second terminal connected between the seventh resistor R7 and the first switching device T1;
a first end of the sixth resistor R6 is connected to the control end of the third switching device T3, and a second end thereof is connected to the supply voltage VCC;
a seventh resistor R7 connected to the ground GND via the first switching device T1;
a control end of the first switching device T1 is connected with the communication link signal SCL through a third resistor R3;
a control end of the second switching device T2 is connected with a power supply voltage VCC through a third switching device T3, and a control end of the second switching device T2 is connected with the first switching device T1 through a seventh resistor R7;
the resistance of the fifth resistor R5 is greater than or equal to the resistance of the seventh resistor R7, whether the second switching device T2 is turned on determines whether the second resistor R2 works, and the second switching device T2 and the third switching device T3 are the same devices.
Example two;
referring to fig. 6, the present invention provides a bidirectional multi-level conversion circuit, including:
a first end of the first resistor R1 is connected with the communication link signal SCL, and a second end of the first resistor R1 is connected with a power supply voltage VCC;
a first end of the second resistor R2 is connected to the communication link signal SCL, and is connected to the supply voltage VCC through the second switching device T2;
a fourth resistor R4 connected between the control terminal of the first switching device T1 and the ground GND;
a fifth resistor R5 having a first terminal connected to the control terminal of the third switching device T3 and a second terminal connected between the seventh resistor R7 and the first switching device T1;
a first end of the sixth resistor R6 is connected to the control end of the third switching device T3, and a second end thereof is connected to the supply voltage VCC;
a seventh resistor R7 connected to the ground GND via the first switching device T1;
a control end of the first switching device T1 is connected with a communication link signal SCL through a third resistor R3;
a control end of the second switching device T2 is connected to the supply voltage VCC through a third switching device T3, and a control end thereof is connected to the first switching device T1 through a seventh resistor R7;
the resistance of the fifth resistor R5 is greater than or equal to the resistance of the seventh resistor R7, whether the second switching device T2 is turned on determines whether the second resistor R2 works, the second switching device T2 and the third switching device T3 are the same devices, the second switching device T2 is turned on only when the first switching device T1 is turned on and the third switching device T3 is not turned on, the first switching device T1 is an NPN triode, and the second switching device T2 and the third switching device T3 are PNP triodes.
When the communication link signal SCL is at a low level, the base of the first switching device T1 is still low after voltage division is performed by the third resistor R3 and the fourth resistor R4, the first switching device T1 is not turned on, the base of the second switching device T2 is at a high level, the emitter and the base of the second switching device T2 cannot be forward biased, the second switching device T2 is not turned on, the second resistor R2 does not work, and at this time, the pull-up resistor is the first resistor R1;
when the communication link signal SCL is a rising edge, when the voltage divided by the third resistor R3 and the fourth resistor R4 is greater than 0.5V-0.9V, the first switch device T1 is turned on, the base of the second switch device T2 is low, the second switch device T2 is turned on, the second resistor R2 operates, and at this time, the pull-up resistor is formed by connecting the first resistor R1 and the second resistor R2 in parallel;
when the communication link signal SCL is at a high level, the first switching device T1 is turned on, the third switching device T3 is turned on, the base voltage of the second switching device T2 becomes the supply voltage VCC, and the second switching device T2 is turned off.
During the rising edge, the on-time of the second switching device T2 can be adjusted by changing the resistance values of the fifth resistor R5, the sixth resistor R6, and the seventh resistor R7.
Optionally, the value range of the first resistor R1 is: r1 ≈ R PU n+1；
R PU The pull-up resistance of the bus when the conversion chip is not needed is assumed to be determined by the requirements of terminal equipment and parasitic capacitance on the PCB;
the value range of the second resistor R2 is as follows: r1// R2 ≈ R PU ；
The third resistor R3 and the fourth resistor R4 satisfy the following resistance value relation;
k is a prescribed coefficient, and the range of K is 1/4 to 2/3, preferably 1/2.
Unless otherwise defined, all terms including technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
The present invention has been described in detail with reference to the specific embodiments and examples, but these are not to be construed as limiting the invention. Many variations and modifications can be made by one skilled in the art without departing from the principles of the invention, which should also be considered as the scope of the invention.
Claims (8)
1. A bi-directional multi-level conversion circuit, comprising:
a first resistor (R1) having a first end connected to the communication link Signal (SCL) and a second end connected to a supply Voltage (VCC);
a second resistor (R2) having a first terminal connected to the communication link Signal (SCL) and being connected to the supply Voltage (VCC) via a second switching device (T2);
a fifth resistor (R5) having a first terminal connected to the control terminal of the third switching device (T3) and a second terminal connected between the seventh resistor (R7) and the first switching device (T1);
a sixth resistor (R6) having a first terminal connected to the control terminal of the third switching device (T3) and a second terminal connected to the supply Voltage (VCC);
a seventh resistor (R7) connected to Ground (GND) via the first switching device (T1);
a first switching device (T1) having a control terminal connected to the communication link Signal (SCL) via a third resistor (R3);
a second switching device (T2) having a control terminal connected to the supply Voltage (VCC) via a third switching device (T3) and a control terminal connected to the first switching device (T1) via a seventh resistor (R7);
the resistance value of the fifth resistor (R5) is larger than or equal to that of the seventh resistor (R7), whether the second switch device (T2) is conducted or not determines whether the second resistor (R2) works or not, and the second switch device (T2) and the third switch device (T3) are the same device.
2. The bi-directional multi-level conversion circuit of claim 1, further comprising:
and a fourth resistor (R4) connected between the control terminal of the first switching device (T1) and Ground (GND).
3. The bi-directional, multi-level conversion circuit of claim 1, wherein:
the second switching device (T2) is only conductive when the first switching device (T1) is conductive and the third switching device (T3) is non-conductive.
4. The bi-directional multi-level conversion circuit of claim 2, wherein: the first switching device (T1) is an NPN transistor, and the second switching device (T2) and the third switching device (T3) are PNP transistors.
5. The bi-directional multi-level conversion circuit of claim 4, wherein:
when a communication link Signal (SCL) is at a low level, the base electrode of a first switch device (T1) is still low after voltage division is carried out through a third resistor (R3) and a fourth resistor (R4), the first switch device (T1) is not conducted, the base electrode of a second switch device (T2) is at a high level, the emitter electrode and the base electrode of the second switch device (T2) cannot be positively biased, the second switch device (T2) is not conducted, the second resistor (R2) does not work, and at the moment, a pull-up resistor is the first resistor (R1);
when a communication link Signal (SCL) is at a rising edge, when the voltage divided by the third resistor (R3) and the fourth resistor (R4) is more than 0.5V-0.9V, the first switch device (T1) is conducted, the base electrode of the second switch device (T2) is low, the second switch device (T2) is conducted, the second resistor (R2) works, and at the moment, the pull-up resistor is formed by connecting the first resistor (R1) and the second resistor (R2) in parallel;
when the communication link Signal (SCL) is high, the first switching device (T1) is turned on, the third switching device (T3) is turned on, the base voltage of the second switching device (T2) becomes the supply Voltage (VCC), and the second switching device (T2) is turned off.
6. The bi-directional, multi-level conversion circuit of claim 1, wherein:
during the rising edge, the on-time of the second switching device (T2) can be adjusted by changing the resistance values of the fifth resistor (R5), the sixth resistor (R6) and the seventh resistor (R7).
7. The bi-directional multi-level conversion circuit of claim 2, wherein:
the value range of the first resistor (R1) is as follows: r1 ≈ R PU (n+1)
R PU Assuming pull-up resistance of the bus when no conversion chip is needed, as required by the terminal equipment and parasitic capacitance on the PCBDetermining;
the value range of the second resistor (R2) is as follows: r1// R2 ≈ R PU ；
The third resistor (R3) and the fourth resistor (R4) satisfy the following resistance value relation;
k is a specified coefficient.
8. The bi-directional, multi-level conversion circuit of claim 7, wherein: k is in the range of 1/4 to 2/3.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202211623750.5A CN115776298A (en) | 2022-12-16 | 2022-12-16 | Bidirectional multi-level conversion circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202211623750.5A CN115776298A (en) | 2022-12-16 | 2022-12-16 | Bidirectional multi-level conversion circuit |
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| CN115776298A true CN115776298A (en) | 2023-03-10 |
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| CN202211623750.5A Pending CN115776298A (en) | 2022-12-16 | 2022-12-16 | Bidirectional multi-level conversion circuit |
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