CN220492976U - Bidirectional level conversion circuit, domain controller and vehicle - Google Patents
Bidirectional level conversion circuit, domain controller and vehicle Download PDFInfo
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Abstract
The utility model provides a bidirectional level conversion circuit, a domain controller and a vehicle, which belong to the technical field of vehicles and comprise: the power supply comprises a first power supply VL, a second power supply VH, a first pull-up resistor R1, a second pull-up resistor R2, a first input/output end Signal_LV and a second input/output end Signal_HV, wherein the first pull-up resistor R1 is connected between the first input/output end Signal_LV and the first power supply VL; the second pull-up resistor R2 is connected between the second input/output terminal signal_hv and the second power supply VH; the first input/output end signal_LV is used for being connected with the first chip, and the second input/output end signal_HV is used for being connected with the second chip; the bidirectional level shift circuit further includes: the first conduction module and the second conduction module; the first conduction module and the second conduction module are connected in parallel between the first input/output end signal_LV and the second input/output end signal_HV. The bidirectional level conversion circuit provided by the utility model can perform bidirectional communication between the first chip and the second chip within a wide temperature range.
Description
Technical Field
The utility model belongs to the technical field of vehicles, and particularly relates to a bidirectional level conversion circuit, a domain controller and a vehicle.
Background
In electronic devices, because the interface voltages of the main control chip and the peripheral chip are not consistent, a level shift chip is generally required to be designed to realize communication between the two. The current low-cost level conversion circuit scheme is mainly based on MOS tube design, the level conversion circuit based on the MOS tube can realize bidirectional transmission, and the speed can reach MHz level, however, with the progress of chip technology, the chip interface voltage is gradually reduced, the interface voltage of a main stream CPU is reduced to below 1.8V, and the interface voltage of a peripheral chip is also generally reduced to 3.3V. However, when the MOS body diode works in a wide temperature range from-40 ℃ to 85 ℃, the forward conduction voltage drop of the MOS body diode can be up to more than 1V, and when signals are transmitted from a high level side to a low level side, the high forward conduction voltage can lead to the failure of the correct transmission of the level, so that the communication between chips is failed, and unpredictable results are generated.
Disclosure of Invention
In view of the foregoing, embodiments of the present application provide a bi-directional level shift circuit, a domain controller, and a vehicle to overcome or at least partially solve the foregoing problems.
In a first aspect of the present embodiment, a bidirectional level shifter circuit is provided, including: the device comprises a first power supply module (101), a second power supply module (102), a first input/output end signal_LV (103), a second input/output end signal_HV (104), a first conduction module (107), a second conduction module (108), a first chip (105) and a second chip (106); wherein the first conduction module (107) comprises a first end, a second end and a third end;
the first power module (101) is respectively connected with the first input/output end signal_lv (103), the first end and the second end, the second power module (102) is respectively connected with the second input/output end signal_hv (104) and the third end, and the second conduction module (108) is respectively connected with the first end and the third end;
the first power supply module (101) is configured to output a first voltage to the first input/output terminal signal_lv (103), and the second power supply module (102) is configured to output a second voltage to the second input/output terminal signal_hv (104), where the first voltage is smaller than the second voltage;
the first chip (105) is used for connecting the first input/output end signal_LV (103), and the second chip (106) is used for connecting the second input/output end signal_HV (104);
the second chip (106) outputs a low-level Signal to the second input/output end signal_hv (104), the second conduction module (108) pulls down the first voltage output by the first power module (101) to the first input/output end signal_lv (103) so as to conduct the first conduction module (107), and the first input/output end signal_lv (103) is converted from a high-level state to a low-level state, so that the second chip (106) transmits the low-level Signal to the first chip (105).
Further, the first power supply module (101) includes: a first power supply VL (1011) and a first pull-up resistor R1 (1012); wherein,
the first power supply VL (1011) is respectively connected to a first end and a first end of the first pull-up resistor R1 (1012), and a second end of the first pull-up resistor R1 (1012) is respectively connected to the second end and the first input/output terminal signal_lv (103).
Further, the second power supply module (102) includes: a second power supply VH (1021) and a second pull-up resistor R2 (1022); wherein,
the second power supply VH (1021) is connected to a first end of the second pull-up resistor R2 (1022), and a second end of the second pull-up resistor R2 (1022) is connected to the third end and the first input/output end signal_lv (103) respectively.
Further, the bidirectional level shift circuit further includes: a capacitor C1 (109); the first end of the capacitor C1 (109) is connected to the first input/output end signal_lv (103) and the second end of the first pull-up resistor R1 (1012), respectively, and the second end of the capacitor C1 (109) is grounded.
Further, the first conduction module (107) comprises a MOS tube Q1; wherein,
the grid electrode of the MOS tube Q1 is respectively connected with the first power supply VL (1011) and the first end of the first pull-up resistor R1 (1012), the source electrode of the MOS tube Q1 is respectively connected with the first input/output end Signal_LV (103) and the second end of the first pull-up resistor R1 (1012), and the drain electrode of the MOS tube Q1 is respectively connected with the second input/output end Signal_HV (104) and the second end of the second pull-up resistor R2 (1022).
Further, the first conduction module (107) comprises a triode Q2; wherein,
the base of the triode Q2 is respectively connected with the first power supply VL (1011) and the first end of the first pull-up resistor R1 (1012), the emitter of the triode Q2 is respectively connected with the first input/output end Signal_LV (103) and the second end of the first pull-up resistor R1 (1012), and the collector of the triode Q2 is respectively connected with the second input/output end Signal_HV (104) and the second end of the second pull-up resistor R2 (1022).
Further, the second conduction module (108) comprises a diode, wherein the anode of the diode is connected with the first input-output end Signal_LV (103), and the cathode of the diode is connected with the second input-output end Signal_HV (104).
Further, the diode is a schottky diode.
Further, the first power supply VL (1011) and the second power supply VH (1021) include direct current constant voltage sources.
In a second aspect of embodiments of the present application, a domain controller is provided, which includes a bidirectional level shifting circuit according to the first aspect of embodiments of the present application.
In a third aspect of embodiments of the present application, a vehicle is provided, the vehicle comprising a domain controller according to the second aspect of embodiments of the present application.
There is provided by an embodiment of the present application a bidirectional level shifter circuit, including: the device comprises a first power supply module (101), a second power supply module (102), a first input/output end signal_LV (103), a second input/output end signal_HV (104), a first conduction module (107), a second conduction module (108), a first chip (105) and a second chip (106); wherein the first conduction module (107) comprises a first end, a second end and a third end; the first power module (101) is respectively connected with the first input/output end signal_LV (103), the first end and the second end, the second power module (102) is respectively connected with the second input/output end signal_HV (104) and the third end, and the second conduction module (108) is respectively connected with the first end and the third end; the first power supply module (101) is used for outputting a first voltage to the first input/output end signal_LV (103), the second power supply module (102) is used for outputting a second voltage to the second input/output end signal_HV (104), and the first voltage is smaller than the second voltage; the first chip (105) is used for connecting the first input/output end signal_LV (103), and the second chip (106) is used for connecting the second input/output end signal_HV (104); the second chip (106) outputs a low-level Signal to the second input/output end signal_hv (104), the second conduction module (108) pulls down the first voltage output by the first power module (101) to the first input/output end signal_lv (103) so as to conduct the first conduction module (107), and the first input/output end signal_lv (103) is converted from a high-level state to a low-level state, so that the second chip (106) transmits the low-level Signal to the first chip (105).
The bidirectional level conversion circuit provided by the embodiment of the application is applied to the communication between the first chip (105) and the second chip (106) corresponding to different interface voltages, and can convert the first input/output end signal_LV (103) and the second input/output end signal_HV (104) into the same level state through the first power module (101), the second power module (102), the first input/output end signal_LV (103), the second input/output end signal_HV (104), the first conduction module (107) and the second conduction module (108) when the communication between the first chip (105) and the second chip (106) is performed, so that the normal bidirectional communication between the first chip (105) and the second chip (106) is realized, in addition, when the first conduction module (107) operates in a wide temperature range from-40 ℃ to 85 ℃, the forward conduction voltage drop can be up to more than 1V, when signals are transmitted from high level side to low level side, the high forward conduction voltage can lead to the failure of the level transmission, at the moment, the second conduction module (108) can pull down the voltage of the first input/output end signal_LV (103), the voltage of the first input/output end signal_LV (103) is controlled in a low level state, the voltage difference between the first power supply VL (1011) and the first input/output end signal_LV (103) is larger than the starting voltage of the first conduction module (107), and then the first conduction module (107) is conducted, the second input/output end signal_hv (104) is pulled down to be in a low level state by the first input/output end signal_lv (103), so that the reliability of bidirectional normal communication between the first chip (105) and the second chip (106) is improved, and the loss caused by incapability of communicating between the first chip (105) and the second chip (106) is avoided.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments of the present application will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a bi-directional level shifter circuit according to an embodiment of the present application;
fig. 2 is a schematic diagram of a bidirectional level conversion circuit of a MOS transistor according to an embodiment of the present application;
fig. 3 is a schematic diagram of a triode bidirectional level shift circuit according to an embodiment of the present disclosure;
reference numerals:
a first power module-101; a second power module-102; a first power supply VL-1011; first pull-up resistors R1-1012; a second power supply VH-1021; a second pull-up resistor R2-1022; a first input/output terminal Signal_LV-103; a second input/output terminal signal_HV-104; a first chip-105; a second chip-106; a first turn-on module-107; a second conduction module-108; capacitors C1-109.
Detailed Description
Exemplary embodiments of the present application will be described in more detail below with reference to the accompanying drawings in the embodiments of the present application. While exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
Example 1
Referring to fig. 1, fig. 1 is a schematic diagram of a bidirectional level shifter circuit according to an embodiment of the present application, where the bidirectional level shifter circuit includes: the device comprises a first power supply module (101), a second power supply module (102), a first input/output end signal_LV (103), a second input/output end signal_HV (104), a first conduction module (107), a second conduction module (108), a first chip (105) and a second chip (106); the first conduction module (107) comprises a first end, a second end and a third end.
As can be seen from fig. 1, the first power module (101) is connected to the first input/output terminal signal_lv (103), the first terminal and the second terminal, the second power module (102) is connected to the second input/output terminal signal_hv (104) and the third terminal, the second conduction module (108) is connected to the first terminal and the third terminal, the first input/output terminal signal_lv (103) is connected to the first chip (105), the second input/output terminal signal_hv (104) is connected to the second chip (106), and the first conduction module (107) and the second conduction module (108) are connected in parallel between the first input/output terminal signal_lv (103) and the second input/output terminal signal_hv (104).
When the second chip (106) outputs a low-level Signal, the voltage of the first power supply VL (1011) is pulled down to the second input/output end signal_hv (104) through the first pull-up resistor R1 (1012) and the second conduction module (108), so that the first conduction module (107) is conducted, and the first input/output end signal_lv (103) is converted from a high-level state to a low-level state, thereby realizing that the second chip (106) transmits the low-level Signal to the first chip (105).
In this embodiment, by the connection manner of the electronic components in fig. 1, the bidirectional level conversion circuit is configured, so that bidirectional communication between the first chip (105) and the second chip (106) can be realized, the first chip (105) can correspond to a main control chip in the electronic device, the second chip (106) can correspond to a peripheral chip in the electronic device, since the interface voltage of the main CPU is already lower than 1.8V, and the interface voltage of the peripheral chip is also generally lower than 3.3V, the interface voltages of the first chip (105) and the second chip (106) are not consistent, the first input/output terminal signal_lv (103) can be used as an interface between the bidirectional level conversion circuit and the first chip (105), and the second input/output terminal signal_hv (104) can be used as an interface between the bidirectional level conversion circuit and the second chip (106). Therefore, the voltage output by the first power supply module (101) is smaller than the voltage output by the second power supply module (102).
At this time, the first power supply VL (1011) is the low voltage side of the bidirectional level shifter circuit, and the second power supply VH (1021) is the high voltage side of the bidirectional level shifter circuit.
When the second chip (106) outputs a low-level Signal to the first chip (105) through the bidirectional level conversion circuit, the voltage output by the first power supply VL (1011) flows into the first input/output terminal signal_lv (103) through the first pull-up resistor R1 (1012), at this time, the first conduction module (107) is not conducted, however, the second conduction module (108) can reduce the voltage at the first input/output terminal signal_lv (103), the voltage difference between the first power supply VL (1011) and the first input/output terminal signal_lv (103) is greater than the starting voltage of the first conduction module (107), at this time, the first conduction module (107) is conducted, the first input/output terminal signal_lv (103) is converted into a low-level state, at this time, the first input/output terminal signal_lv (103) and the second input/output terminal signal_hv (104) are both in a low-level state, and the second chip (106) can conduct low-level Signal communication with the first chip (105).
In addition, the first chip (105) can also transmit low-level signals to the second chip (106), and the first chip (105) and the second chip (106) transmit high-level signals mutually.
When the first chip (105) outputs a low-level Signal to the second chip (106) through the bidirectional level conversion circuit, the first conduction module (107) conducts to conduct a loop between the first input/output end signal_lv (103) and the second input/output end signal_hv (104), so that the second input/output end signal_hv (104) is converted into a low-level state, and at the moment, the first input/output end signal_lv (103) and the second input/output end signal_hv (104) are both in a low-level state, and the first chip (105) can perform low-level Signal communication with the second chip (106).
When the first chip (105) outputs a high-level Signal, the first conduction module (107) and the second conduction module (108) are in a cut-off state, at this time, since the second power supply VH (1021) is always in a discharge state, at this time, since the second pull-up resistor R2 (1022) is connected between the second power supply VH (1021) and the second input/output terminal signal_hv (104), at this time, the second pull-up resistor R2 (1022) can pull up the second input/output terminal signal_hv (104) to a high-level state, at this time, the first input/output terminal signal_lv (103) and the second input/output terminal signal_hv (104) are both in a high-level state, and then high-level Signal communication between the first chip (105) and the second chip (106) can be realized.
When the second chip (106) outputs a high-level Signal, the first conduction module (107) and the second conduction module (108) are in a cut-off state, at this time, since the first power supply VL (1011) is always in a discharge state, at this time, since the first pull-up resistor R1 (1012) is connected between the first power supply VL (1011) and the first input/output terminal signal_lv (103), at this time, the first pull-up resistor R1 (1012) can pull up the first input/output terminal signal_lv (103) to a high-level state, at this time, the first input/output terminal signal_lv (103) and the second input/output terminal signal_hv (104) are both in a high-level state, and then high-level Signal communication between the first chip (105) and the second chip (106) can be realized.
Through the bidirectional level conversion circuit provided by the embodiment of the application, the bidirectional level conversion circuit is applied to the communication between the first chip (105) and the second chip (106) corresponding to different interface voltages, and in addition, when the communication is performed between the first chip (105) and the second chip (106), the forward conduction voltage of the first conduction module (107) can reach more than 1V at the moment, when the Signal is transmitted from the high level side to the low level side, the high forward conduction voltage can not be transmitted correctly, the first input/output end signal_lv (103) and the second input/output end signal_hv (104) are converted into the same level state, so that the normal bidirectional communication between the first chip (105) and the second chip (106) is realized, when the Signal works in a wide temperature range of-40 ℃ to 85 ℃, the first conduction module (107) can not transmit the level correctly, when the Signal is transmitted from the high level side to the low level side, the second conduction module (108) can control the first input/output voltage of the first input/output end signal_lv (103) to the first input/output end Signal (103) to the first Signal at the moment, the first Signal is in the low-level state (LV) and the first Signal (103) is controlled to be in the high-level state, the second input/output end signal_hv (104) is pulled down to be in a low level state by the first input/output end signal_lv (103), so that the reliability of bidirectional normal communication between the first chip (105) and the second chip (106) is improved, and unpredictable loss caused by incapability of communicating between the first chip (105) and the second chip (106) is avoided.
In one embodiment, the first power module (101) comprises: a first power supply VL (1011) and a first pull-up resistor R1 (1012); the first power supply VL (1011) is respectively connected to a first end and a first end of the first pull-up resistor R1 (1012), and a second end of the first pull-up resistor R1 (1012) is respectively connected to the second end and the first input/output terminal signal_lv (103).
In this embodiment, referring to fig. 1, the first power module (101) includes a first power VL (1011) and a first pull-up resistor R1 (1012), the first pull-up resistor R1 (1012) is connected between the first input/output terminal signal_lv (103) and the first power VL (1011), the first power module (101) is used to pull up the first input/output terminal signal_lv (103) to a high state, and assist the on-off state of the first conduction module (107), so that the high level Signal can be transferred between the first input/output terminal signal_lv (103) and the second input/output terminal signal_hv (104), and how the first power module (101) enables to pull up the first input/output terminal signal_lv (103) to the high state, and the on-off state of the first conduction module (107) can be achieved by connecting the first end of the first pull-up resistor R1 (1012) to the first end of the first pull-up resistor R1 (1011) and connecting the first input terminal signal_lv (103) to the first input terminal signal_lv (103) respectively.
In one embodiment, the second power module (102) includes: a second power supply VH (1021) and a second pull-up resistor R2 (1022); the second power supply VH (1021) is connected to a first end of the second pull-up resistor R2 (1022), and a second end of the second pull-up resistor R2 (1022) is connected to the third end and the first input/output end signal_lv (103) respectively.
In this embodiment, referring to fig. 1, the second power module (102) includes a second power VH (1021) and a second pull-up resistor R2 (1022), the second pull-up resistor R2 (1022) is connected between the second input/output terminal signal_hv (104) and the second power VH (1021), the second power module (102) is configured to pull up the second input/output terminal signal_hv (104) to a high level state, so that a high level Signal can be transferred between the first input/output terminal signal_lv (103) and the second input/output terminal signal_hv (104), and how the first power module (101) is configured to pull up the first input/output terminal signal_lv (103) to a high level state may be implemented by connecting the second power VH (1021) to the first end of the second pull-up resistor R2 (1022), and connecting the second end of the second pull-up resistor R2 (1022) to the third end and the first input/output terminal signal_lv (103) respectively.
In one embodiment, the bi-directional level shift circuit further comprises: a capacitor C1 (109); the first end of the capacitor C1 (109) is connected to the first input/output end signal_lv (103) and the second end of the first pull-up resistor R1 (1012), respectively, and the second end of the capacitor C1 (109) is grounded.
In this embodiment, referring to fig. 1, the bidirectional level shift circuit further includes: the capacitor C1 (109), the first terminal of the capacitor C1 (109) is connected to the first input/output terminal signal_lv (103) and the second terminal of the first pull-up resistor R1 (1012), respectively, the second terminal of the capacitor C1 (109) is grounded, when the bi-directional level conversion circuit converts the second input/output terminal signal_hv (104) from the low level state to the high level state, the second conduction module (108) is in the off state, the second conduction module (108) generally selects a schottky diode, and when the schottky diode is selected, since the PN junction capacitor C1 (109) inside the schottky diode can release the stored charges, the second conduction module (108) can release the stored charges at this time, so as to avoid that the charges are released to the first input/output terminal signal_lv (103), the voltage of the first input/output terminal signal_lv (103) is higher than the voltage of the first power VL (1011), and the first chip (105) is damaged, so that an extra charge absorbed by the capacitor C1 (109) needs to be added.
In addition, when the bidirectional level conversion circuit is actually used, the resistance values of the first pull-up resistor R1 (1012) and the second pull-up resistor R2 (1022) can be adjusted within the range of 1KHz-4.7KHz according to actual requirements, the capacitance value of the capacitor C1 (109) can be adjusted within the range of 1pF-22pF, the higher the required communication rate is, the faster the high-low level conversion rate at the signal_hv (104) of the second input/output terminal is, the smaller the capacitance value of the capacitor C1 (109) needs to be selected, and the bidirectional level conversion circuit provided in this embodiment can realize bidirectional communication from hundreds KHz to tens MHz.
In one embodiment, the first conduction module (107) includes a MOS transistor Q1; the gate of the MOS transistor Q1 is connected to the first power VL (1011) and the first end of the first pull-up resistor R1 (1012), the source of the MOS transistor Q1 is connected to the first input/output end signal_lv (103) and the second end of the first pull-up resistor R1 (1012), and the drain of the MOS transistor Q1 is connected to the second input/output end signal_hv (104) and the second end of the second pull-up resistor R2 (1022).
In this embodiment, referring to fig. 2, fig. 2 is a schematic diagram of a bidirectional level conversion circuit of a MOS transistor provided in this embodiment, and in combination with fig. 1, a description is given of a first conduction module (107) as a MOS transistor Q1:
the grid electrode of the MOS tube Q1 is respectively connected with the first ends of VL and R1, the source electrode of the MOS tube Q1 is respectively connected with the second ends of Signal_LV and R1, the drain electrode of the MOS tube Q1 is respectively connected with the second ends of Signal_HV and R2, the first end of the second pull-up resistor R2 (1022) is connected with the second power supply VH (1021), the MOS tube Q1 can be a general NMOS, and the model is BSS138P.
The following describes the level conversion of the signal transmission of the first chip (105) and the second chip (106) by the bidirectional level conversion circuit of the MOS transistor Q1:
when the first chip (105) sends out a high level Signal, the signal_lv is in a high level state, the MOS transistor Q1 is turned off and is in an off state, meanwhile, since the voltage of VH is higher than that of VL, D1 is also in an off state, the signal_hv is pulled up to VH through R2, and at the moment, the signal_hv is also in a high level state, and both the signal_lv and the signal_hv are in a high level state, so that the first chip (105) can transmit the high level Signal to the second chip (106).
When the first chip (105) sends out a low level Signal, the signal_lv is in a low level state, the MOS transistor Q1 is turned on, and the signal_hv is also pulled to be in a low level state, so that the signal_lv and the signal_hv are both in a low level state, and the first chip (105) can transmit the low level Signal to the second chip (106).
When the second chip (106) sends out the high level Signal, the signal_hv is in the high level state, and at this time, the MOS transistors Q1 and D1 are both in the off state, and since the signal_lv is pulled up to VL by R1, and the signal_lv is in the high level state, the signal_lv and the signal_hv are both in the high level state, so that the second chip (106) can transmit the high level Signal to the first chip (105).
When the second chip (106) sends out a low level Signal, the signal_hv is in a low level state, VL is conducted to the signal_hv through R1 and D1, the conduction voltage drop of D1 is smaller than 0.3V in the range of-40 ℃ to 85 ℃, the voltage of the signal_lv is smaller than 0.3V at the moment, the voltage of the signal_lv is reduced, the MOS transistor Q1 is caused to conduct, the voltage of the signal_lv is further reduced, the signal_hv is also pulled to be in a low level state at the moment, the signal_lv and the signal_hv are both in a low level state, and the second chip (106) can transmit the low level Signal to the first chip (105).
In one embodiment, the first conduction module (107) comprises a transistor Q2; the base of the triode Q2 is respectively connected with the first power supply VL (1011) and the first end of the first pull-up resistor R1 (1012), the emitter of the triode Q2 is respectively connected with the first input/output end signal_lv (103) and the second end of the first pull-up resistor R1 (1012), and the collector of the triode Q2 is respectively connected with the second input/output end signal_hv (104) and the second end of the second pull-up resistor R2 (1022).
In this embodiment, referring to fig. 3, fig. 3 is a schematic diagram of a triode bidirectional level conversion circuit provided in the embodiment of the present application, and in combination with fig. 1, the first conduction module (107) is described as a triode Q2:
the base of the triode Q2 is respectively connected with the first power supply VL (1011) and the first end of the first pull-up resistor R1 (1012), the emitter of the triode Q2 is respectively connected with the first input/output end Signal_LV (103) and the second end of the first pull-up resistor R1 (1012), the collector of the triode Q2 is respectively connected with the second input/output end Signal_HV (104) and the second end of the second pull-up resistor R2 (1022), and the first end of the second pull-up resistor R2 (1022) is connected with the second power supply VH (1021).
The following describes the level conversion of the triode Q2 bidirectional level conversion circuit for signal transmission between the first chip (105) and the second chip (106):
when the first chip (105) sends out a high level Signal, the signal_LV is in a high level state, the triode Q2 is closed and is in an off state, meanwhile, since the voltage of VH is higher than that of VL, D1 is also in an off state, the signal_HV is pulled up to VH through R2, the signal_HV is also in a high level state, and the signal_LV and the signal_HV are both in a high level state, so that the first chip (105) can transmit the high level Signal to the second chip (106).
When the first chip (105) sends out a low level Signal, the signal_lv is in a low level state, the triode Q2 is turned on, the signal_hv is also pulled to be in a low level state, and then the signal_lv and the signal_hv are both in the low level state, so that the first chip (105) can transmit the low level Signal to the second chip (106).
When the second chip (106) sends out the high level Signal, the signal_hv is in the high level state, and at this time, the transistors Q2 and D1 are both in the off state, and since the signal_lv is pulled up to VL by R1 and is in the high level state, the signal_lv and the signal_hv are both in the high level state, so that the second chip (106) can transmit the high level Signal to the first chip (105).
When the second chip (106) sends out a low level Signal, the signal_hv is in a low level state, VL is conducted to the signal_hv through R1 and D1, the conduction voltage drop of D1 is smaller than 0.3V in the range of-40 ℃ to 85 ℃, the voltage of the signal_lv is smaller than 0.3V at the moment, the voltage of the signal_lv is reduced, the triode Q2 is caused to conduct, and the voltage of the signal_lv is further reduced, so that the signal_lv and the signal_hv are both in a low level state, and the second chip (106) can transmit the low level Signal to the first chip (105).
In one embodiment, the second conduction module (108) comprises a diode, wherein an anode of the diode is connected to the first input/output signal_lv (103), and a cathode of the diode is connected to the second input/output signal_hv (104).
In this embodiment, in combination with fig. 1, the second conduction module (108) includes a diode, where an anode of the diode is connected to the first input/output signal_lv (103), and a cathode of the diode is connected to the second input/output signal_hv (104), and functions to reduce the voltage at the first input/output signal_lv (103) when the second input/output signal_hv (104) is in a low state.
In one embodiment, the diode is a schottky diode.
In this embodiment, referring to fig. 2 and 3, the diode is a schottky diode D1, the schottky diode D1 is a schottky diode with low reverse current, when both signal_lv and signal_hv are in a high-level state, the schottky diode D1 is in a reverse off-state, and if the reverse leakage current is large, a large voltage drop is also generated on R2, which results in that the signal_hv voltage is too low and no longer in a high-level state, thereby causing communication errors. The model selection for schottky diode D1 may be BAT54-Q.
In one embodiment, the first power supply VL (1011) and the second power supply VH (1021) comprise dc constant voltage sources.
In this embodiment, referring to fig. 1, since the bidirectional level shift circuit is in an operation state, the first power supply VL (1011) and the second power supply VH (1021) are in a state where a discharge needs to be maintained, and since it is not determined whether the first chip (105) or the second chip (106) outputs high level information, in order to ensure bidirectional communication between the first chip (105) and the second chip (106), the first power supply VL (1011) and the second power supply VH (1021) may be dc constant voltage sources, for example, the first power supply VL (1011) is 1.8V or 1.2V, and the second power supply VH (1021) is 3.3V or 5V, and the voltage values of the first power supply VL (1011) and the second power supply VH (1021) are not limited, but are merely illustrative.
The following will be a schematic diagram of a bidirectional level shift circuit for a MOS transistor provided in fig. 2, assuming that the first power supply is 1.8V and the second power supply is 3.3V, the working states in fig. 2 are as follows:
for example, vl=1.8v, vh=3.3v, the circuit in fig. 1 operates in the following state:
when the signal_LV receives a high level Signal of the first chip (105), the signal_LV does not pull down the voltage of VL at this time, the signal_LV pulls up the voltage to 1.8V through R1 and is in a high level state, the gate and source voltages of Q1 are 1.8V, vgs is 0 and smaller than the forward voltage drop voltage, Q1 is in an cut-off state, D1 is also in a cut-off state, the signal_HV pulls up the voltage to 3.3V through R2 and is also in a high level state, and the signal_LV and the signal_HV are both in a high level state.
When the signal_lv receives the low level Signal of the first chip (105), the source electrode of Q1 becomes low level, and the gate electrode of Q1 is the terminal voltage of VL, i.e. 1.8V, vgs is 1.8V, which is greater than the forward voltage drop voltage, and the forward voltage drop voltage of Q1 is generally 0.6V-0.8V, and when the MOS transistor Q1 is turned on, the signal_hv is pulled down to low level by the turned-on Q1, and when the signal_lv and the signal_hv are both in low level state.
When signal_hv receives a low level Signal of the second chip (106), signal_lv is pulled down to a level by D1, a PN junction is present in D1 to form a capacitor, and charges flowing through D1 are stored, so that signal_lv can be pulled down to a level of typically 0.3V, and a gate of Q1 is a terminal voltage of VL, that is, 1.8V, vgs is 1.5V and greater than a forward voltage drop voltage (0.6V to 0.8V), at which time Q1 is in a conductive state, at which time signal_hv is pulled down to a low level by signal_lv through the conductive Q1, at which time signal_lv and signal_hv are both in a low level state.
Similarly, when the signal_hv receives the high level Signal of the second chip (106), the signal_hv pulls up the voltage to 3.3V through R2, where Q1 is cut off, and D1 is also in an off state, but D1 is in a discharging state, in order to avoid the released current of D1 flowing to the first chip (105), the pin of the first chip (105) is damaged, where C1 stores the released current of D1 and releases it to the ground, so that the signal_lv smoothly pulls up the voltage to 1.8V through R1, and is in a high level state, where both the signal_lv and the signal_hv are in a high level state.
Example two
Embodiments of the present application provide a domain controller including a bi-directional level shifter circuit as described herein.
Example III
Embodiments of the present application provide a vehicle comprising a domain controller as described in embodiment two of the present application
In this specification, each embodiment is described in a progressive manner, and each embodiment is mainly described by differences from other embodiments, and identical and similar parts between the embodiments are all enough to be referred to each other.
While preferred embodiments of the present utility model have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiment and all such alterations and modifications as fall within the scope of the embodiments of the utility model.
Finally, it is further noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, article, or terminal. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, article or terminal device comprising the element.
The above description of the bidirectional level conversion circuit, the domain controller and the vehicle provided by the utility model applies specific examples to illustrate the principle and implementation of the utility model, and the above examples are only used to help understand the utility model and its core ideas; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in accordance with the ideas of the present utility model, the present description should not be construed as limiting the utility model of the present application in view of the above.
Claims (11)
1. A bi-directional level shift circuit, comprising: the device comprises a first power supply module (101), a second power supply module (102), a first input/output end signal_LV (103), a second input/output end signal_HV (104), a first conduction module (107), a second conduction module (108), a first chip (105) and a second chip (106); wherein the first conduction module (107) comprises a first end, a second end and a third end;
the first power module (101) is respectively connected with the first input/output end signal_lv (103), the first end and the second end, the second power module (102) is respectively connected with the second input/output end signal_hv (104) and the third end, and the second conduction module (108) is respectively connected with the first end and the third end;
the first power supply module (101) is configured to output a first voltage to the first input/output terminal signal_lv (103), and the second power supply module (102) is configured to output a second voltage to the second input/output terminal signal_hv (104), where the first voltage is smaller than the second voltage;
the first chip (105) is used for connecting the first input/output end signal_LV (103), and the second chip (106) is used for connecting the second input/output end signal_HV (104); wherein,
the second chip (106) outputs a low-level Signal to the second input/output end signal_hv (104), the second conduction module (108) pulls down the first voltage output by the first power module (101) to the first input/output end signal_lv (103) so as to conduct the first conduction module (107), and the first input/output end signal_lv (103) is converted from a high-level state to a low-level state, so that the second chip (106) transmits the low-level Signal to the first chip (105).
2. The bi-directional level shift circuit of claim 1, wherein the first power supply module (101) comprises: a first power supply VL (1011) and a first pull-up resistor R1 (1012); wherein,
the first power supply VL (1011) is respectively connected to a first end and a first end of the first pull-up resistor R1 (1012), and a second end of the first pull-up resistor R1 (1012) is respectively connected to the second end and the first input/output terminal signal_lv (103).
3. The bi-directional level shift circuit of claim 2, wherein the second power supply module (102) comprises: a second power supply VH (1021) and a second pull-up resistor R2 (1022); wherein,
the second power supply VH (1021) is connected to a first end of the second pull-up resistor R2 (1022), and a second end of the second pull-up resistor R2 (1022) is connected to the third end and the first input/output end signal_lv (103) respectively.
4. A bi-directional level shift circuit as claimed in claim 2 or 3, wherein the bi-directional level shift circuit further comprises: a capacitor C1 (109); the first end of the capacitor C1 (109) is connected to the first input/output end signal_lv (103) and the second end of the first pull-up resistor R1 (1012), respectively, and the second end of the capacitor C1 (109) is grounded.
5. A bi-directional level shift circuit as claimed in claim 3, wherein the first turn-on module (107) comprises a MOS transistor Q1; wherein,
the grid electrode of the MOS tube Q1 is respectively connected with the first power supply VL (1011) and the first end of the first pull-up resistor R1 (1012), the source electrode of the MOS tube Q1 is respectively connected with the first input/output end Signal_LV (103) and the second end of the first pull-up resistor R1 (1012), and the drain electrode of the MOS tube Q1 is respectively connected with the second input/output end Signal_HV (104) and the second end of the second pull-up resistor R2 (1022).
6. A bi-directional level shift circuit as claimed in claim 3, wherein the first conduction block (107) comprises a transistor Q2; wherein,
the base of the triode Q2 is respectively connected with the first power supply VL (1011) and the first end of the first pull-up resistor R1 (1012), the emitter of the triode Q2 is respectively connected with the first input/output end Signal_LV (103) and the second end of the first pull-up resistor R1 (1012), and the collector of the triode Q2 is respectively connected with the second input/output end Signal_HV (104) and the second end of the second pull-up resistor R2 (1022).
7. The bi-directional level shift circuit of claim 1, wherein the second conduction block (108) comprises a diode, wherein an anode of the diode is connected to the first input output Signal LV (103) and a cathode of the diode is connected to the second input output Signal HV (104).
8. The bi-directional level shift circuit of claim 7, wherein said diode is a schottky diode.
9. A bi-directional level shift circuit as claimed in claim 3, wherein the first power supply VL (1011) and the second power supply VH (1021) comprise dc constant voltage sources.
10. A domain controller comprising a bi-directional level shifter circuit as claimed in any one of claims 1 to 9.
11. A vehicle comprising the domain controller of claim 10.
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| CN202322138626.6U CN220492976U (en) | 2023-08-09 | 2023-08-09 | Bidirectional level conversion circuit, domain controller and vehicle |
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| CN202322138626.6U CN220492976U (en) | 2023-08-09 | 2023-08-09 | Bidirectional level conversion circuit, domain controller and vehicle |
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