CN104635836A - Band-gap reference circuit - Google Patents
Band-gap reference circuit Download PDFInfo
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- CN104635836A CN104635836A CN201310567283.3A CN201310567283A CN104635836A CN 104635836 A CN104635836 A CN 104635836A CN 201310567283 A CN201310567283 A CN 201310567283A CN 104635836 A CN104635836 A CN 104635836A
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Abstract
The invention provides a band-gap reference circuit. The band-gap reference circuit comprises a band-gap core unit, a starting unit, an output unit and a clamping unit, wherein the starting unit comprises a first PMOS tube, a first resistor, a current-limiting diode, a first NMOS tube and a circuit mirror unit; the clamping unit is applicable to conduct clamping on a grid electrode of the first NMOS tube. According to the technical scheme, the reference voltage provided by the band-gap reference circuit is small in overshoot when being started and improves the reliability of a circuit system.
Description
Technical field
The present invention relates to technical field of integrated circuits, particularly a kind of band-gap reference circuit.
Background technology
Band-gap reference circuit have low-temperature coefficient, low supply voltage and can with the advantage such as standard CMOS process is compatible, be widely used in the Digital Analog Hybrid Circuits systems such as D/A switch, analog/digital conversion, storer and Switching Power Supply.The stability of band-gap reference circuit output voltage and noise resisting ability are the key factors affecting various application system precision, along with the raising of application system precision, also more and more higher to the stability requirement of the temperature of band-gap reference circuit, voltage and technique.
The principle of work of band-gap reference circuit is the characteristic temperature independent according to the band gap voltage of silicon materials, utilize the negative temperature coefficient of the base emitter voltage of bipolar transistor mutually to compensate from the positive temperature coefficient (PTC) of the difference of two bipolar transistor base emitter voltage under different current density, make the temperature drift that the voltage of output reaches very low.
Fig. 1 is the circuit diagram of existing a kind of band-gap reference circuit.With reference to figure 1, described band-gap reference circuit comprises band gap core cell 11, start unit 12 and output unit 13.Described band gap core cell 11 comprises: the first PMOS P11, the second PMOS P12, operational amplifier OPA, the first resistance R11, the second resistance R12, the 3rd resistance R13, the first PNP pipe Q11 and the second PNP pipe Q12.Described start unit 12 comprises: the 3rd PMOS P13, the 4th resistance R14, the first NMOS tube N11 and current lens unit 14, and described current lens unit 14 comprises the second NMOS tube N12 and the 3rd NMOS tube N13.Described output unit 13 comprises: the 4th PMOS P14 and the 5th resistance R15.
First power lead Vdd and second source line Vss provides supply voltage for described band-gap reference circuit, the supply voltage that the supply voltage that described first power lead Vdd provides provides higher than described second source line Vss, usually, the supply voltage that described second source line Vss provides is ground voltage.In described band-gap reference circuit, the annexation of each device is with reference to shown in figure 1, does not repeat them here.
Described start unit 12 is suitable under the control of bias voltage PD, provides trigger voltage to described band gap core cell 11 and described output unit 13, enters normal operating conditions during to ensure that described band-gap reference circuit can start (powering on) in Circuits System; Described band gap core cell 11 is suitable for producing the electric current with positive temperature coefficient (PTC) and the electric current with negative temperature coefficient, and superposes to produce reference current with the electric current with negative temperature coefficient to the described electric current with positive temperature coefficient (PTC); Described output unit 13 is suitable for the reference current that described band gap core cell 11 produces being converted to reference voltage V ref and exports.
Fig. 2 is the waveform schematic diagram of the reference voltage V ref that the band-gap reference circuit shown in Fig. 1 exports, and when described band-gap reference circuit starts, voltage overshoot phenomenon appears in described reference voltage V ref, and overshoot voltage is very large, affects the stability of Circuits System.
Summary of the invention
There is the problem of larger overshoot in the reference voltage that what the present invention solved is band-gap reference circuit exports when starting.
For solving the problem, the invention provides a kind of band-gap reference circuit, comprising band gap core cell, start unit and output unit, also comprising clamping unit;
Described start unit comprises the first PMOS, the first resistance, Current Limiting Diodes, the first NMOS tube and current lens unit, wherein, the grid of described first PMOS is suitable for input offset voltage, the source electrode of described first PMOS is suitable for connection first power lead, and the drain electrode of described first PMOS connects one end of described first resistance; The other end of described first resistance connects the anode of described Current Limiting Diodes; The negative electrode of described Current Limiting Diodes connects the grid of described first NMOS tube and the image current output terminal of described current lens unit; The drain electrode of described first NMOS tube is suitable for providing trigger voltage to described band gap core cell and described output unit, the source electrode of described first NMOS tube is suitable for connecting second source line, the supply voltage that the supply voltage that described second source line provides provides lower than described first power lead; The reference current input end of described current lens unit is suitable for receiving the reference current that described band gap core cell provides;
Described clamping unit is suitable for carrying out clamper to the grid of described first NMOS tube.
Optionally, the clamp voltage of described clamping unit is relevant to the threshold voltage of described first NMOS tube.
Optionally, described clamping unit comprises N number of diode of connecting successively, and the anode of first diode connects the grid of described first NMOS tube, and the negative electrode of N number of diode is suitable for connecting second source line, N >=1.
Optionally, described clamping unit comprises the second resistance, and one end of described second resistance connects the grid of described first NMOS tube, and the other end of described second resistance is suitable for connecting described second source line.
Optionally, described current lens unit comprises the second NMOS tube and the 3rd NMOS tube;
The drain electrode of described second NMOS tube connects the grid of described second NMOS tube and the grid of described 3rd NMOS tube and as the reference current input end of described current lens unit, the source electrode of described second NMOS tube is suitable for connecting described second source line;
The drain electrode of described 3rd NMOS tube is as the image current output terminal of described current lens unit, and the source electrode of described 3rd NMOS tube is suitable for connecting described second source line.
Optionally, described band gap core cell comprises the second PMOS, the 3rd PMOS, operational amplifier, the 3rd resistance, the 4th resistance, the 5th resistance, the first PNP pipe and the second PNP pipe;
The source electrode of described second PMOS is suitable for connecting described first power lead, the grid of described second PMOS connects the drain electrode of the described grid of the 3rd PMOS, the output terminal of described operational amplifier and described first NMOS tube, and the drain electrode of described second PMOS connects the first input end of described operational amplifier, one end of described 3rd resistance and one end of described 4th resistance;
The source electrode of described 3rd PMOS is suitable for connecting described first power lead, and the drain electrode of described 3rd PMOS connects the second input end of described operational amplifier, the emitter of described second PNP pipe and one end of described 5th resistance;
The bias current end of described operational amplifier connects the reference current input end of described current lens unit;
The other end of described 3rd resistance connects the emitter of described first PNP pipe;
The collector of the other end of described 4th resistance, the other end of described 5th resistance, the base stage of described first PNP pipe, the collector of described first PNP pipe, the base stage of described second PNP pipe and described second PNP pipe is all suitable for connecting described second source line.
Optionally, described output unit comprises the 4th PMOS and the 6th resistance;
The grid of described 4th PMOS connects the drain electrode of described first NMOS tube, and the source electrode of described 4th PMOS is suitable for connecting described first power lead, and the drain electrode of described 4th PMOS connects one end of described 6th resistance and is suitable for output reference voltage;
The other end of described 6th resistance is suitable for connecting described second source line.
Optionally, the supply voltage that described second source line provides is ground voltage.
Compared with prior art, technical scheme of the present invention has the following advantages:
The band-gap reference circuit that technical solution of the present invention provides, except comprising band gap core cell, start unit and output unit, also comprises the clamping unit with clamper function.When described band-gap reference circuit starts, the grid of described clamping unit to the first NMOS tube in described start unit carries out clamper, the grid of described first NMOS tube is suppressed to occur peak voltage, thus make the grid potential of the power MOS pipe in described band gap core cell and described output unit can not by excessively drop-down, therefore, the reference voltage that the band-gap reference circuit that technical solution of the present invention provides exports overshoot when starting is very little, improves the reliability of Circuits System.
The first resistance in described start-up circuit connects the grid of described first NMOS tube and the image current output terminal of current lens unit by Current Limiting Diodes, described Current Limiting Diodes can limit the electric current flowing through described first PMOS, reduces the overshoot of described reference voltage when starting further.
Accompanying drawing explanation
Fig. 1 is the circuit diagram of existing a kind of band-gap reference circuit;
Fig. 2 is the waveform schematic diagram of the reference voltage V ref shown in Fig. 1;
Fig. 3 is the voltage waveform view of the node a shown in Fig. 1;
Fig. 4 is the current waveform schematic diagram flowing through the first NMOS tube N11 shown in Fig. 1;
Fig. 5 is the circuit diagram of a kind of band-gap reference circuit that the embodiment of the present invention provides;
Fig. 6 is the voltage waveform view of the node a shown in Fig. 5;
Fig. 7 is the current waveform schematic diagram flowing through the first NMOS tube N51 shown in Fig. 5;
Fig. 8 is the waveform schematic diagram of the reference voltage V ref shown in Fig. 5;
Fig. 9 is the circuit diagram of the another kind of band-gap reference circuit that the embodiment of the present invention provides.
Embodiment
With reference to figure 1, existing band-gap reference circuit start-up course is as follows:
After the Circuits System at described band-gap reference circuit place powers on, namely after described first power lead Vdd and described second source line Vss provides supply voltage, bias voltage PD is applied to the grid of described 3rd PMOS P13, make described 3rd PMOS P13 conducting, by described 3rd PMOS P13 and described 4th resistance R14, to node a charging, (described node a is described 4th resistance R14 to supply voltage on described first power lead Vdd, the drain electrode of described 3rd NMOS tube N13 and the grid tie point of described first NMOS tube N11), the current potential of described node a is constantly raised,
When threshold voltage higher than described first NMOS tube N11 of the current potential of described node a, described first NMOS tube N11 conducting, the grid potential of the grid potential of the grid potential of described first PMOS P11, described second PMOS P12 and described 4th PMOS P14 is dragged down, make described first PMOS P11, described second PMOS P12 and described 4th PMOS P14 conducting, described band gap core cell 11 and described output unit 13 start;
After described band gap core cell 11 starts, described operational amplifier OPA provides reference current by its bias current end to described current lens unit 14, described current lens unit 14 carries out mirror image to described reference current, produce the image current flowing through described 3rd NMOS tube N13, i.e. described 3rd NMOS tube N13 conducting, described node a is pulled to electronegative potential, and make described first NMOS tube N11 cut-off, described band-gap reference circuit enters normal operating conditions.
But, because described first NMOS tube N11 and described 3rd NMOS tube N13 is cut-off state before described band-gap reference circuit starts, and there is stray capacitance in the grid of described first NMOS tube N11, thus when charging to described node a, the current potential of described node a can be made to occur very large overshoot, and the voltage waveform view of described node a can with reference to shown in figure 3.
The current potential overshoot of described node a makes the conducting heighten degree of described first NMOS tube N11, and the peak current namely flowing through described first NMOS tube N11 is very large, and the waveform schematic diagram flowing through the electric current I of described first NMOS tube N11 can with reference to shown in figure 4.Due to the conducting heighten degree of described first NMOS tube N11, the grid potential of described first PMOS P11, described second PMOS P12 and described 4th PMOS P14 is drawn too low, therefore, there is very large overshoot voltage when described band-gap reference circuit starts in described reference voltage V ref.
Technical solution of the present invention provides a kind of band-gap reference circuit, effectively can reduce the overshoot of the reference voltage that described band-gap reference circuit exports when starting, and improves the stability of Circuits System.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.
The embodiment of the present invention provides a kind of band-gap reference circuit, and the circuit diagram of described band-gap reference circuit as shown in Figure 5.With reference to figure 5, described band-gap reference circuit comprises band gap core cell 51, start unit 52, output unit 53 and clamping unit 54.
Described start unit 52 comprises the first PMOS P51, the first resistance R51, Current Limiting Diodes D0, the first NMOS tube N51 and current lens unit 55.
The grid of described first PMOS P51 is suitable for input offset voltage PD, and the source electrode of described first PMOS P51 is suitable for connection first power lead Vdd, and the drain electrode of described first PMOS P51 connects one end of described first resistance R51.
Described bias voltage PD is the enabling signal of described band-gap reference circuit, and namely when the described band-gap reference circuit work of needs, the grid to described first PMOS P51 provides described bias voltage PD, makes described first PMOS P51 conducting.Described first power lead Vdd is suitable for providing supply voltage to described band-gap reference circuit.It will be understood by those skilled in the art that the supply voltage that described bias voltage PD and described first power lead Vdd provides can be preset according to conditions such as actual circuit structure, do not repeat them here.
The other end of described first resistance R51 connects the anode of described Current Limiting Diodes D0, and the negative electrode of described Current Limiting Diodes D0 connects the grid of described first NMOS tube N51 and the image current output terminal of described current lens unit 55.
Described current lens unit 55 comprises the second NMOS tube N52 and the 3rd NMOS tube N53.
The drain electrode of described second NMOS tube N52 connects the grid of described second NMOS tube N52 and the grid of described 3rd NMOS tube N53 and as the reference current input end of described current lens unit 55, the source electrode of described second NMOS tube N52 is suitable for connecting second source line Vss.
Described second source line Vss is also suitable for providing supply voltage to described band-gap reference circuit, but the supply voltage that its supply voltage provided provides lower than described first power lead Vdd.In the present embodiment, the voltage that described second source line Vss provides is ground voltage.
The drain electrode of described 3rd NMOS tube N53 is as the image current output terminal of described current lens unit 55, and the source electrode of described 3rd NMOS tube N53 is suitable for connecting described second source line Vss.
The reference current input end of described current lens unit 55 is suitable for receiving the reference current that described band gap core cell 51 provides, and the image current output terminal of described current lens unit 55 is suitable for exporting the image current with described reference current proportion relation.In the present embodiment, because described current lens unit 55 is made up of NMOS tube, therefore, described image current is the image current output terminal flowing into described current lens unit 55, also can think described current lens unit 55 image current output terminal export be a negative current.It should be noted that, the circuit structure of described current lens unit 55 is not limited to the explanation of the present embodiment, and in other embodiments, described current lens unit 55 also can be made up of PMOS or triode.
The drain electrode of described first NMOS tube N51 is suitable for providing trigger voltage to described band gap core cell 51 and described output unit 53, and the source electrode of described first NMOS tube N51 is suitable for connecting described second source line Vss.
Described band gap core cell 51 comprises the second PMOS P52, the 3rd PMOS P53, operational amplifier OPA, the 3rd resistance R53, the 4th resistance R54, the 5th resistance R55, the first PNP pipe Q51 and the second PNP pipe Q52.
The source electrode of described second PMOS P52 is suitable for connecting described first power lead Vdd, the grid of described second PMOS P52 connects the drain electrode of the grid of described 3rd PMOS P53, the output terminal of described operational amplifier OPA and described first NMOS tube N51, and the drain electrode of described second PMOS P52 connects the first input end of described operational amplifier OPA, one end of described 3rd resistance R53 and one end of described 4th resistance R54.
The drain electrode that the source electrode of described 3rd PMOS P53 is suitable for connecting described first power lead Vdd, described 3rd PMOS P53 connects second input end of described operational amplifier OPA, the emitter of described second PNP pipe Q52 and one end of described 5th resistance R55.
It should be noted that, the first input end of described operational amplifier OPA can be in-phase input end, also can be inverting input; Correspondingly, second input end of described operational amplifier OPA can be inverting input, also can be in-phase input end.
The bias current end of described operational amplifier OPA connects the reference current input end of described current lens unit 55, and the reference current that namely the reference current input end of described current lens unit 55 receives is provided by described operational amplifier OPA.
The other end of described 3rd resistance R53 connects the emitter of described first PNP pipe Q51.
The collector of the other end of described 4th resistance R54, the other end of described 5th resistance R55, the base stage of described first PNP pipe Q51, the collector of described first PNP pipe Q51, the base stage of described second PNP pipe Q52 and described second PNP pipe Q52 is all suitable for connecting described second source line Vss.
Described output unit comprises the 4th PMOS P54 and the 6th resistance R56.
The grid of described 4th PMOS P54 connects the drain electrode of described first NMOS tube N51, the drain electrode that the source electrode of described 4th PMOS P54 is suitable for connecting described first power lead Vdd, described 4th PMOS P54 connects one end of described 6th resistance R56 and is suitable for output reference voltage Vref.
The other end of described 6th resistance R56 is suitable for connecting described second source line Vss.
Described clamping unit 54 is suitable for carrying out clamper to the grid of described first NMOS tube N51.In the present embodiment, described clamping unit 54 comprise N number of connect successively diode D1, D
n, the anode of each diode connects the negative electrode of another diode, and the anode of first diode D1 connects the grid of described first NMOS tube N51, N number of diode D
nnegative electrode be suitable for connecting described second source line Vss, N>=1, namely described clamping unit 54 at least comprises a diode.
Due to described first NMOS tube N51 conducting must be ensured before described band gap core cell 51 and described output unit 53 start, therefore, the clamp voltage of described clamping unit 54 is relevant to the threshold voltage of described first NMOS tube N51.Further, described clamp voltage should higher than the threshold voltage of described first NMOS tube N51, and concrete magnitude of voltage can be arranged according to the size of described first NMOS tube N51.If the size of described first NMOS tube N51 is comparatively large, the driving force of described first NMOS tube N51 is strong, and described clamp voltage can arrange less; If the size of described first NMOS tube N51 is less, the driving force of described first NMOS tube N51 is weak, and described clamp voltage can arrange larger.
In the present embodiment, described clamping unit 54 is made up of the diode of connecting, therefore, and the product of the quantity of described clamp voltage and described series diode and the conduction voltage drop of single diode, change the quantity of described series diode, just can change the magnitude of voltage of described clamp voltage.
Below the principle of work of the band-gap reference circuit of the present embodiment is described.
Described start unit 52 is suitable under the control of described bias voltage PD, there is provided trigger voltage to described band gap core cell 51 and described output unit 53, during to ensure that described band-gap reference circuit can start (powering on) in Circuits System, enter normal operating conditions.
Particularly, after the Circuits System at described band-gap reference circuit place powers on, apply the grid of described bias voltage PD to described first PMOS P51, make described first PMOS P51 conducting, supply voltage on described first power lead Vdd is charged (described node a is the drain junction of the negative electrode of described Current Limiting Diodes D0, the grid of described first NMOS tube N51 and described 3rd NMOS tube N53) to node a by described first PMOS P51, described first resistance R51 and described Current Limiting Diodes D0, and the current potential of described node a is constantly raised.
When threshold voltage higher than described first NMOS tube N51 of the current potential of described node a, described first NMOS tube N11 conducting.Because described first NMOS tube N51 and described 3rd NMOS tube N53 is cut-off state before described band-gap reference circuit starts, and there is stray capacitance in the grid of described first NMOS tube N51, thus, after described first NMOS tube N51 conducting, the current potential of described node a also can continue to rise.When clamp voltage higher than described clamping unit 54 of the current potential of described node a, the conducting of described clamping unit 54, the current potential of described node a keeps equal with the clamp voltage of described clamping unit 54.
Because the clamp voltage of described clamping unit 54 is higher than the threshold voltage of described first NMOS tube N51, described first NMOS tube N51 keeps conducting state, the grid potential of the grid potential of described second PMOS P52, described 3rd PMOS P53 and the grid potential of described 4th PMOS P54 are dragged down, make described second PMOS P52, described 3rd PMOS P53 and described 4th PMOS P54 conducting, described band gap core cell 51 and described output unit 53 start.
After described band gap core cell 51 starts, described operational amplifier OPA provides reference current by its bias current end to described current lens unit 55.Described current lens unit 55 carries out mirror image to described reference current, produce the image current flowing through described 3rd NMOS tube N53, namely described 3rd NMOS tube N53 conducting, drags down the current potential of described node a, make described first NMOS tube N51 cut-off, described band-gap reference circuit enters normal operating conditions.
In normal operation, described band gap core cell 51 produces to be had the electric current of positive temperature coefficient (PTC) and has the electric current of negative temperature coefficient, and superposes to produce reference current with the electric current with negative temperature coefficient to the described electric current with positive temperature coefficient (PTC).The reference current that described band gap core cell produces is converted to reference voltage V ref and exports by described output unit 53.
Fig. 6 is the waveform schematic diagram of the voltage Va of the described node a of the embodiment of the present invention, and Fig. 7 is the waveform schematic diagram flowing through the electric current I of described first NMOS tube N51 of the embodiment of the present invention, and Fig. 8 is the waveform schematic diagram of the described reference voltage V ref of the embodiment of the present invention.With reference to figure 6 ~ Fig. 8, in the present embodiment, due to the clamping action of described clamping unit 54, when described band-gap reference circuit starts, the current potential of described node a is limited, there will not be large peak voltage, therefore, eliminate the peak current flowing through described first NMOS tube N51, namely the electric current I flowing through described first NMOS tube N51 is also limited, make the grid potential of described second PMOS P52, the grid potential of described 3rd PMOS P53 and the grid potential of described 4th PMOS P54 can not by excessively drop-down, therefore, the overshoot of the reference voltage V ref that described band-gap reference circuit exports when starting is very little, improve the stability of Circuits System.
When described band-gap reference circuit starts, pressure drop is there is between the anode of described Current Limiting Diodes D0 and negative electrode, therefore, described Current Limiting Diodes D0 can limit the electric current flowing through described first PMOS P51, reduces the overshoot of described reference voltage V ref when starting further.
The embodiment of the present invention also provides a kind of band-gap reference circuit, and the circuit diagram of described band-gap reference circuit as shown in Figure 9.With reference to figure 9, described band-gap reference circuit comprises band gap core cell 51, start unit 52, output unit 53 and clamping unit 54.Described band gap core cell 51, start unit 52 and output unit 53 with reference to the description to Fig. 5, can not repeat them here.
Described clamping unit 54 comprises the second resistance R52, and one end of described second resistance R52 connects the grid of described first NMOS tube N51, and the other end of described second resistance R52 is suitable for connecting described second source line Vss.In the present embodiment, the clamp voltage of described clamping unit 54 can be arranged by regulating the resistance value of described second resistance R52.
In sum, the reference voltage that the band-gap reference circuit that technical solution of the present invention provides exports overshoot when starting is very little, improves the stability of Circuits System.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (8)
1. a band-gap reference circuit, comprises band gap core cell, start unit and output unit, it is characterized in that, also comprise clamping unit;
Described start unit comprises the first PMOS, the first resistance, Current Limiting Diodes, the first NMOS tube and current lens unit, wherein, the grid of described first PMOS is suitable for input offset voltage, the source electrode of described first PMOS is suitable for connection first power lead, and the drain electrode of described first PMOS connects one end of described first resistance; The other end of described first resistance connects the anode of described Current Limiting Diodes; The negative electrode of described Current Limiting Diodes connects the grid of described first NMOS tube and the image current output terminal of described current lens unit; The drain electrode of described first NMOS tube is suitable for providing trigger voltage to described band gap core cell and described output unit, the source electrode of described first NMOS tube is suitable for connecting second source line, the supply voltage that the supply voltage that described second source line provides provides lower than described first power lead; The reference current input end of described current lens unit is suitable for receiving the reference current that described band gap core cell provides;
Described clamping unit is suitable for carrying out clamper to the grid of described first NMOS tube.
2. band-gap reference circuit as claimed in claim 1, it is characterized in that, the clamp voltage of described clamping unit is relevant to the threshold voltage of described first NMOS tube.
3. band-gap reference circuit as claimed in claim 1, it is characterized in that, described clamping unit comprises N number of diode of connecting successively, and the anode of first diode connects the grid of described first NMOS tube, the negative electrode of N number of diode is suitable for connecting second source line, N >=1.
4. band-gap reference circuit as claimed in claim 1, it is characterized in that, described clamping unit comprises the second resistance, and one end of described second resistance connects the grid of described first NMOS tube, and the other end of described second resistance is suitable for connecting described second source line.
5. band-gap reference circuit as claimed in claim 1, it is characterized in that, described current lens unit comprises the second NMOS tube and the 3rd NMOS tube;
The drain electrode of described second NMOS tube connects the grid of described second NMOS tube and the grid of described 3rd NMOS tube and as the reference current input end of described current lens unit, the source electrode of described second NMOS tube is suitable for connecting described second source line;
The drain electrode of described 3rd NMOS tube is as the image current output terminal of described current lens unit, and the source electrode of described 3rd NMOS tube is suitable for connecting described second source line.
6. band-gap reference circuit as claimed in claim 1, it is characterized in that, described band gap core cell comprises the second PMOS, the 3rd PMOS, operational amplifier, the 3rd resistance, the 4th resistance, the 5th resistance, the first PNP pipe and the second PNP pipe;
The source electrode of described second PMOS is suitable for connecting described first power lead, the grid of described second PMOS connects the drain electrode of the described grid of the 3rd PMOS, the output terminal of described operational amplifier and described first NMOS tube, and the drain electrode of described second PMOS connects the first input end of described operational amplifier, one end of described 3rd resistance and one end of described 4th resistance;
The source electrode of described 3rd PMOS is suitable for connecting described first power lead, and the drain electrode of described 3rd PMOS connects the second input end of described operational amplifier, the emitter of described second PNP pipe and one end of described 5th resistance;
The bias current end of described operational amplifier connects the reference current input end of described current lens unit;
The other end of described 3rd resistance connects the emitter of described first PNP pipe;
The collector of the other end of described 4th resistance, the other end of described 5th resistance, the base stage of described first PNP pipe, the collector of described first PNP pipe, the base stage of described second PNP pipe and described second PNP pipe is all suitable for connecting described second source line.
7. band-gap reference circuit as claimed in claim 1, it is characterized in that, described output unit comprises the 4th PMOS and the 6th resistance;
The grid of described 4th PMOS connects the drain electrode of described first NMOS tube, and the source electrode of described 4th PMOS is suitable for connecting described first power lead, and the drain electrode of described 4th PMOS connects one end of described 6th resistance and is suitable for output reference voltage;
The other end of described 6th resistance is suitable for connecting described second source line.
8. band-gap reference circuit as claimed in claim 1, it is characterized in that, the supply voltage that described second source line provides is ground voltage.
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| CN107992144A (en) * | 2018-01-25 | 2018-05-04 | 上海华虹宏力半导体制造有限公司 | The start-up circuit of band gap reference |
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| CN110199238A (en) * | 2017-01-18 | 2019-09-03 | ams有限公司 | Output circuit and for provide output electric current method |
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| CN113110678A (en) * | 2021-04-21 | 2021-07-13 | 湖南融创微电子有限公司 | High-reliability starting circuit based on low power supply voltage bandgap and control method |
| CN115268547A (en) * | 2022-08-09 | 2022-11-01 | 骏盈半导体(上海)有限公司 | Band gap reference circuit |
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| CN110199238A (en) * | 2017-01-18 | 2019-09-03 | ams有限公司 | Output circuit and for provide output electric current method |
| US10819352B2 (en) | 2017-01-18 | 2020-10-27 | Ams Ag | Output circuit and method for providing an output current |
| CN110199238B (en) * | 2017-01-18 | 2021-03-26 | ams有限公司 | Output circuit and method for providing an output current |
| CN108803773A (en) * | 2017-05-02 | 2018-11-13 | 立积电子股份有限公司 | Band gap reference circuit, voltage generator and voltage control method |
| CN108803773B (en) * | 2017-05-02 | 2020-08-07 | 立积电子股份有限公司 | Band gap reference circuit, voltage generator and voltage control method |
| CN107992144A (en) * | 2018-01-25 | 2018-05-04 | 上海华虹宏力半导体制造有限公司 | The start-up circuit of band gap reference |
| CN111293876A (en) * | 2019-12-31 | 2020-06-16 | 广州思信电子科技有限公司 | Linear circuit of charge pump |
| CN111293876B (en) * | 2019-12-31 | 2023-04-18 | 广州思信电子科技有限公司 | Linear circuit of charge pump |
| CN113110678A (en) * | 2021-04-21 | 2021-07-13 | 湖南融创微电子有限公司 | High-reliability starting circuit based on low power supply voltage bandgap and control method |
| CN115268547A (en) * | 2022-08-09 | 2022-11-01 | 骏盈半导体(上海)有限公司 | Band gap reference circuit |
| CN115268547B (en) * | 2022-08-09 | 2023-11-07 | 骏盈半导体(上海)有限公司 | Band gap reference circuit |
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