CN115662949A - Semiconductor structure and preparation method thereof - Google Patents
Semiconductor structure and preparation method thereof Download PDFInfo
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- CN115662949A CN115662949A CN202211688128.2A CN202211688128A CN115662949A CN 115662949 A CN115662949 A CN 115662949A CN 202211688128 A CN202211688128 A CN 202211688128A CN 115662949 A CN115662949 A CN 115662949A
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- 238000002360 preparation method Methods 0.000 title abstract description 8
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- 238000000034 method Methods 0.000 claims abstract description 36
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- 229920002120 photoresistant polymer Polymers 0.000 claims description 14
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- 229910003460 diamond Inorganic materials 0.000 claims 1
- 239000010432 diamond Substances 0.000 claims 1
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- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 5
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- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
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- 229910052782 aluminium Inorganic materials 0.000 description 1
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- 229910052801 chlorine Inorganic materials 0.000 description 1
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- 125000001153 fluoro group Chemical group F* 0.000 description 1
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- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
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Abstract
The invention provides a semiconductor structure and a preparation method thereof, wherein the semiconductor structure comprises: the conductive column comprises a first metal layer, an insulating layer, a conductive column and a second metal layer, wherein the insulating layer is arranged between the first metal layer and the second metal layer; the conductive column penetrates through the insulating layer, and two ends of the conductive column are respectively embedded into the first metal layer and the second metal layer. According to the invention, the conductive column between the metal layers in the back-end process extends into the metal layers at the two ends, so that the contact area between the conductive column and the metal layer is increased, the contact resistance is reduced, the probability of short circuit of a device caused by poor contact between the conductive column and the metal layer is reduced, and the performance reliability of the device is improved; meanwhile, the thickness of the conductive column extending into the metal layer is set, so that the contact area between the conductive column and the metal layer is maximized, and the conductive column between the metal layers is prevented from short circuit; in addition, the cross-sectional shape of the conductive column further increases the contact area between the conductive column and the metal layer.
Description
Technical Field
The invention belongs to the technical field of semiconductor integrated circuit manufacturing, and particularly relates to a semiconductor structure and a preparation method thereof.
Background
In chip design, multiple layers of metal wires are usually designed, and the connections between each layer of metal are connected by conductive pillars (commonly referred to as contacts or VIA). In an N-layer metal design, there are N layers of conductive pillars. In particular, in some designs, there is only one conductive post for the metal-to-metal connection, so that the probability of open circuit failure is high.
Ideally, the resistance between the metal and the conductive pillar is zero, but in an actual process, the metal is affected by the process conditions and the size of the wafer area during deposition, and shows different properties in different regions, and the resistance between the metal and the conductive pillar also changes greatly. For example, in the process of converting the arrangement of the metal TiN (titanium nitride) -Al (aluminum) -TiN (titanium nitride) with a sandwich structure from the lower pre-plating layer TiN to the deposition of Al, if the waiting time in the conversion process is too long, the flatness of the lower pre-plating layer may be poor, so that the metal layer and the conductive pillar are in poor contact, the contact resistance is increased, or even an open circuit is formed, and the circuit function is affected.
At present, the conventional solution is to control the deposition time and process conditions of the metal layer, but because the control effect is not ideal, a new solution is urgently needed to solve the problem of the excessive contact resistance.
It should be noted that the above description of the technical background is only for the sake of clarity and complete description of the technical solutions of the present application and for the understanding of the skilled person, and the technical solutions are not considered to be known to the skilled person merely because they are described in the background section of the present application.
Disclosure of Invention
In view of the above drawbacks of the prior art, an object of the present invention is to provide a semiconductor structure and a method for manufacturing the same, which are used to solve the problem of excessive contact resistance between a conductive pillar and a metal layer between metal layers in the prior art.
In order to achieve the above object, the present invention provides a method for manufacturing a semiconductor structure, the method comprising:
arranging a first metal layer;
arranging an insulating layer on the first metal layer;
a contact hole is arranged in the insulating layer, penetrates through the insulating layer and extends to a depth in the first metal layer;
arranging a conductive column in the contact hole, wherein the conductive column fills the contact hole and covers the surface of the insulating layer;
removing the conductive column on the surface of the insulating layer until the top surface of the conductive column is flush with the surface of the insulating layer;
removing part of the thickness of the insulating layer to enable the conductive column to protrude out of the surface of the insulating layer by a certain height;
and arranging a second metal layer on the insulating layer and the conductive columns, so that the tops of the conductive columns are embedded into the second metal layer.
Optionally, the method for providing the contact hole includes: covering photoresist on the insulating layer, carrying out graphical exposure to preset the position of the contact hole, developing the photoresist, exposing the insulating layer after etching and developing, further etching the first metal layer to a certain depth to form the contact hole, and then removing the photoresist.
Optionally, the method for removing part of the thickness of the insulating layer includes: selectively etching by using a preset etching agent to remove part of the thickness of the insulating layer, wherein the preset etching agent has a high etching selection ratio on the insulating layer and the conductive column; or an anti-etching layer is arranged on the conductive post, the anti-etching layer is exposed through exposure and development, and the anti-etching layer is removed through an etching process by removing part of the thickness of the insulating layer.
Optionally, after the first metal layer is disposed, a first plating layer is disposed on the first metal layer, and the insulating layer is disposed on the first plating layer; before the second metal layer is arranged, a second plating layer is arranged on the exposed surfaces of the insulating layer and the conductive posts, and the second metal layer is arranged on the second plating layer.
Optionally, the method for removing the insulating layer is one or a combination of more than one of plasma etching, reactive ion etching, sputter etching, ion beam etching and reactive ion beam etching.
Optionally, the thickness of the conductive pillar embedded in the first metal layer is less than half of the thickness of the first metal layer, and/or the thickness of the second metal layer embedded in the conductive pillar is less than half of the thickness of the second metal layer.
The invention also provides a semiconductor structure, which is obtained by any one of the preparation methods, and the semiconductor structure comprises: the first metal layer, the insulating layer, the conductive column and the second metal layer; the insulating layer is arranged between the first metal layer and the second metal layer; the conductive column penetrates through the insulating layer, and two ends of the conductive column are embedded into the first metal layer and the second metal layer respectively.
Optionally, a first plating layer is disposed between the first metal layer and the insulating layer, and the first plating layer covers the surface of the first metal layer and the surface of the first metal layer to which the conductive pillar extends; a second plating layer is arranged between the second metal layer and the insulating layer, and the second plating layer covers the surface of the insulating layer and the surface of the second metal layer to which the conductive posts extend.
Optionally, a cross-sectional shape of the conductive pillar along a direction parallel to the first metal layer is one of a triangle, a rectangle, a rhombus, a pentagon, a hexagon, a circle, or an ellipse.
Optionally, the thickness of the conductive pillar embedded in the first metal layer is less than half of the thickness of the first metal layer, and/or the thickness of the second metal layer embedded in the conductive pillar is less than half of the thickness of the second metal layer.
As described above, the semiconductor structure and the manufacturing method thereof of the present invention have the following beneficial effects:
according to the invention, the conductive column between the metal layers in the back-end process extends into the metal layers at the two ends, so that the contact area between the conductive column and the metal layer is increased, the contact resistance is reduced, the probability of short circuit of a device caused by poor contact between the conductive column and the metal layer is reduced, and the performance reliability of the device is improved;
the thickness of the conductive column extending into the metal layer is set, so that the contact area between the conductive column and the metal layer is maximized, and the conductive column between the metal layers is prevented from short circuit;
the cross section shape of the conductive column is set, so that the contact area between the conductive column and the metal layer is further increased.
Drawings
Fig. 1 is a schematic cross-sectional view illustrating a metal layer and a conductive pillar in contact with each other in the prior art.
Fig. 2 is a schematic top view illustrating a contact manner between a metal layer and a conductive pillar in the prior art.
Fig. 3 is a schematic structural diagram illustrating a first metal layer disposed in an optional step 1 according to an embodiment of the present invention.
Fig. 4 is a schematic structural diagram of an insulating layer disposed in step 2 according to an embodiment of the invention.
Fig. 5 is a schematic structural diagram of the step 3 of covering the photoresist according to an alternative embodiment of the present invention.
Fig. 6 is a schematic diagram illustrating a structure of developing the photoresist in an optional step 3 according to an embodiment of the present invention.
Fig. 7 is a schematic structural diagram showing a first metal layer etched in an optional step 3 according to an embodiment of the present invention.
Fig. 8 is a schematic structural diagram illustrating the removal of the photoresist in an optional step 3 according to an embodiment of the present invention.
Fig. 9 is a schematic structural diagram illustrating the arrangement of the conductive pillars in step 4 according to the embodiment of the present invention.
Fig. 10 is a schematic structural diagram illustrating the removal of the conductive pillars on the surface of the insulating layer in step 5 according to the embodiment of the present invention.
Fig. 11 is a schematic structural diagram illustrating a structure of removing a portion of the thickness of the insulating layer in step 6 according to the embodiment of the invention.
FIG. 12 is a schematic diagram of a structure for providing an anti-etching layer and a reticle in an optional step 6 according to an embodiment of the invention.
FIG. 13 is a schematic diagram illustrating a structure of the exposed and developed resist layer in step 6 according to an alternative embodiment of the present invention.
Fig. 14 is a schematic structural diagram illustrating a structure of removing a portion of the insulating layer in an optional step 6 according to an embodiment of the invention.
FIG. 15 is a schematic diagram illustrating an alternative structure for removing the anti-etching layer in step 6 according to an embodiment of the present invention.
Fig. 16 is a schematic structural diagram illustrating the second metal layer disposed in step 7 according to the embodiment of the present invention.
Fig. 17 is a schematic cross-sectional view of a semiconductor structure according to a second embodiment of the invention.
Fig. 18 is a schematic top view of a semiconductor structure according to a second embodiment of the invention.
Description of the element reference
1. A first metal layer; 2. an insulating layer; 3. photoresist; 4. masking the plate; 5. a contact hole; 6. a conductive post; 7. a second metal layer; 8. an etch resistant layer; 9. a first plating layer; 10. a second plating layer; H. the conductive column is extended and embedded into the thicknesses of the first metal layer and the second metal layer; l1, conducting column width; l2, conducting column length; l, the thickness of the first metal and the second metal.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
As used herein, the drawings are not intended to be limiting, but are to be construed in an illustrative and exemplary manner. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures.
In the context of this application, a structure described as a first feature being "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.
It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
In the prior art, as shown in fig. 1-2, two ends of a conductive pillar 6 between metal layers are only in surface contact with the metal layers, the height of the conductive pillar 6 is the same as the thickness of an insulating layer 2 between the metal layers, L1 is the width of the conductive pillar, L2 is the length of the conductive pillar, and the contact area between the conductive pillar and the metal layers
The contact area is too small, the contact area is inversely proportional to the contact resistance, the contact resistance is large, and when the contact surface is not smooth enough, the conductive connection between the conductive column and the metal layer is easy to open, so that the semiconductor structure is poor and cannot normally work.
Example one
In order to solve the above problems, as shown in fig. 3 to 16, the present invention provides a method for manufacturing a semiconductor structure, the method comprising:
step 1: arranging a first metal layer 1;
step 2: an insulating layer 2 is arranged on the first metal layer 1;
and step 3: a contact hole 5 is arranged in the insulating layer 2, and the contact hole 5 penetrates through the insulating layer 2 and extends to a depth in the first metal layer 1;
and 4, step 4: arranging a conductive column 6 in the contact hole 5, wherein the conductive column 6 fills the contact hole 5 and covers the surface of the insulating layer 2;
and 5: removing the conductive column 6 on the surface of the insulating layer 2 until the top surface of the conductive column 6 is flush with the surface of the insulating layer 2;
step 6: removing part of the thickness of the insulating layer 2 to enable the conductive column 6 to protrude out of the surface of the insulating layer 2 by a certain height;
and 7: and arranging a second metal layer 7 on the insulating layer 2 and the conductive pillars 6, so that the tops of the conductive pillars 6 are embedded in the second metal layer 7.
The method for fabricating a semiconductor structure according to the present invention will be described in detail with reference to the accompanying drawings, wherein it should be noted that the above sequence does not strictly represent the sequence of the method for fabricating a semiconductor structure according to the present invention, and can be changed by those skilled in the art according to the actual fabrication steps.
First, step 1 is performed to provide a first metal layer 1.
As an example, as shown in fig. 3, after the first metal layer 1 is disposed, a first plating layer 9 is disposed on the first metal layer 1, and the insulating layer 2 is disposed on the first plating layer 9.
Then, as shown in fig. 4, step 2 is performed to dispose an insulating layer 2 on the first metal layer 1.
Next, as shown in fig. 5-8, step 3 is performed to form a contact hole 5 in the insulating layer 2, wherein the contact hole 5 penetrates through the insulating layer 2 and extends to a depth in the first metal layer 1.
As an example, the method of providing the contact hole 5 includes: as shown in fig. 5, a photoresist 3 is covered on the insulating layer 2, and the position of the contact hole 5 is preset through patterned exposure of a mask 4; as shown in fig. 6, the photoresist 3 is developed; as shown in fig. 7, the insulating layer 2 is exposed after etching and developing, and the first metal layer 1 is further etched to a certain depth to form the contact hole 5; the photoresist 3 is then removed as shown in fig. 8.
In one embodiment, the insulating layer 2 is etched using a fluorine-containing gas.
In one embodiment, the first metal layer 1 is etched using a chlorine-containing gas.
Specifically, the insulating layer 2 and the first metal layer 1 are etched by dry etching.
In one embodiment, the first metal layer 1 is etched to an etching depth less than half the thickness of the first metal layer 1.
The thickness H of the conductive column 6 extending and embedding in the first metal layer 1 is set to be less than half of the thickness L of the first metal layer 1, so that the contact area of the conductive column 6 in the first metal layer 1 can be sufficiently large to ensure that the contact resistance is sufficiently small and poor contact is avoided, and meanwhile, the conductive column 6 is prevented from being too large in contact area in the first metal layer 1 to be short-circuited with the conductive column 6 on the other side of the first metal layer 1, the reliability of the semiconductor structure is further improved by the setting of the extending and embedding thickness of the conductive column 6, and the poor probability of electrical connection of the semiconductor structure is reduced.
Then, as shown in fig. 9, step 4 is performed to dispose conductive pillars 6 in the contact holes 5, where the conductive pillars 6 fill the contact holes 5 and cover the surface of the insulating layer 2.
Next, as shown in fig. 10, step 5 is performed to remove the conductive pillars 6 on the surface of the insulating layer 2 until the top surfaces of the conductive pillars 6 are flush with the surface of the insulating layer 2.
In one embodiment, the conductive pillars 6 on the surface of the insulating layer 2 are removed by CMP (chemical mechanical polishing) until the top surfaces of the conductive pillars 6 are flush with the surface of the insulating layer 2.
Then, as shown in fig. 11, step 6 is performed to remove a portion of the thickness of the insulating layer 2, so that the conductive pillar 6 protrudes a height above the surface of the insulating layer 2.
In one embodiment, the insulating layer 2 is etched to make the height of the conductive pillar 6 protruding from the insulating layer 2 less than half of the thickness of the second metal layer 7 in the subsequent steps.
According to the invention, the thickness H of the conductive column 6 extending and embedded in the second metal layer 7 is set to be less than half of the thickness L of the second metal layer 7, so that the contact area of the conductive column 6 in the second metal layer 7 can be large enough to ensure that the contact resistance is small enough and poor contact can not occur, and meanwhile, the conductive column 6 is prevented from being too large in contact area in the second metal layer 7 to be short-circuited with the conductive column 6 on the other side of the second metal layer 7, the reliability of the semiconductor structure is further improved by setting the extending and embedding thickness of the conductive column 6, and the poor probability of electrical connection of the semiconductor structure is reduced.
As an example, as shown in fig. 11, the preparation method for removing a partial thickness of the insulating layer 2 includes: and selectively etching by using a preset etching agent to remove part of the thickness of the insulating layer 2, wherein the preset etching agent has a high etching selectivity ratio on the insulating layer 2 and the conductive column 6.
In one embodiment, the predetermined etchant is a fluorine-containing gas, and fluorine reacts only with the material of the insulating layer 2 and hardly reacts with the material of the conductive pillar 6, so that the insulating layer 2 can be selectively etched.
In another example, the preparation method for removing a partial thickness of the insulating layer 2 includes: as shown in fig. 12, an anti-etching layer 8 and a mask 4 are disposed on the conductive pillar 6; as shown in fig. 13, the insulating layer 2 is exposed from the anti-etching layer 8 after exposure and development through the mask 4; as shown in fig. 14, a part of the thickness of the insulating layer 2 is removed by an etching process; as shown in fig. 15, the etch resist layer 8 is removed.
Specifically, the etch resist layer 8 is a negative photoresist 3 to remain during development to protect the portion of the insulating layer 2 covered thereby from removal.
The extending part of the conductive column 6 is obtained by using a selective etching mode, so that the cost is low, but the conductive column 6 material is easily damaged to a certain degree, and the maintenance of the preset shape of the conductive column 6 material is influenced; the extending portion of the conductive post 6 is obtained by performing photolithography on the anti-etching layer 8, so that the preset shape of the conductive post 6 material can be maintained, but the cost is high and the alignment accuracy is poor. The skilled person can select a suitable etching manner to remove a part of the thickness of the insulating layer 2 according to specific product performance requirements.
As an example, the method for removing the insulating layer 2 is one or a combination of more than one of plasma etching, reactive ion etching, sputter etching, ion beam etching and reactive ion beam etching.
Finally, as shown in fig. 16, step 7 is performed to dispose a second metal layer 7 on the insulating layer 2 and the conductive pillars 6, so that the tops of the conductive pillars 6 are embedded in the second metal layer 7.
Since the contact hole 5 between the metal layers plays a very important role in circuit connection in the back-end process, the function of the semiconductor device is seriously affected due to the open circuit or poor contact of the contact hole 5, while the reliability is poor because the contact hole 5 and the metal layers are electrically connected only through the laminated surface contact surface in the conventional process, and poor contact or even open circuit between the contact hole 5 and the metal layers is easily generated when the contact surface is not flat enough. According to the invention, the conductive column 6 between the metal layers in the back-end process is extended and embedded into the first metal layer 1 and the second metal layer 7, so that the contact area between the conductive column 6 in the contact hole 5 and the first metal layer 1 and the second metal layer 7 is increased, the contact resistance is reduced, the probability of short circuit of the device caused by poor contact between the conductive column 6 and the first metal layer 1 and the second metal layer 7 is reduced, meanwhile, the connection between the conductive column 6 and the first metal layer 1 and the second metal layer 7 is more firm, the abnormality such as translocation is not easy to generate, and the performance reliability of the device is improved.
For example, as shown in fig. 9, before the second metal layer 7 is disposed, a second plating layer 10 is disposed on the exposed surfaces of the insulating layer 2 and the conductive post 6, and the second metal layer 7 is disposed on the second plating layer 10.
Specifically, the first plating layer 9 and the second plating layer 10 are prepared by a multi-arc and sputtering deposition method.
Example two
As shown in fig. 17 to 18, the present invention provides a semiconductor structure obtained by any one of the preparation methods of the first embodiment, the semiconductor structure comprising: the structure comprises a first metal layer 1, an insulating layer 2, a conductive column 6 and a second metal layer 7; the insulating layer 2 is arranged between the first metal layer 1 and the second metal layer 7; the conductive column 6 penetrates through the insulating layer 2, and two ends of the conductive column 6 are embedded in the first metal layer 1 and the second metal layer 7 respectively.
As shown in fig. 17-18, H sets the thickness of the conductive pillar 6 embedded in the first metal layer 1 and the second metal layer 7, where L1 is the width of the conductive pillar 6, and L2 is the length of the conductive pillar 6; in the cross-sectional view of fig. 17, the conductive pillars 6 extend in the up-down direction and are embedded into the first metal layer 1 and the second metal layer 7, while the top view of fig. 18 is the same as the top view of fig. 2 in the prior art, and is not changed. In the present invention, the conductive pillar 6 is extended and embedded into the first metal layer 1 and the second metal layer 7, so that the contact area between the conductive pillar 6 and the first metal layer 1 and the second metal layer 7 is increased
So that the contact area is greatly increased. Since the contact resistance is inversely proportional to the contact area, the contact resistance is reduced, the reliability of the conductive connection between the conductive column 6 and the first metal layer 1 and the second metal layer 7 is improved, and the open circuit caused by poor contact of the contact surface is reduced.
As an example, a first plating layer 9 is disposed between the first metal layer 1 and the insulating layer 2, and the first plating layer 9 covers the surface of the first metal layer 1 and the conductive post 6 extends to the surface of the first metal layer 1; a second plating layer 10 is disposed between the second metal layer 7 and the insulating layer 2, and the second plating layer 10 covers the surface of the insulating layer 2 and the surface of the second metal layer 7 to which the conductive post 6 extends.
According to the invention, the first plating layer 9 and the second plating layer 10 are arranged between the first metal layer 1, the second metal layer 7 and the insulating layer 2, so that the adhesion between the metal layers and the insulating layer 2 is improved, the stability of the metal layers on the insulating layer 2 is ensured, and the phenomena of falling off, separation and the like are prevented.
In one embodiment, the material of the first plating layer 9 and the second plating layer 10 is titanium, and the connection reliability between the first metal layer 1, the second metal layer 7 and the insulating layer 2 is further improved by utilizing the higher metal conductivity, adhesion and better thickness uniformity of titanium.
In one embodiment, the material of the first plating layer 9 and the second plating layer 10 may also be titanium nitride.
As an example, the cross-sectional shape of the conductive pillar 6 along a direction parallel to the first metal layer 1 is one of a triangle, a rectangle, a rhombus, a pentagon, a hexagon, a circle, or an ellipse.
In one embodiment, the cross-sectional shape of the conductive pillar 6 parallel to the first metal layer 1 is a triangle, and the portion of the conductive pillar 6 embedded in the first metal layer 1 and the second metal layer 7 is a triangular pyramid.
According to the invention, the cross-sectional area of the conductive column 6 is set, so that the expansion degree of the contact area can be adjusted according to specific requirements, and when the parts of the conductive column 6, which are embedded into the first metal layer 1 and the second metal layer 7, are triangular pyramids, the maximum contact area can be realized under the same volume, so that the material of the conductive column 6 is saved, and the maximization of the contact area is realized at the same time.
In an embodiment, when the cross-sectional shape of the conductive pillar 6 along the direction parallel to the first metal layer 1 is a concave polygonal cross-sectional shape, the contact area between the conductive pillar 6 and the first metal layer 1 and the second metal layer 7 can be further increased without increasing the thickness of the conductive pillar 6 embedded in the first metal layer 1 and the second metal layer 7, so as to reduce the contact resistance, but care should be taken to reduce the existence of the corner so as to avoid the local over-temperature caused by the charge accumulation effect from short-circuiting the contact hole 5.
In one embodiment, the material of the insulating layer 2 is silicon dioxide.
In one embodiment, the material of the conductive pillar 6 is tungsten.
In one embodiment, the first metal layer 1 and/or the second metal layer 7 material may be aluminum, copper, gold, silver, or other suitable conductive material.
As an example, the thickness of the conductive pillar 6 embedded in the first metal layer 1 is less than half of the thickness of the first metal layer 1, and/or the thickness of the second metal layer 7 embedded in the conductive pillar 6 is less than half of the thickness of the second metal layer 7.
According to the invention, the thickness H of the conductive column 6 which is extended and embedded in the first metal layer 1 and the second metal layer 7 is set to be less than half of the thickness L of the first metal layer 1 and the second metal layer 7, so that the contact area of the conductive column 6 in the first metal layer 1 and the second metal layer 7 can be large enough to ensure that the contact resistance is small enough and poor contact can not occur, and meanwhile, the conductive column 6 is prevented from being short-circuited with the conductive column 6 on the other side of the first metal layer 1 and the second metal layer 7 due to the overlarge contact area in the first metal layer 1 and the second metal layer 7, and the extension and embedding thickness of the conductive column 6 further improves the reliability of a semiconductor structure and reduces the poor probability of electrical connection of the semiconductor structure.
In summary, according to the semiconductor structure and the manufacturing method thereof, the conductive column between the metal layers in the back-end process extends into the metal layers at the two ends, so that the contact area between the conductive column and the metal layers is increased, the contact resistance is reduced, the probability of short circuit of the device caused by poor contact between the conductive column and the metal layers is reduced, and the performance reliability of the device is improved; meanwhile, the thickness of the conductive column extending into the metal layer is set, so that the contact area between the conductive column and the metal layer is maximized, and the conductive column between the metal layers is prevented from short circuit; in addition, the cross section shape of the conductive column is arranged, so that the contact area between the conductive column and the metal layer is further increased.
Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which may be made by those skilled in the art without departing from the spirit and scope of the present invention as defined in the appended claims.
Claims (10)
1. A method for fabricating a semiconductor structure, the method comprising:
arranging a first metal layer;
arranging an insulating layer on the first metal layer;
arranging a contact hole in the insulating layer, wherein the contact hole penetrates through the insulating layer and extends to a depth in the first metal layer;
arranging a conductive column in the contact hole, wherein the conductive column fills the contact hole and covers the surface of the insulating layer;
removing the conductive column on the surface of the insulating layer until the top surface of the conductive column is flush with the surface of the insulating layer;
removing part of the thickness of the insulating layer to enable the conductive column to protrude out of the surface of the insulating layer by a certain height;
and arranging a second metal layer on the insulating layer and the conductive columns to enable the tops of the conductive columns to be embedded into the second metal layer.
2. The method for manufacturing a semiconductor structure according to claim 1, wherein the method for providing the contact hole comprises: covering photoresist on the insulating layer, carrying out graphical exposure to preset the position of the contact hole, developing the photoresist, exposing the insulating layer after etching and developing, further etching the first metal layer to a certain depth to form the contact hole, and then removing the photoresist.
3. The method of claim 1, wherein removing a portion of the thickness of the insulating layer comprises: selectively etching by using a preset etching agent to remove part of the thickness of the insulating layer, wherein the preset etching agent has a high etching selection ratio on the insulating layer and the conductive column; or an anti-etching layer is arranged on the conductive column, the anti-etching layer is exposed through exposure and development, the insulating layer is exposed, and the anti-etching layer is removed through the etching process to remove part of the thickness of the insulating layer.
4. The method of claim 1, wherein after the first metal layer is deposited, a first plating layer is deposited on the first metal layer and the insulating layer is deposited on the first plating layer; before the second metal layer is arranged, a second plating layer is arranged on the exposed surfaces of the insulating layer and the conductive posts, and the second metal layer is arranged on the second plating layer.
5. The method for manufacturing a semiconductor structure according to claim 1, wherein the method for removing the insulating layer is one or a combination of more than one of plasma etching, reactive ion etching, sputter etching, ion beam etching and reactive ion beam etching.
6. The method as claimed in claim 1, wherein the conductive pillar is embedded in the first metal layer to a thickness less than half of the thickness of the first metal layer, and/or the second metal layer is embedded in the conductive pillar to a degree less than half of the thickness of the second metal layer.
7. A semiconductor structure obtained by the method according to any one of claims 1 to 6, comprising: the first metal layer, the insulating layer, the conductive column and the second metal layer;
the insulating layer is arranged between the first metal layer and the second metal layer;
the conductive column penetrates through the insulating layer, and two ends of the conductive column are embedded into the first metal layer and the second metal layer respectively.
8. The semiconductor structure of claim 7, wherein a first plating layer is disposed between the first metal layer and the insulating layer, the first plating layer covering a surface of the first metal layer and the conductive pillar extending to the surface of the first metal layer; a second plating layer is arranged between the second metal layer and the insulating layer, and the second plating layer covers the surface of the insulating layer and the surface of the second metal layer to which the conductive posts extend.
9. The semiconductor structure of claim 7, wherein a cross-sectional shape of the conductive pillar along a direction parallel to the first metal layer is one of triangular, rectangular, diamond, pentagonal, hexagonal, circular, or elliptical.
10. The semiconductor structure of claim 7, wherein the conductive pillar is embedded in the first metal layer to a thickness less than half of a thickness of the first metal layer, and/or the second metal layer is embedded in the conductive pillar to a thickness less than half of a thickness of the second metal layer.
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0730094A (en) * | 1993-07-13 | 1995-01-31 | Citizen Watch Co Ltd | Semiconductor device and manufacture thereof |
| JPH11135629A (en) * | 1997-10-22 | 1999-05-21 | Lg Semicon Co Ltd | Wiring structure of semiconductor device and its forming method |
| US20020185740A1 (en) * | 2001-06-07 | 2002-12-12 | Samsung Electronics Co., Ltd. | Semiconductor device having multilevel interconnections and method of manufacturing the same |
| CN108389797A (en) * | 2018-02-28 | 2018-08-10 | 佛山市宝粤美科技有限公司 | A kind of preparation method of metal interconnection structure |
| CN110211923A (en) * | 2019-06-10 | 2019-09-06 | 武汉新芯集成电路制造有限公司 | Metal interconnection structure and preparation method thereof |
| CN114334959A (en) * | 2020-11-25 | 2022-04-12 | 台湾积体电路制造股份有限公司 | Semiconductor structure |
-
2022
- 2022-12-28 CN CN202211688128.2A patent/CN115662949A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0730094A (en) * | 1993-07-13 | 1995-01-31 | Citizen Watch Co Ltd | Semiconductor device and manufacture thereof |
| JPH11135629A (en) * | 1997-10-22 | 1999-05-21 | Lg Semicon Co Ltd | Wiring structure of semiconductor device and its forming method |
| US20020185740A1 (en) * | 2001-06-07 | 2002-12-12 | Samsung Electronics Co., Ltd. | Semiconductor device having multilevel interconnections and method of manufacturing the same |
| CN108389797A (en) * | 2018-02-28 | 2018-08-10 | 佛山市宝粤美科技有限公司 | A kind of preparation method of metal interconnection structure |
| CN110211923A (en) * | 2019-06-10 | 2019-09-06 | 武汉新芯集成电路制造有限公司 | Metal interconnection structure and preparation method thereof |
| CN114334959A (en) * | 2020-11-25 | 2022-04-12 | 台湾积体电路制造股份有限公司 | Semiconductor structure |
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