CN115662911A - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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Publication number
CN115662911A
CN115662911A CN202211428741.0A CN202211428741A CN115662911A CN 115662911 A CN115662911 A CN 115662911A CN 202211428741 A CN202211428741 A CN 202211428741A CN 115662911 A CN115662911 A CN 115662911A
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Prior art keywords
semiconductor device
contact pads
integrated circuit
interconnect
immersion
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CN202211428741.0A
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Inventor
邵栋梁
萧义理
陈筱芸
董志航
余振华
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Publication of CN115662911A publication Critical patent/CN115662911A/zh
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Abstract

公开了半导体器件及其制造方法。在一些实施例中，一种制造器件的方法包括通过间隔件将第一半导体器件连接至第二半导体器件。第一半导体器件具有在第一半导体器件上设置的第一接触焊盘并且第二半导体器件具有在第二半导体器件上设置的第二接触焊盘。该方法包括在第一半导体器件的第一接触焊盘和第二半导体器件的第二接触焊盘之间形成浸没互连件。本发明实施例涉及半导体器件及其制造方法。

Description

半导体器件及其制造方法
本申请是于2017年06月26日提交的申请号为201710494979.6的名称为“半导体器件及其制造方法”的发明专利申请的分案申请。
技术领域
本发明实施例涉及半导体器件及其制造方法。
背景技术
半导体器件在各种电子应用中使用，如个人电脑、手机、数码相机和其他电子设备。半导体工业通过不断减小最小化部件尺寸来继续提高各种电子组件(如，晶体管、二极管、电阻器、电容器等)的集成密度，这允许更多的组件集成到给定的面积中。由于近来对小型化、更高的速度和更大的带宽以及较低的功耗和延迟的需求不断增长，因此亟需用于半导体管芯的更小和更具创造性的封装技术。
随着半导体技术的进一步发展，已经出现了堆叠半导体器件(例如，三维集成电路(3DIC)器件)，以作为进一步减小半导体器件的物理尺寸的有效可选方式。在堆叠式半导体器件中，在不同半导体晶圆上制造诸如逻辑电路、存储电路、处理器电路等的有源电路。两个或更多的半导体晶圆可以安装或堆叠在彼此的顶部上以进一步降低半导体器件的形状因数。
可以通过合适的接合技术将两个半导体晶圆和/或管芯接合在一起。通常使用的接合技术包括直接接合、化学激活接合、等离子体激活接合、阳极接合、共熔接合、玻璃浆料接合、粘合接合、热压接合、反应接合等。可以在堆叠半导体晶圆之间设置电连接。堆叠式半导体器件可以提供具有更小的形成因数的更高的密度并且允许增加的性能和更低的功耗。
发明内容
根据本发明的一个实施例，提供了一种制造器件的方法，所述方法包括：通过多个间隔件将第一半导体器件连接至第二半导体器件，所述第一半导体器件具有设置在所述第一半导体器件上的多个第一接触焊盘，所述第二半导体器件具有设置在所述第二半导体器件上的多个第二接触焊盘；以及在所述第一半导体器件的所述多个第一接触焊盘的每个和所述第二半导体器件的所述多个第二接触焊盘的一个之间形成浸没互连件。
根据本发明的另一实施例，还提供了一种制造器件的方法，所述方法包括：通过多个间隔件将第一半导体器件连接至第二半导体器件,所述第一半导体器件具有设置在所述第一半导体器件上的多个第一接触焊盘,所述第二半导体器件具有设置在所述第二半导体器件上的多个第二接触焊盘，所述多个间隔件与所述第一接触焊盘和所述第二接触焊盘间隔开；以及使用化学镀工艺以在所述第一半导体器件的所述多个第一接触焊盘的每个和所述第二半导体器件的所述多个第二接触焊盘的一个之间形成浸没互连件。
根据本发明的又一实施例，还提供了一种半导体器件，包括：第一集成电路管芯，具有设置在所述第一集成电路管芯上的多个第一接触焊盘；第二集成电路管芯，连接至所述第一集成电路管芯，具有设置在所述第二集成电路管芯上的多个第二接触焊盘；多个间隔件，连接至所述第一集成电路管芯和所述第二集成电路管芯并且设置在所述第一集成电路管芯和所述第二集成电路管芯之间、接近所述多个第一接触焊盘和所述多个第二接触焊盘，所述多个间隔件与所述第一接触焊盘和所述第二接触焊盘间隔开；以及浸没互连件，设置在所述多个第一接触焊盘的每个和所述多个第二接触焊盘的一个之间。
附图说明
当结合附图进行阅读时，根据下面详细的描述可以更好地理解本发明的实施例。应该强调的是，根据工业中的标准实践，对各种部件没有按比例绘制并且仅仅用于说明的目的。实际上，为了清楚的讨论，各种部件的尺寸可以被任意增大或缩小。
图1是根据本发明的一些实施例示出通过多个间隔件连接在一起的两个半导体器件的截面图。
图2和图3是根据一些实施例示出在图1中示出的两个半导体器件的接触焊盘之间形成浸没互连件的方法的截面图。
图4至图6是根据一些实施例的图1至图3中示出的半导体器件的部分的顶视图和仰视图，示出多个间隔件的一些示例性形状和放置。
图7A至图7D是根据一些实施例示出在各个阶段的浸没工艺的截面图，其中，在两个半导体器件的接触焊盘之间制作浸没互连件。
图8A至图8D示出了根据一些实施例的在各个阶段的浸没工艺的截面图，其中，在第一半导体器件的导电柱和第二半导体器件的导电焊盘之间制作浸没互连件。
图9A至图9D示出了根据一些实施例的在各个阶段的浸没工艺的截面图，其中，在第一半导体器件的导电柱和第二半导体器件的导电柱之间制作浸没互连件。
图10是根据一些实施例的化学镀套件的顶视图，示出了形成用于多个半导体器件的浸没互连件的方法。
图11和图12是根据一些实施例的示出了化学镀工艺中的溶剂的流动的图10中示出的化学镀套件的部分的截面图。
图13是根据一些实施例示出形成用于多个半导体器件的浸没互连件的方法的化学镀套件的顶视图。
图14和图15是根据一些实施例示出化学镀工艺中的溶剂的流动的图13中示出的化学镀套件的部分的截面图。
图16至图19是根据一些实施例示出包括浸没互连件的封装的半导体器件的截面图。
图20是根据本发明的一些实施例示出用于半导体器件的制造方法的流程图。
具体实施方式
以下公开内容提供了许多用于实现所提供主题的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，在以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件形成为直接接触的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实例中重复参考标号和/或字母。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为便于描述，在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等的空间相对术语，以便于描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上)，而在此使用的空间相对描述符可以同样地作相应的解释。
本公开中公开了半导体器件的制造方法及其结构。在一些实施例中，诸如集成电路管芯的半导体器件和/或半导体晶圆连接在一起，形成3DIC。在两个半导体器件之间形成间隔件，并且在两个半导体器件的接触焊盘和/或导电柱之间形成浸没互连件。例如，浸没互连件形成工艺提供了用于在集成电路管芯和/或晶圆之间形成连接的简化方法和结构，可以在低温和低机械应力级下执行，提供循环时间和节省成本，并且增强共面性和对准的工艺窗。贯穿各个视图和示出的实施例，相同的参考标号用于指定相同的元件。
图1是根据本发明的一些实施例示出第一半导体器件102a通过多个间隔件104连接至第二半导体器件102b的截面图。图2和图3分别地示出在根据一些实施例的图1中示出的第一半导体器件102a和第二半导体器件102b的接触焊盘106a和106b之间形成的浸没互连件120的截面图。
首先参照图1，提供第一半导体器件102a。在一些实施例中，第一半导体器件102a包括集成电路管芯或包括具有多个集成电路管芯的半导体晶圆。还可以提供多个第一半导体器件102a，多个第一半导体器件102a包括已经从晶圆形态分割的集成电路管芯。
在一些实施例中，第一半导体器件102a可以包括衬底。衬底可以包括硅晶圆、硅碳衬底、硅锗衬底、由其它半导体材料形成的衬底、块状衬底、晶圆上硅(SOI)衬底或其它支撑衬底(即，如本领域已知的石英、玻璃等)或它们的组合。衬底可以包括在其表面上设置的一种或多种绝缘材料。绝缘材料可以包括一层或多层SiO2或其它绝缘材料。
例如，在一些实施例中，在制造工艺或其它类型工艺的前段制程(FEOL)阶段中，第一半导体器件102a的衬底可以包括包括在衬底上方和/或内形成的有源器件层的电路。电路可以包括合适于特殊应用的任何类型的电路。电路可以包括一种或多种电气或电子器件。例如，电路可以包括互连件以执行一种或多种功能的各种N型金属氧化物半导体(NMOS)器件和/或P型金属氧化物半导体(PMOS)器件，诸如晶体管、电容器、电阻器、二极管、光电二极管、熔丝等。电路的功能可以包括存储器结构、逻辑结构、处理结构、传感器、放大器、配电或电源管理、输入/输出电路、有源或无源器件、射频(RF)器件、模拟器件或数字器件等。本领域的普通技术人员将理解，为了说明性目的提供以上实例，以进一步解释一些说明性实施例的应用并且不意味着以任何方式限制本公开。第一半导体器件102a还可以包括如适合于给定应用的其它电路。
可以在电路系统上方，例如，第一半导体器件102a的衬底上方，形成互连结构。例如，可以在制造工艺的后段制程(BEOL)阶段中形成互连结构。互连结构可以包括在多个绝缘材料层内设置的多个导电部件、多个导电线和/或多个导电通孔。例如，互连结构可以包括层间电介质(ILD)、金属间介电(IMD)层或金属间层。例如，多个绝缘材料层可由使用本领域已知的任意合适的方法(诸如，旋涂、化学汽相沉积(CVD)或等离子体增强CVD(PECVD))形成的低K介电材料(诸如，磷硅酸盐玻璃(PSG)、硼磷硅酸盐玻璃(BPSG)、氟硅酸盐玻璃(FSG)、SiOxCy、未掺杂硅酸盐玻璃(USG)、旋涂玻璃、旋涂聚合物、碳化硅材料、它们的化合物、它们的复合物、其它材料、它们的组合或多层等)形成。
互连结构的多个导电部件、多个导电线和/或多个导电通孔将在衬底中和上形成的诸如无源和有源组件的各种电路彼此连接并且连接至外部组件。例如，互连结构可包括通过嵌入在介电层内的通孔(未示出)垂直互连的导电迹线的一层或多层，通孔使用镶嵌工艺或削减蚀刻(subtractive etch)技术形成。在一些实例中，可不包括互连结构。
第一半导体器件102a包括在其上设置的多个接触焊盘106a。如图1所示，多个接触焊盘106a的表面可以与第一半导体器件102a的表面共平面。还可以在第一半导体器件102a的表面上方设置多个接触焊盘106a，未示出。在一些实施例中，多个接触焊盘106a可以连接至第一半导体器件102a的互连结构内的导电部件、导电线和/或导电通孔。多个接触焊盘106a还可以直接地或通过互连结构连接至衬底的电路。例如，多个接触焊盘106a可以包括Cu、Al、其它金属或材料或它们的组合、多层或合金。图1至图3中示出三个接触焊盘106a；然而，第一半导体器件102a可以包括设置在第一半导体器件102a的表面上或形成在衬底或互连结构内的许多接触焊盘106a。多个接触焊盘106a在本文又称为多个第一接触焊盘。
还提供了第二半导体器件102b。在一些实施例中，第二半导体器件102b包括集成电路管芯或包括具有多个集成电路管芯的半导体晶圆。还可以提供包括已经从晶圆形态分割的集成电路管芯的多个第二半导体器件102b。第二半导体器件102b可以包括与第一半导体器件102a的描述相似的元件。例如，第二半导体器件102b可以包括衬底、电路和互连结构。在一些实施例中，第二半导体器件102b可以包括插入衬底(interposer substrate)(在图1中未示出；见图16和图17)，插入衬底包括形成在插入衬底中的多个贯通孔156。第二半导体器件102b包括在第二半导体器件102b上设置的多个接触焊盘106b。第二半导体器件102b的多个接触焊盘106b在本文又称为多个第二接触焊盘。
第二半导体器件102b可以是，但无需必须是，与第一半导体器件102a相同类型的器件，并且可使用相似的工艺制造第二半导体器件102b，并且第二半导体器件102b可包括与第一半导体器件102a相似的结构和材料。第二半导体器件102b还可包括与第一半导体器件102a不同类型的器件，并且可使用与第一半导体器件102a不同的工艺、结构和材料制造第二半导体器件102b。
如图1所示，第一半导体器件102a被颠倒并且通过多个间隔件104连接至第二半导体器件102b。第一半导体器件102a的接触焊盘106a与第二半导体器件102b的接触焊盘106b对准。在一些实施例中，多个间隔件104固定地或暂时地将第一半导体器件102a接合至第二半导体器件102b。例如，多个间隔件104可以包括诸如聚酰亚胺、聚对苯二甲酸乙二醇酯(PET)、聚甲基丙烯酸甲酯(PMMA)、硅、单面胶带、双面胶带、粘合剂、胶水和/或它们的组合或多层的材料。例如，在一些实施例中，多个间隔件104可以包括聚酰亚胺或PET双面胶带(具有PMMA或硅粘合剂)。在一些实施例中，多个间隔件104中的每个均包括包括尺寸d1的宽度，其中，例如，尺寸d1包括约50μm至约1,000μm。在一些实施例中，多个间隔件104包括包括尺寸d2的厚度，其中，例如，尺寸d2包括约5μm至约100μm。例如，在一些实施例中，多个间隔件104的尺寸d1和d2包括足以在第一半导体器件102a和第二半导体器件102b之间创建间隔的大小以用于溶剂114(见图2)流动从而在接触焊盘106a和106b之间形成浸没互连件120(见图3)。多个间隔件104通过接合器可以附接至第一半导体器件102a和/或第二半导体器件102b。还可以通过在第一半导体器件102a和/或第二半导体器件102b上方沉积材料，以及图案化沉积在第一半导体器件102a和/或第二半导体器件102b上的材料以形成多个间隔件104来形成多个间隔件104。如其他实例，在一些实施例中，还可以通过旋涂工艺或层压工艺施加多个间隔件104的材料。多个间隔件104还可以包括其它材料、尺寸和形成方法或附接方法。
例如，在一些实施例中，多个间隔件104可以附接至第一半导体器件102a或第二半导体器件102b，或者可以形成在第一半导体器件102a或第二半导体器件102b上。如另一实例，在一些实施例中，多个间隔件104的一部分还可以附接至第一半导体器件102a和第二半导体器件102b两者，或者可以形成在第一半导体器件102a和第二半导体器件102b两者上。例如，在一些实施例中，多个间隔件104设置在第一半导体器件102a或第二半导体器件102b的接近边缘或边界处。
在一些实施例中，第一半导体器件102a与第二半导体器件102b对准，从而第一半导体器件102a的多个接触焊盘106a的每个与第二半导体器件102b的多个接触焊盘106b中的一个对准。例如，在一些实施例中，第一半导体器件102a的多个接触焊盘106a和第二半导体器件102b的多个接触焊盘106b基本上可以具有相同图案。第一半导体器件102a和第二半导体器件102b可以包括在第一半导体器件102a和第二半导体器件102b上设置的对准标记(未示出)以在使用多个间隔件104的安装和接合工艺期间帮助对准。
在一些实施例中，例如，在水平方向上，多个间隔件104与多个接触焊盘106a和多个接触焊盘106b间隔开。例如，在一些实施例中，多个间隔件104没有设置为邻近多个接触焊盘106a和多个接触焊盘106b。例如，在一些实施例中，多个间隔件104可以与多个接触焊盘106a和多个接触焊盘106b间隔开以允许溶剂114流(见图2)穿过间隔件104并且到达多个接触焊盘106a和多个接触焊盘106b，从而可以在多个接触焊盘106a和多个接触焊盘106b之间制作浸没互连件120。多个间隔件104还可以与多个接触焊盘106a和多个接触焊盘106b间隔开足够多，从而浸没互连件120的部分可以横向地延伸超过接触焊盘106a和106b靠近接触焊盘106a和106b的边缘(见图7D)。
再次参照图1，在一些实施例中，接合的第一半导体器件102a和第二半导体器件102b包括半导体器件100，半导体器件100包括封装的半导体器件或3DIC。例如，在一些实施例中，将第一半导体器件102a连接至第二半导体器件102b包括形成3DIC器件。
区域110包括靠近多个接触焊盘106a中的一个和多个接触焊盘106b中的一个的区域。将参照图7A至图7D、图8A至图8D和图9A至图9D在本文进一步描述用于在区域110中的多个接触焊盘106a中的一个和多个接触焊盘106b中的一个之间形成浸没互连件120的更详细的工艺流程。
接下来参照图2，在如图1中示出的使用多个间隔件104将第一半导体器件102a和第二半导体器件102b对准、堆叠和接合在一起之后，在第一半导体器件102a和第二半导体器件102b之间形成垂直电连接件。在一些实施例中，使用浸没工艺形成垂直的电连接件。例如，在一些实施例中，浸没工艺包括化学镀工艺。
如图2中所示，第二半导体器件102b安装至支撑件112b，并且支撑件112a放置在第一半导体器件102a上方。支撑件112a和支撑件112b可以包括托盘、板、框架或其它类型的支撑器件或结构。例如，在一些实施例中，支撑件112a和支撑件112b可以包括化学镀套件的部分(见图10和图13中示出的化学镀套件130)。
再次参照图2，溶剂114从半导体器件100的一侧116a流动至半导体器件100的相对侧116b。溶剂114穿过多个间隔件104流入第一半导体器件102a和第二半导体器件102b之间以及多个接触焊盘106a和多个接触焊盘106b之间的间隙。例如，在一些实施例中，半导体器件100可以浸没在溶剂114中。在一些实施例中，溶剂114包括适合于化学镀至多个接触焊盘106a和多个接触焊盘106b上的材料。在一些实施例中，溶剂114包括化学镀溶剂。例如，在一些实施例中，溶剂114可以包括Cu、Ni、Pd、Au、Co、Ag、Sn、Pb、Rh、Fe和/或它们的组合。溶剂114还可以包括其它成分，诸如一种或多种抑制剂、流平剂、催化剂和/或其它添加剂。
如图3所示，溶剂114的流动持续预定的时间段，该预定的时间段足以在多个接触焊盘106a中的每个和多个接触焊盘106b中的一个之间形成浸没互连件120。例如，用于溶剂114的流动的持续时间量的变化可以取决于浸没互连件120包括的材料的类型和诸如期望的浸没互连件120的大小的其他因素。例如，可以编制按照材料类型(诸如Cu、Ni、Pd、Au、Co、Ag、Sn、Pb、Rh和/或Fe)的镀速的数据表，并且基于按照材料类型的镀速，可以确定形成期望大小的浸没互连件120所需的镀时间的估计。还可以使用其它方法确定用于溶剂114的流动的持续时间。
当已经超过用于形成浸没互连件120确定的持续时间时，溶剂114的流动停止，并且从支撑件112b和支撑件112a去除半导体器件100。在其中第二半导体器件102b包括晶圆的一些实施例中，分割晶圆，并且已经完成用于半导体器件100的制造工艺。将在此进一步描述还可以进行或继续的用于半导体器件100的封装工艺。同样地，在其中第一半导体器件102a包括晶圆的一些实施例中，分割晶圆，并且已经完成用于半导体器件100的制造工艺。还可以进行或继续用于半导体器件100的封装工艺。同样地，在其中第一半导体器件102a和第二半导体器件102b都包括集成电路管芯的实施例中，已经完成用于半导体器件100的制造工艺，或者也可以执行或持续用于半导体器件100的封装工艺。如另一实例，在一些实施例中，可以在支撑件112b上放置通过多个间隔件104接合的多个第一半导体器件102a和多个第二半导体器件102b，并且可以形成浸没互连件120。
根据一些实施例，在形成浸没互连件120之后，可以在半导体器件100上留下多个间隔件104。在一些实施例中，在形成浸没互连件120之后，可以去除多个间隔件104。例如，在其中多个间隔件104包括可以使用蚀刻工艺、清洗工艺和/或其它类型的工艺去除的材料的一些实施例中，在半导体器件100用于端应用程序或被进一步封装之前，可以去除多个间隔件104(见图16至图19，其中，未示出多个间隔件104将被包括在封装的半导体器件150和170中)。还可以使用其他方法去除多个间隔件104。
在一些实施例中，在图3中示出的浸没互连件120可以包括Cu、Ni、Pd、Au、Co、Ag、Sn、Pb、Rh、Fe或它们的组合。在一些实施例中，分别在第一半导体器件102a和第二半导体器件102b的多个接触焊盘106a和106b之间形成的浸没互连件120可以包括无焊料材料。在一些实施例中，例如，在第一半导体器件102a和第二半导体器件102b的多个接触焊盘106a和106b之间形成的浸没互连件120可以不包括合金，相反地，可以包括包括单一元素的材料。在一些实施例中，例如，包括含有元素元件的材料的浸没互连件120可以包括Cu、Ni、Pd、Au、Co、Ag、Sn、Pb、Rh或Fe。浸没互连件120也可以包括其它材料。
图4、图5和图6是根据一些实施例的图1至图3中示出的半导体器件100的部分的顶视图或仰视图,其示出半导体器件100的多个间隔件104和其它元件的一些示例性形状和位置。多个接触焊盘106a或106b可以布置为阵列。例如，图4、图5和图6中示出了多个接触焊盘106a或106b的三乘三的阵列。多个接触焊盘106a或106b还可以布置为其他形状。在图4中，多个间隔件104放置在第一半导体器件102a或第二半导体器件102b的拐角中，并且多个间隔件104基本上包括矩形。多个间隔件104还可以包括其它形状，诸如椭圆形、方形、圆形、L形或其它形状，并且多个间隔件104可以放置在第一半导体器件102a或第二半导体器件102b上的其它位置中。在图5中，多个间隔件104包括L形并且放置在第一半导体器件102a或第二半导体器件102b的拐角中。在图6中，多个间隔件104包括圆形并且放置在第一半导体器件102a或第二半导体器件102b的边界和边缘区域中的各个位置中。在一些实施例中，多个间隔件104彼此分隔开足够的空间从而溶剂114(见图2和图3)可以在多个间隔件104之间流动并且到达多个接触焊盘106a和106b。
图7A至图7D、图8A至图8D和图9A至图9D示出了根据一些实施例的用于图1至图3的区域110的浸没工艺的更详细的视图。图7A至图7D示出了根据一些实施例的在各个阶段的浸没工艺的截面图，其中，分别在第一半导体器件102a和第二半导体器件102b的接触焊盘106a和接触焊盘106b之间制成浸没互连件120。图7A示出了在溶剂114流动(见图2和图3)开始之前的接触焊盘106a和接触焊盘106b，其中，接触焊盘106a和接触焊盘106b基本上对准并且间隔开基本上与多个间隔件104的尺寸d2的厚度相同的量(见图1)。图7B示出了溶剂114的流动已经开始之后的浸没互连件120的第一部分120a的形成。浸没互连件120的第一部分120a形成在接触焊盘106a和接触焊盘106b的表面上方并且可以包括圆顶状。如图7C所示，随着溶剂114的流动持续，浸没互连件120的第二部分120b形成在接触焊盘106a和接触焊盘106b上方的第一部分120a上方。例如，在图7C中示出的浸没工艺阶段中，第二部分120b已经彼此连接。如图7D所示，随着溶剂114的流动持续，浸没互连件120的第三部分120c形成在接触焊盘106a和接触焊盘106b上方设置的第二部分120b上方。例如，第三部分120c可以横向地延伸并且增大浸没互连件120。浸没互连件120包括分别设置在第一半导体器件102a和第二半导体器件102b的接触焊盘106a和接触焊盘106b之间的第一部分120a、第二部分120b和第三部分120c。
在一些实施例中，多个接触焊盘106a和/或多个接触焊盘106b均包括连接至多个接触焊盘106a和/或多个接触焊盘106b的导电柱122a/122b(见图8A至图9D)，并且形成浸没互连件120还包括在导电柱122a/122b周围和/或上方形成浸没互连件120。例如，导电柱122a/122b连接至接触焊盘106a和/或106b并且可以包括铜、铜合金或其它导电材料。例如，可以使用镀敷工艺或沉积工艺形成导电柱122a/122b。还可以使用其它方法形成导电柱122a/122b。
例如，在图8A至图8D中，第一半导体器件102a的接触焊盘106a包括连接至接触焊盘106a的导电柱122a。图8A至图8D示出了根据一些实施例的在各个阶段的浸没工艺的截面图，其中，在连接至第一半导体器件102a的接触焊盘106a的导电柱122a和第二半导体器件102b的接触焊盘106b之间制成浸没互连件120。在图8A中，在第一半导体器件102a通过多个间隔件104连接至第二半导体器件102b之后，导电柱122a与接触焊盘106b间隔开基本上与包括多个间隔件104的尺寸d2的厚度相同的小于导电柱122a的厚度的量。图8B示出了溶剂114的流动已经开始之后的浸没互连件120的第一部分120a的形成。浸没互连件120的第一部分120a形成在导电柱122a和接触焊盘106b的表面上方并且可以包括接触焊盘106b上方的圆顶状。如图8C所示，随着溶剂114的流动持续，浸没互连件120的第二部分120b形成在导电柱122a和接触焊盘106b上方的第一部分120a上方。例如，在图8C中示出的浸没工艺阶段中，第二部分120b已经彼此连接。如图8D所示，随着溶剂114的流动持续，浸没互连件120的第三部分120c形成在设置在导电柱122a和接触焊盘106b上方的第二部分120b上方。例如，第三部分120c可以横向地延伸并且增大浸没互连件120。浸没互连件120包括第一部分120a、第二部分120b和第三部分120c，第一部分120a、第二部分120b和第三部分120c设置在导电柱122a(连接至第一半导体器件102a的接触焊盘106a的)周围、导电柱122a和第二半导体器件102b的接触焊盘106b之间。
图9A至图9D示出了根据一些实施例的在各个阶段的浸没工艺的截面图，其中，在连接至第一半导体器件102a的导电焊盘106a的导电柱122a和连接至第二半导体器件102b的导电焊盘106b的导电柱122b之间制作浸没互连件120。在图9A中，在通过多个间隔件104将第一半导体器件102a连接至第二半导体器件102b之后，导电柱122a与导电柱122b间隔开基本上与包括多个间隔件104的尺寸d2的厚度相同的小于导电柱122a和导电柱122b的厚度的量。图9B示出了在溶剂114的流动已经开始之后的浸没互连件120的第一部分120a的形成。浸没互连件120的第一部分120a形成在导电柱122a和导电柱122b的表面上方。如图9C所示，随着溶剂114的流动继续，浸没互连件120的第二部分120b形成在位于导电柱122a和导电柱122b上方的第一部分120a上方。例如，在图9C中示出的浸没工艺阶段中，第二部分120尚未彼此连接。如图9D所示，随着溶剂114的流动持续，浸没互连件120的第三部分120c形成在设置在导电柱122a和导电柱122b上方的第二部分120b上方。例如，第三部分120c将第二部分120b连接在一起。例如，第三部分120c还可以横向地延伸并且增大浸没互连件120。浸没互连件120包括第一部分120a、第二部分120b和第三部分120c，第一部分120a、第二部分120b和第三部分120c设置在分别连接至第一半导体器件102a和第二半导体器件102b的接触焊盘106a和接触焊盘106b的导电柱122a和导电柱122b之间。浸没互连件120的部分设置在导电柱122a和导电柱122b周围。
因此，在一些实施例中，多个第一接触焊盘106a和/或多个第二接触焊盘106b可以包括连接至多个第一接触焊盘106a和/或多个第二接触焊盘106b的导电柱122a或导电柱122b，并且形成浸没互连件120还包括在导电柱122a或122b周围形成浸没互连件120。
请注意，在一些实施例中，第二半导体器件102b的接触焊盘106b可以具有设置在接触焊盘106b上的导电柱122b，并且第一半导体器件102a的接触焊盘106a可能不具有在接触焊盘106a上设置的导电柱。还应该注意，在图8A至图8D和图9A至图9D中示出的一些实施例中，多个间隔件104可以包括包括尺寸d2的厚度，从而在图8A中示出的浸没工艺阶段中，导电柱122a最初与接触焊盘106b接触，或在图9A中示出的浸没工艺阶段中，导电柱122a最初与导电柱122b接触。
有利地，溶剂114的流动可以包括相对低温工艺，即，在约80摄氏度下或更低。例如，浸没互连件120包括无需高接合力或高热机械力而形成的电连接件或接头。因此，提高了半导体器件100的产量。另外，用于形成浸没互连件120的溶剂114的流动包括选择性沉积工艺，从而可能轻微失准的接触焊盘106a和接触焊盘106b和/或导电柱122a或导电柱122b将与形成的浸没连接件120连接。
图10是化学镀套件130的顶视图，示出了形成用于多个半导体器件100的浸没互连件120的方法。示出了包括晶圆上芯片(CoW)型流程设计套件的化学镀套件130，其中第二半导体器件102b是晶圆126形式并且以分割的集成电路管芯形式的多个第一半导体器件102a连接至晶圆126形式的第二半导体器件102b。例如，在浸没互连件120形成之后，晶圆126形式的第二半导体器件102b可以沿着划线128分割。例如，在一些实施例中，晶圆126可以包括半导体晶圆，和插入衬底晶圆或集成扇出(InFO)晶圆。
晶圆126形式的第二半导体器件102b(具有设置在第二半导体器件102b上的安装好的第一半导体器件102a)放置在化学镀套件130中。例如，使用泵132使溶剂114通过传送装置134流动至可以包括一个或多个管道、管、线路或沟道的半导体器件100。溶剂114横跨晶圆126在半导体器件100的第一半导体器件102a和第二半导体器件102b之间的间隙中流动。在图10中示出的一些实施例中，溶剂114从化学镀套件130的右侧流至左侧。然后，在一些实施例中，溶剂114经过脱泡器136和颗粒过滤器138，并且返回泵132。溶剂114继续横跨晶圆126在半导体器件100的第一半导体器件102a和第二半导体器件102b之间的间隙中流动直至完成浸没互连件120的形成。然后，从化学镀套件130去除晶圆126形式的第二半导体器件102b(具有设置在第二半导体器件102b上的安装好的第一半导体器件102a)。
图11和图12是示出化学镀工艺或浸没工艺中溶剂114的流动的图10中示出的化学镀套件的部分的截面图。在图11中示出了沿着图10中示出的视图中的x轴的第一半导体器件102a和第二半导体器件102b之间的溶剂114的流动。在图12中示出了沿着图10中示出的视图中的y轴的第一半导体器件102a和第二半导体器件102b之间的溶剂114的流动。
图13是示出形成用于多个半导体器件100的浸没互连件120的方法的化学镀套件130的顶视图。示出了包括芯片上芯片(CoC)型流程设计套件的化学镀套件130，其中，均为分割的集成电路管芯形式的第二半导体器件102b和第一半导体器件102a通过多个间隔件104接合在一起并且安装至化学镀套件130上。溶剂114横跨半导体器件100在多个半导体器件100的第一半导体器件102a和第二半导体器件102b之间的间隙中流动直至完成浸没互连件120的形成。然后，从化学镀套件130去除多个半导体器件100。
图14和图15是示出图13中示出的化学镀工艺或浸没工艺中溶剂114的流动的图13中示出的化学镀套件的部分的截面图。在图14中示出了沿着图13中示出的视图中的x轴的第一半导体器件102a和第二半导体器件102b之间的溶剂114的流动。在图15中示出了沿着图13中示出的视图中的y轴的第一半导体器件102a和第二半导体器件102b之间的溶剂114的流动。
图16至图19是示出包括浸没互连件的封装的半导体器件150和170的截面图。在图16和图17中，封装的半导体器件150可以包括包括插入衬底的第二半导体器件102b，并且包括在本文描述的半导体器件100的封装的半导体器件150可以包括3DIC或衬底上晶圆上芯片(CoWoS)器件。在图18和图19中，包括在本文描述的半导体器件100的封装的半导体器件170可以包括三维集成扇出(3D InFO)器件。
在图16中，封装的半导体器件150包括第一半导体器件102a，第一半导体器件102a包括通过多个浸没互连件120连接至第二半导体器件102b的集成电路管芯。如图16中所示，间隔件104可以留在封装的半导体器件150中，或者间隔件104可以被去除。第二半导体器件102b包括插入衬底154，插入衬底154包括在插入衬底154中形成的多个贯通孔156。多个贯通孔156为封装的半导体器件150提供从第二半导体器件102b的一侧(即，顶侧)至另一侧(即，底侧)的垂直电连接。第二半导体器件102b包括在每侧上为封装的半导体器件150提供水平电连接的互连结构158a和158b。例如，顶部互连结构158a可以包括由一个或多个导电线层组成的扇出引线。顶部互连结构158a还可以包括一个或多个导电通孔层，未示出。可以包括布置为球栅阵列(BGA)的焊球或凸块、可控塌陷芯片连接(C4)凸块或其它类型的连接件的多个连接件160可以连接至底部互连结构158b并且用于将封装的半导体器件150电连接至另一器件、板或端应用中的其他器件。例如，封装的半导体器件150可以通过连接件160连接至衬底以形成CoWoS器件。
例如，在一些实施例中，在第一半导体器件102a通过间隔件104连接至第二半导体器件102b之后或之前以及在形成浸没互连件120之后，连接件160可以连接至第二半导体器件102b。
绝缘材料152可以设置在第一半导体器件102a和第二半导体器件102b之间，例如，设置在浸没互连件120之间和周围。绝缘材料152可以包括环氧树脂、聚酰亚胺、底部填充材料或其它类型的材料。
图17示出了封装的半导体器件150，其中，第一半导体器件102a包括通过在本文描述的多个浸没互连件120连接至第二半导体器件102b的两个或多个集成电路管芯，第二半导体器件102b包括插入衬底154。例如，封装的半导体器件150可以通过连接件160连接至衬底以形成CoWoS器件。
根据一些实施例，一种制造器件的方法，包括：通过多个间隔件104将第一半导体器件102a连接至第二半导体器件102b,第一半导体器件102a具有在第一半导体器件102a上设置的多个第一接触焊盘106a,第二半导体器件102b具有在第二半导体器件102b上设置的多个第二接触焊盘106b，多个间隔件104与第一接触焊盘106a和第二接触焊盘106b间隔开。该方法包括使用化学镀工艺以在第一半导体器件102a的多个第一接触焊盘106a中的每个和第二半导体器件102b的多个第二接触焊盘106b中的一个之间形成浸没互连件120。在一些实施例中，如在图10中所示，第二半导体器件102b为晶圆的形式，并且该制造方法还包括分割第二半导体器件102b，例如，沿着划线128。
在一些实施例中，一种制造方法，包括连接包括集成电路管芯的第一半导体器件102a和第二半导体器件102b，并且第二半导体器件102b包括如图16或图17中示出的插入衬底154(包括在插入衬底154中设置的多个贯通孔156)、连接至插入衬底154和多个贯通孔156的互连结构158b和连接至互连结构158b的多个连接件160。
接下来参照图18，在一些实施例中，一种制造方法包括：连接包括第一集成电路管芯的第一半导体器件102a和包括第二集成电路管芯的第二半导体器件102b。该方法还包括在第二集成电路管芯周围形成模制材料172，在模制材料172中形成多个贯通孔156，以及将互连结构158连接至模制材料172、多个贯通孔156和第二集成电路管芯。多个连接件160可以连接至互连结构158。互连结构158可以包括用于封装的半导体器件170的扇出引线。在一些实施例中，封装的半导体器件170可以包括3D InFO器件。
在一些实施例中，一种制造方法包括：如图19中所示，提供包括多个第二集成电路管芯的第二半导体器件102b，并且该方法包括在多个第二集成电路管芯周围形成模制材料172。在一些实施例中，封装的半导体器件170可以包括3D InFO器件。
在图18和图19中示出的一些实施例中，首先第二半导体器件102b可以通过间隔件104连接至第一半导体器件102a并且可以形成浸没互连件120，接下来形成绝缘材料152、多个贯通孔156、模制材料172、互连结构158和连接件160。一个或多个载体可以用于利用模制材料172包封第二半导体器件102b并且形成封装的半导体器件170的其它部件，其它部件诸如贯通孔156、绝缘材料152、互连结构158和连接件160。在一些实施例中，第二半导体器件102b可以由模制材料172包封，并且在第一半导体器件102a通过间隔件104连接至第二半导体器件102b之前和在形成浸没互连件120之前，可以形成诸如贯通孔156、绝缘材料152、互连结构158和连接件160的封装的半导体器件170的其它部件。
图20是根据本发明的一些实施例示出的制造半导体器件100的方法的流程图180。在流程图180的步骤182中，第一半导体器件102a通过多个间隔件104连接至第二半导体器件102b，第一半导体器件102a具有在第一半导体器件102a上设置的多个第一接触焊盘106a，并且第二半导体器件102b具有在第一半导体器件102a上设置的多个第二接触焊盘106b(又见图1)。在步骤184中，在第一半导体器件102a的多个第一接触焊盘106a中的每个和第二半导体器件102b的多个第二接触焊盘106b中的一个之间形成浸没互连件120(又见图2和图3)。
如在此描述的，本发明的一些实施例包括半导体器件100，半导体器件100包括在接触焊盘106a和接触焊盘106b之间的间隔件104和浸没互连件120。一些实施例包括半导体器件100，半导体器件100包括在接触焊盘106a和接触焊盘106b之间的浸没互连件120，其中，已经去除间隔件104。本发明的一些实施例包括使用在本文描述的间隔件104以及浸没工艺制造包括浸没互连件120的半导体器件100的方法。
本发明的一些实施例的一些益处包括提供具有在集成电路管芯的接触焊盘之间的无焊料浸没连接件的半导体器件和3DIC。例如，提供后堆叠互连工艺和结构，当用于在3D封装应用中的高密度芯片堆叠时后堆叠互连工艺和结构是特别有利的。预对准管芯堆叠和后堆叠化学镀工艺用于形成包括浸没互连件的接头。在一些实施例中，与晶圆上管芯(CoW)工艺结合，在本文描述的浸没工艺可以使具有更高良率的已知良好管芯(KGD)成为可能，并且异质器件芯片可以堆叠在一个封装件中。
浸没互连包括简化的工艺流程和在诸如集成电路管芯的两个半导体器件之间的互连结构，并且在一些实施例中可以具有较短的周期，从而导致成本节约。可以在低温下而无需接合力或热机械力有利地执行用于形成浸没互连件的浸没工艺，导致提高的良率。通过浸没工艺和化学镀的使用，提高工艺窗口的共面性和对准。例如，用于形成浸没互连件的浸没工艺包括选择性沉积工艺，从而可能轻微失准的接触焊盘和/或导电柱将仍与形成的浸没连接件连接。在晶圆至晶圆、芯片至芯片和芯片至晶圆接合中可以实现在本文中描述的本公开的一些实施例。另外，可在现有的半导体器件制造和/或封装工艺流程和结构中容易地实现在本文描述的方法和器件。
在一些实施例中，一种制造器件的方法包括通过多个间隔件将第一半导体器件连接至第二半导体器件。第一半导体器件具有在第一半导体器件上设置的多个第一接触焊盘并且第二半导体器件具有在第一半导体器件上设置的多个第二接触焊盘。在第一半导体器件的多个第一接触焊盘中的每个和第二半导体器件的多个第二接触焊盘中的一个之间形成浸没互连件。
在一些实施例中，一种制造器件的方法包括：通过多个间隔件将第一半导体器件连接至第二半导体器件，第一半导体器件具有在第一半导体器件上设置的多个第一接触焊盘并且第二半导体器件具有在第二半导体器件上设置的多个第二接触焊盘。多个间隔件与第一接触焊盘和第二接触焊盘间隔开。该方法包括使用化学镀工艺以在第一半导体器件的多个第一接触焊盘中的每个和第二半导体器件的多个第二接触焊盘中的一个之间形成浸没互连件。
在一些实施例中，一种半导体器件包括第一集成电路管芯和连接至第一集成电路管芯的第二集成电路管芯，第一集成电路管芯具有在第一集成电路管芯上设置的多个第一接触焊盘，第二集成电路管芯具有在第二集成电路管芯上设置的多个第二接触焊盘。多个间隔件连接至第一集成电路管芯和第二集成电路管芯。在第一集成电路管芯和第二集成电路管芯之间靠近多个第一接触焊盘和多个第二接触焊盘设置多个间隔件。多个间隔件与第一接触焊盘和第二接触焊盘间隔开。在多个第一接触焊盘的每个和多个第二接触焊盘的一个之间形成浸没互连件。
根据本发明的一个实施例，提供了一种制造器件的方法，所述方法包括：通过多个间隔件将第一半导体器件连接至第二半导体器件，所述第一半导体器件具有设置在所述第一半导体器件上的多个第一接触焊盘，所述第二半导体器件具有设置在所述第二半导体器件上的多个第二接触焊盘；以及在所述第一半导体器件的所述多个第一接触焊盘的每个和所述第二半导体器件的所述多个第二接触焊盘的一个之间形成浸没互连件。
在上述方法中，将所述第一半导体器件连接至所述第二半导体器件包括将包括晶圆、集成电路管芯或多个集成电路管芯的第一半导体器件连接至所述第二半导体器件。
在上述方法中，将所述第一半导体器件连接至所述第二半导体器件包括将所述第一半导体器件连接至包括晶圆、集成电路管芯或多个集成电路管芯的第二半导体器件。
在上述方法中，所述多个第一接触焊盘或所述多个第二接触焊盘包括连接至所述多个第一接触焊盘或所述多个第二接触焊盘的导电柱，并且其中，形成所述浸没互连件还包括在所述导电柱周围形成所述浸没互连件。
在上述方法中，还包括去除所述多个间隔件。
在上述方法中，在所述第一半导体器件或所述第二半导体器件的接近边缘或边界处设置所述多个间隔件。
在上述方法中，将所述第一半导体器件连接至所述第二半导体器件包括形成三维集成电路(3DIC)器件。
根据本发明的另一实施例，还提供了一种制造器件的方法，所述方法包括：通过多个间隔件将第一半导体器件连接至第二半导体器件,所述第一半导体器件具有设置在所述第一半导体器件上的多个第一接触焊盘,所述第二半导体器件具有设置在所述第二半导体器件上的多个第二接触焊盘，所述多个间隔件与所述第一接触焊盘和所述第二接触焊盘间隔开；以及使用化学镀工艺以在所述第一半导体器件的所述多个第一接触焊盘的每个和所述第二半导体器件的所述多个第二接触焊盘的一个之间形成浸没互连件。
在上述方法中，所述第二半导体器件为晶圆形式，并且其中，所述方法还包括分割所述第二半导体器件。
在上述方法中，连接所述第一半导体器件包括连接集成电路管芯，并且其中，所述第二半导体器件包括：插入衬底，所述插入衬底包括设置在所述插入衬底中的多个贯通孔；连接至所述插入衬底和所述多个贯通孔的互连结构；以及连接至所述互连结构的多个连接件。
在上述方法中，连接所述第一半导体器件包括连接第一集成电路管芯，其中，所述第二半导体器件包括第二集成电路管芯，并且其中，所述方法还包括：在所述第二集成电路管芯周围形成模制材料；在所述模制材料中形成多个贯通孔；将互连结构连接至所述模制材料、所述多个贯通孔和所述第二集成电路管芯；以及将多个连接件连接至所述互连结构。
在上述方法中，所述互连结构包括扇出引线。
在上述方法中，所述第二半导体器件包括多个第二集成电路管芯，并且其中，所述方法包括在所述多个第二集成电路管芯周围形成所述模制材料。
在上述方法中，还包括封装所述第一半导体器件和所述第二半导体器件以形成衬底上晶圆上芯片(CoWoS)器件或三维集成扇出(3D InFO)器件。
根据本发明的又一实施例，还提供了一种半导体器件，包括：第一集成电路管芯，具有设置在所述第一集成电路管芯上的多个第一接触焊盘；第二集成电路管芯，连接至所述第一集成电路管芯，具有设置在所述第二集成电路管芯上的多个第二接触焊盘；多个间隔件，连接至所述第一集成电路管芯和所述第二集成电路管芯并且设置在所述第一集成电路管芯和所述第二集成电路管芯之间、接近所述多个第一接触焊盘和所述多个第二接触焊盘，所述多个间隔件与所述第一接触焊盘和所述第二接触焊盘间隔开；以及浸没互连件，设置在所述多个第一接触焊盘的每个和所述多个第二接触焊盘的一个之间。
在上述半导体器件中，所述浸没互连件包括无焊料材料。
在上述半导体器件中，所述浸没互连件包括从由Cu、Ni、Pd、Au、Co、Ag、Sn、Pb、Rh、Fe和它们的组合组成的组选择的材料。
在上述半导体器件中，所述多个间隔件包括50μm至1,000μm的宽度。
在上述半导体器件中，所述多个间隔件包括5μm至100μm的厚度。
在上述半导体器件中，所述多个间隔件包括从由聚酰亚胺、聚对苯二甲酸乙二醇酯(PET)、聚甲基丙烯酸甲酯(PMMA)、硅、单面胶带、双面胶带、粘合剂、胶和它们的组合组成的组选择的材料。
上面概述了若干实施例的部件、使得本领域技术人员可以更好地理解本发明的方面。本领域技术人员应该理解，他们可以容易地使用本发明作为基础来设计或修改用于实现与在此所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围、并且在不背离本发明的精神和范围的情况下，在此他们可以做出多种变化、替换以及改变。

Claims (10)

1.一种制造器件的方法，所述方法包括：
通过多个非导电间隔件将第一半导体器件连接至第二半导体器件，所述第一半导体器件具有设置在所述第一半导体器件上的多个第一接触焊盘，所述第二半导体器件具有设置在所述第二半导体器件上的多个第二接触焊盘，所述多个非导电间隔件与所述第一接触焊盘和所述第二接触焊盘间隔开，在将所述第一半导体器件连接至所述第二半导体器件之后，所述多个第一接触焊盘与所述多个第二接触焊盘电隔离；以及
之后，所述第一半导体器件和所述第二半导体器件安装在化学镀套件上并且至少部分浸没在流动的溶剂中，所述溶剂通过所述第一半导体器件和所述第二半导体器件之间的间隙并且经过所述间隙的位于相邻的所述第一接触焊盘之间的部分，从所述第一半导体器件和所述第二半导体器件的一侧单向地持续流动至所述第一半导体器件和所述第二半导体器件的相对侧，从而通过镀从所述多个第一接触焊盘的面向所述第二半导体器件的表面延伸并且进一步从所述多个第二接触焊盘的面向所述第一半导体器件的表面延伸的导电材料，在所述第一半导体器件的所述多个第一接触焊盘的一个的表面上方和所述第二半导体器件的所述多个第二接触焊盘的相应一个的表面上方形成浸没互连件的第一部分，随着所述溶剂的流动持续，浸没互连件的第二部分形成在所述第一接触焊盘和所述第二接触焊盘上方的所述第一部分上方并且彼此连接，随着所述溶剂的流动持续，浸没互连件的第三部分形成在所述第一接触焊盘和所述第二接触焊盘上方设置的第二部分上方，所述第三部分横向地延伸，所述溶剂经过所述第一半导体器件、所述第二半导体器件并且经过脱泡器循环流动。
2.根据权利要求1所述的方法，其中，将所述第一半导体器件连接至所述第二半导体器件包括将包括晶圆、集成电路管芯或多个集成电路管芯的第一半导体器件连接至所述第二半导体器件。
3.根据权利要求1所述的方法，其中，将所述第一半导体器件连接至所述第二半导体器件包括将所述第一半导体器件连接至包括晶圆、集成电路管芯或多个集成电路管芯的第二半导体器件。
4.根据权利要求1所述的方法，还包括去除所述多个非导电间隔件。
5.根据权利要求1所述的方法，其中，在所述第一半导体器件或所述第二半导体器件的接近边缘或边界处设置所述多个非导电间隔件。
6.根据权利要求1所述的方法，其中，将所述第一半导体器件连接至所述第二半导体器件包括形成三维集成电路(3DIC)器件。
7.一种制造器件的方法，所述方法包括：
通过多个非导电间隔件将第一半导体器件连接至第二半导体器件，所述第一半导体器件具有设置在所述第一半导体器件上的多个第一接触焊盘,所述第二半导体器件具有设置在所述第二半导体器件上的多个第二接触焊盘，所述多个非导电间隔件与所述第一接触焊盘和所述第二接触焊盘间隔开，在将所述第一半导体器件连接至所述第二半导体器件之后，所述多个第一接触焊盘与所述多个第二接触焊盘电隔离；以及
之后，所述第一半导体器件和所述第二半导体器件安装在化学镀套件上并且至少部分浸没在流动的溶剂中，所述溶剂通过所述第一半导体器件和所述第二半导体器件之间的间隙并且经过所述间隙的位于相邻的所述第一接触焊盘之间的部分，从所述第一半导体器件和所述第二半导体器件的一侧单向地持续流动至所述第一半导体器件和所述第二半导体器件的相对侧，从而使用化学镀工艺以在所述第一半导体器件的所述多个第一接触焊盘的一个和所述第二半导体器件的所述多个第二接触焊盘的相应一个之间形成浸没互连件，其中，所述浸没互连件通过镀从所述多个第一接触焊盘的面向所述第二半导体器件的表面延伸并且进一步从所述多个第二接触焊盘的面向所述第一半导体器件的表面延伸的导电材料形成，所述浸没互连件由与所述第一半导体器件接触的第一段以及与所述第二半导体器件接触的第二段组成，所述第一段的侧壁向内凹陷，所述溶剂脱泡器经过所述第一半导体器件、所述第二半导体器件并且经过脱泡器循环流动。
8.根据权利要求7所述的方法，其中，所述第二半导体器件为晶圆形式，并且其中，所述方法还包括分割所述第二半导体器件。
9.一种半导体器件，包括：
第一集成电路管芯，具有设置在所述第一集成电路管芯上的多个第一接触焊盘；
第二集成电路管芯，连接至所述第一集成电路管芯，具有设置在所述第二集成电路管芯上的多个第二接触焊盘；
多个间隔件，连接至所述第一集成电路管芯和所述第二集成电路管芯并且设置在所述第一集成电路管芯和所述第二集成电路管芯之间、接近所述多个第一接触焊盘和所述多个第二接触焊盘，所述多个间隔件与所述第一接触焊盘和所述第二接触焊盘间隔开；以及
浸没互连件，设置在所述多个第一接触焊盘的每个和所述多个第二接触焊盘的一个之间；
所述浸没互连件的与所述第一接触焊盘接触的表面以及所述第一集成电路管芯的表面共平面，所述浸没互连件的与所述第二接触焊盘接触的表面以及所述第二集成电路管芯的表面共平面；
所述浸没互连件的部分在所述第一集成电路管芯的表面和所述第二集成电路管芯的表面横向地延伸超过所述多个第一接触焊盘和所述多个第二接触焊盘的边缘，所述浸没互连件的整个侧壁向内凹陷，所述侧壁分为邻接所述第一集成电路管芯的第一部分和邻接所述第二集成电路管芯的第二部分，所述第一部分和所述第二部分均向内凹陷。
10.一种制造器件的方法，所述方法包括：
通过多个非导电间隔件将第一半导体器件连接至第二半导体器件，所述第一半导体器件具有设置在所述第一半导体器件上的多个第一接触焊盘，所述第二半导体器件具有设置在所述第二半导体器件上的多个第二接触焊盘，并且所述多个第二接触焊盘横跨连接的所述第一半导体器件和所述第二半导体器件之间的间隙与所述多个第一接触焊盘电隔离，所述多个非导电间隔件与所述第一接触焊盘和所述第二接触焊盘间隔开；以及
所述第一半导体器件和所述第二半导体器件安装在化学镀套件上，通过所述间隙中的溶剂经过所述间隙的位于相邻的所述第一接触焊盘之间的部分，并且从所述第一半导体器件和所述第二半导体器件的一侧单向地持续流动至所述第一半导体器件和所述第二半导体器件的相对侧，以对所述第一半导体器件的所述多个第一接触焊盘的一个的表面以及对所述第二半导体器件的所述多个第二接触焊盘的相应一个的表面作用，从而在所述第一半导体器件的所述多个第一接触焊盘的一个和所述第二半导体器件的所述多个第二接触焊盘的相应一个之间形成导电浸没互连件，所述溶剂脱泡器经过所述第一半导体器件、所述第二半导体器件并且经过脱泡器循环流动。
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