CN115656609B - Inductance current sampling circuit - Google Patents
Inductance current sampling circuit Download PDFInfo
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- CN115656609B CN115656609B CN202211692537.XA CN202211692537A CN115656609B CN 115656609 B CN115656609 B CN 115656609B CN 202211692537 A CN202211692537 A CN 202211692537A CN 115656609 B CN115656609 B CN 115656609B
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Abstract
The invention relates to the technical field of switching power supplies, and particularly discloses an inductance current sampling circuit, which comprises: the sampling module can collect current initial sampling signals under various control signals according to a preset proportion, wherein the current initial sampling signals comprise a forward current initial sampling signal under a high-side control signal, a forward current initial sampling signal under a low-side control signal, a reverse current initial sampling signal under the high-side control signal and a reverse current initial sampling signal under the low-side control signal; and the operation module is used for respectively carrying out operation processing on the current initial sampling signals under different control signals to obtain corresponding current sampling data. The inductance current sampling circuit provided by the invention has the advantage of high sampling precision.
Description
Technical Field
The invention relates to the technical field of switching power supplies, in particular to an inductance current sampling circuit.
Background
Inductor current sampling is one of the important modules of a switching power supply circuit, and resistance sampling, DCR sampling, MOSFET sampling and the like are generally adopted in the prior art.
As shown in fig. 1, a schematic circuit diagram of resistor sampling is shown, wherein the basic principle of resistor sampling is to make the current flowing through the switching tube be the current generated by the sampling voltage on the resistor R1 by utilizing the characteristics of "virtual break" and "virtual short" of the operational amplifier, and then amplify the current and output the amplified current. In the resistor sampling mode, the operational amplifier structure is adopted, so that the sampling speed is ensured, and the operational amplifier with wider bandwidth is required, so that the size of a sampling circuit is larger, the power consumption is higher, and accurate current sampling cannot be obtained.
As shown in fig. 2, which is a schematic circuit diagram of DCR sampling, the DCR sampling circuit includes a sampling resistor Rs and a sampling capacitor Cs, where Rs is connected in series with Cs and then connected in parallel with an inductance L (the inductance dc resistance is represented by RL), and the basic principle is that: when the Rs, cs and L branch time constants are perfectly matched (cs×rs=l/RL), the voltage signal Vsense across Cs is equal to IL times RL. The DCR sampling circuit has the problems that the time constant of the sampling circuit is not matched, compensation adjustment is needed, stability and dynamic response speed are difficult to be compatible, and the sampling precision is low.
As shown in fig. 3, a schematic diagram of a MOSFET sampling circuit is shown, current detection is performed through a sampling resistor at the source of a MOS transistor, and this mode is generally used for a power supply controlled by a valley mode, and the sampling precision is poor due to inconsistent conditions of three ends of the MOS transistor and the power transistor caused by the existence of the sampling resistor.
Therefore, how to improve the sampling accuracy of the sampling circuit is a technical problem to be solved by those skilled in the art.
Disclosure of Invention
The invention provides an inductance current sampling circuit, which solves the problem of low sampling precision in the related technology.
As one aspect of the present invention, there is provided an inductor current sampling circuit, comprising:
The sampling module can collect current initial sampling signals under various control signals according to a preset proportion, wherein the current initial sampling signals comprise a forward current initial sampling signal under a high-side control signal, a forward current initial sampling signal under a low-side control signal, a reverse current initial sampling signal under the high-side control signal and a reverse current initial sampling signal under the low-side control signal;
and the operation module is used for respectively carrying out operation processing on the current initial sampling signals under different control signals to obtain corresponding current sampling data.
Further, the sampling module comprises a high-side sampling unit and a low-side sampling unit, the high-side sampling unit is connected with the low-side sampling unit,
the high-side sampling unit is used for collecting current according to a preset proportion under a high-side control signal and obtaining a forward current initial sampling signal under the high-side control signal and a reverse current initial sampling signal under the high-side control signal;
the low-side sampling unit is used for collecting current according to a preset proportion under a low-side control signal and obtaining a forward current initial sampling signal under the low-side control signal and a reverse current initial sampling signal under the low-side control signal.
Further, the high-side sampling unit includes: a first power tube, a first sampling tube and a second sampling tube,
the driving end of the first power tube is used for connecting a high-side control signal, the first end and the second end of the first power tube are both connected with the operation module,
the driving end of the first sampling tube is connected with a high-side control signal, the first end and the second end of the first sampling tube are both connected with the operation module, the second end of the first sampling tube is connected with the second end of the first power tube,
the driving end of the second sampling tube is connected with the driving end of the first sampling tube, the first end and the second end of the second sampling tube are both connected with the operation module, and the first end of the second sampling tube is connected with the first end of the first power tube.
Further, the low-side sampling unit includes: a second power tube, a third sampling tube and a fourth sampling tube,
the driving end of the second power tube is used for connecting a low-side control signal, the first end of the second power tube is connected with the operation module, the second end of the second power tube is connected with signal ground, the first end of the second power tube is connected with the second end of the first power tube,
The driving end of the third sampling tube is connected with the driving end of the second power tube, the first end and the second end of the third sampling tube are both connected with the operation module, the first end of the third sampling tube is connected with the first end of the second power tube,
the driving end of the fourth sampling tube is connected with the driving end of the third sampling tube, the first end of the fourth sampling tube is connected with the operation module, and the second end of the fourth sampling tube is connected with the signal ground.
Further, the operation module comprises a high-side sampling current operation unit and a low-side sampling current operation unit,
the high-side sampling current operation unit is used for respectively carrying out operation processing on a forward current initial sampling signal under the high-side control signal and a reverse current initial sampling signal under the high-side control signal to obtain corresponding current sampling data,
the low-side sampling current operation unit is used for respectively carrying out operation processing on the forward current initial sampling signal under the low-side control signal and the reverse current initial sampling signal under the low-side control signal to obtain corresponding current sampling data.
Further, the high-side sampling current operation unit includes: a first operational amplifier, a second operational amplifier, a first operational MOS tube, a second operational MOS tube, a third operational MOS tube, a fourth operational MOS tube, a fifth operational MOS tube, a sixth operational MOS tube, a first switch, a second switch, a third switch and a fourth switch,
The normal phase input end of the first operational amplifier is connected with the first end of the first sampling tube, the reverse phase input end of the first operational amplifier is connected with the first end of the first power tube, the two ends of the first switch are respectively connected with the normal phase input end and the reverse phase input end of the first operational amplifier,
the driving end of the first operation MOS tube is connected with the output end of the first operation amplifier, the first end of the first operation MOS tube is connected with the first end of the first sampling tube, the second end of the first operation MOS tube is connected with the signal ground, the two ends of the second switch are respectively connected with the driving end of the first operation MOS tube and the signal ground,
the driving end of the second operation MOS tube is connected with the driving end of the first operation MOS tube, the first end of the second operation MOS tube is an output end of the operation module, the second end of the second operation MOS tube is connected with a signal ground,
the normal phase input end of the second operational amplifier is connected with the second end of the second sampling tube, the reverse phase input end of the second operational amplifier is connected with the second end of the first power tube, the two ends of the third switch are respectively connected with the normal phase input end and the reverse phase input end of the second operational amplifier,
The driving end of the third operation MOS tube is connected with the output end of the second operation amplifier, the first end of the third operation MOS tube is connected with the second end of the second sampling tube, the second end of the third operation MOS tube is connected with the signal ground, the two ends of the fourth switch are respectively connected with the driving end of the third operation MOS tube and the signal ground,
the driving end of the fourth operation MOS tube is connected with the driving end of the third operation MOS tube, the second end of the fourth operation MOS tube is connected with the signal ground,
the driving end and the second end of the fifth operation MOS tube are both connected with the first end of the fourth operation MOS tube,
the driving end of the sixth operation MOS tube is connected with the driving end of the fifth operation MOS tube, the first end of the sixth operation MOS tube is connected with the first end of the fifth operation MOS tube, the second end of the sixth operation MOS tube is the output end of the operation module, and the first end of the sixth operation MOS tube and the first end of the fifth operation MOS tube are both connected with power supply voltage.
Further, the first operation MOS tube, the second operation MOS tube, the third operation MOS tube and the fourth operation MOS tube all comprise N-type MOSFET tubes, the fifth operation MOS tube and the sixth operation MOS tube all comprise P-type MOSFET tubes, the driving end of each N-type MOSFET tube is a grid, the first end of each N-type MOSFET tube is a drain electrode, the second end of each N-type MOSFET tube is a source electrode, the driving end of each P-type MOSFET tube is a grid, the first end of each P-type MOSFET tube is a source electrode, and the second end of each P-type MOSFET tube is a drain electrode.
Further, the low-side sampling current operation unit includes: a third operational amplifier, a fourth operational amplifier, a seventh operational MOS tube, an eighth operational MOS tube, a ninth operational MOS tube, a tenth operational MOS tube, an eleventh operational MOS tube, a twelfth operational MOS tube, a fifth switch, a sixth switch, a seventh switch and an eighth switch,
the normal phase input end of the third operational amplifier is connected with the first end of the fourth sampling tube, the reverse phase input end of the third operational amplifier is connected with the first end of the second power tube, the two ends of the fifth switch are respectively connected with the normal phase input end and the reverse phase input end of the third operational amplifier,
the driving end of the seventh operation MOS tube is connected with the output end of the third operation amplifier, the second end of the seventh operation MOS tube is connected with the first end of the fourth sampling tube, the two ends of the sixth switch are respectively connected with the output end of the third operation amplifier and the first end of the seventh operation MOS tube,
the driving end of the eighth operation MOS tube is connected with the driving end of the seventh operation MOS tube, the first end of the eighth operation MOS tube is connected with the first end of the seventh operation MOS tube, the first end of the eighth operation MOS tube and the first end of the seventh operation MOS tube are both connected with the power supply voltage,
The positive phase input end of the fourth operational amplifier is connected with the second end of the third sampling tube, the negative phase input end of the fourth operational amplifier is connected with the second end of the second power tube, the two ends of the seventh switch are respectively connected with the positive phase input end and the negative phase input end of the fourth operational amplifier,
the driving end of the ninth operational MOS tube is connected with the output end of the fourth operational amplifier, the second end of the ninth operational MOS tube is connected with the second end of the third sampling tube, the two ends of the eighth switch are respectively connected with the output end of the fourth operational amplifier and the first end of the ninth operational MOS tube,
the driving end of the tenth operation MOS tube is connected with the driving end of the ninth operation MOS tube, the first end of the tenth operation MOS tube is connected with the first end of the ninth operation MOS tube, the second end of the tenth operation MOS tube is an output end of the operation module, the first end of the tenth operation MOS tube and the first end of the ninth operation MOS tube are both connected with the power supply voltage,
the driving end of the eleventh operation MOS tube is connected with the first end of the eleventh operation MOS tube, the first end of the eleventh operation MOS tube is connected with the second end of the eighth operation MOS tube, the second end of the eleventh operation MOS tube is connected with the signal ground,
The driving end of the twelfth operation MOS tube is connected with the first end of the eleventh operation MOS tube, the first end of the twelfth operation MOS tube is connected with the second end of the tenth operation MOS tube, and the second end of the twelfth operation MOS tube is connected with the signal ground.
Further, the seventh operation MOS transistor, the eighth operation MOS transistor, the ninth operation MOS transistor and the tenth operation MOS transistor all include P-type MOSFET transistors, the eleventh operation MOS transistor and the twelfth operation MOS transistor all include N-type MOSFET transistors, the drive end of N-type MOSFET transistors is the grid, the first end of N-type MOSFET transistors is the drain, the second end of N-type MOSFET transistors is the source, the drive end of P-type MOSFET transistors is the grid, the first end of P-type MOSFET transistors is the source, the second end of P-type MOSFET transistors is the drain.
Further, the first power tube, the second power tube, the first sampling tube, the second sampling tube, the third sampling tube and the fourth sampling tube all comprise N-type MOSFET tubes, the driving end of each N-type MOSFET tube is a grid, the first end of each N-type MOSFET tube is a drain, and the second end of each N-type MOSFET tube is a source.
According to the inductor current sampling circuit provided by the invention, the sampling module is used for collecting the initial current sampling signals under various control signals, the initial current sampling signals under the high-low side control signals are included, the forward current and the reverse current can be collected, and the working condition and the main power tube are always consistent when the sampling function is realized through the negative feedback structure, so that the ratio of the collected initial current sampling signals to the preset sampling current is realized, and the sampling precision can be effectively ensured.
Drawings
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification, illustrate the invention and together with the description serve to explain, without limitation, the invention.
Fig. 1 is a schematic diagram of a resistor sampling circuit in the prior art.
Fig. 2 is a schematic diagram of a DCR sampling circuit in the prior art.
Fig. 3 is a schematic diagram of a MOSFET sampling circuit in the prior art.
Fig. 4 is a schematic diagram of an inductor current sampling circuit according to the present invention.
Fig. 5 is a schematic diagram of a test feature of current sampling using an inductor current sampling circuit according to the present invention.
Fig. 6a is a layout diagram of an integrated device of the inductor current sampling circuit according to the present invention.
Fig. 6b is a layout diagram of another integrated device of the inductor current sampling circuit according to the present invention.
Detailed Description
It should be noted that, without conflict, the embodiments of the present invention and features of the embodiments may be combined with each other. The invention will be described in detail below with reference to the drawings in connection with embodiments.
In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate in order to describe the embodiments of the invention herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
In this embodiment, an inductor current sampling circuit is provided, and fig. 4 is a schematic circuit diagram of a circuit structure of the inductor current sampling circuit provided according to an embodiment of the present invention, as shown in fig. 4, including:
the sampling module 100 is capable of collecting current initial sampling signals under various control signals according to a preset proportion, wherein the current initial sampling signals comprise a forward current initial sampling signal under a high-side control signal, a forward current initial sampling signal under a low-side control signal, a reverse current initial sampling signal under the high-side control signal and a reverse current initial sampling signal under the low-side control signal;
The operation module 200 performs operation processing on the current initial sampling signals under different control signals respectively to obtain corresponding current sampling data.
It should be noted that, in the embodiment of the present invention, the high-side control signal may be specifically understood as a control signal of the gate driving end of the high-side power tube, and the subsequent sampling may be performed only when the control signal is at a high level; the low-side control signal can be understood as a control signal of the gate driving end of the low-side power tube, and the subsequent sampling is only performed when the control signal is at a high level.
It should be understood that the inductor current sampling circuit in the embodiment of the invention can also realize forward and reverse current sampling under the condition of being compatible with the control signals of the high-low side power tube.
In the embodiment of the invention, the sampling module is used for collecting the initial current sampling signals under various control signals, the initial current sampling signals comprise the initial current sampling signals under the high-low side control signals, the forward current and the reverse current can be collected, and the working condition and the main power tube are always consistent when the sampling function is realized through the negative feedback structure, so that the collected initial current sampling signals are in proportion to the preset sampling current, and the sampling precision can be effectively ensured.
In particular, as shown in fig. 4, the sampling module 100 includes a high-side sampling unit 110 and a low-side sampling unit 120, the high-side sampling unit 110 being connected to the low-side sampling unit 120,
the high-side sampling unit 110 is configured to collect current according to a preset ratio under a high-side control signal and obtain a forward current initial sampling signal under the high-side control signal and a reverse current initial sampling signal under the high-side control signal;
the low-side sampling unit 120 is configured to collect current according to a preset ratio under a low-side control signal and obtain a forward current initial sampling signal under the low-side control signal and a reverse current initial sampling signal under the low-side control signal.
It should be understood that the high-side sampling unit 110 can collect forward and reverse currents according to a predetermined ratio, and the low-side sampling unit 120 can collect forward and reverse currents according to a predetermined ratio.
In an embodiment of the present invention, as shown in fig. 4, the high-side sampling unit 110 includes: a first power tube M1, a first sampling tube M3 and a second sampling tube M4,
the driving end of the first power tube M1 is used for connecting a high-side control signal GH, the first end and the second end of the first power tube M1 are both connected with the operation module 200,
The driving end of the first sampling tube M3 is connected with a high-side control signal GH, the first end and the second end of the first sampling tube M3 are both connected with the operation module 200, the second end of the first sampling tube M3 is connected with the second end of the first power tube M1,
the driving end of the second sampling tube M4 is connected with the driving end of the first sampling tube M3, the first end and the second end of the second sampling tube M4 are both connected with the operation module 200, and the first end of the second sampling tube M4 is connected with the first end of the first power tube M1.
Note that, since the first sampling tube M3 and the second sampling tube M4 are both kept at 1 with the first power tube M1: n, and by combining the virtual short and virtual break characteristics of the operational amplifier in the operation module 200, it can be realized that the voltages at the three ends of the first sampling tube M3 and the second sampling tube M4 are consistent with the voltage at the three ends of the first power tube M1, so as to ensure that the ratio of the sampling current to the inductance current is the same as the ratio of the sampling tube width to length and the ratio of the power tube width to length is 1: n, thereby helping to increase the current sampling accuracy under the high-side control signal.
In an embodiment of the present invention, the low-side sampling unit 120 includes: a second power tube M2, a third sampling tube M5 and a fourth sampling tube M6,
The driving end of the second power tube M2 is used for connecting a low-side control signal GL, the first end of the second power tube M2 is connected with the operation module 200, the second end of the second power tube M2 is connected with a signal ground PGND, and the first end of the second power tube M2 is connected with the second end of the first power tube M1,
the driving end of the third sampling tube M5 is connected with the driving end of the second power tube M2, the first end and the second end of the third sampling tube M5 are both connected with the operation module 200, the first end of the third sampling tube M5 is connected with the first end of the second power tube M2,
the driving end of the fourth sampling tube M6 is connected with the driving end of the third sampling tube M5, the first end of the fourth sampling tube M6 is connected with the operation module 200, and the second end of the fourth sampling tube M6 is connected with the signal ground PGND.
It should be noted that, under the control of the low-side control signal GL, since the third sampling tube M5 and the fourth sampling tube M6 are both kept at 1 with the second power tube M2: n, and by combining the virtual short and virtual break characteristics of the operational amplifier in the operation module 200, it can be realized that the voltages at the three ends of the third sampling tube M5 and the fourth sampling tube M6 are consistent with the voltage at the three ends of the second power tube M2, so as to ensure that the ratio of the sampling current to the inductance current is the same as the ratio of the sampling tube width to length and the ratio of the power tube width to length is 1: n, thereby helping to increase the current sampling accuracy under the high-side control signal.
In the embodiment of the present invention, the first power tube M1, the second power tube M2, the first sampling tube M3, the second sampling tube M4, the third sampling tube M5 and the fourth sampling tube M6 each include an N-type MOSFET tube, the driving end of the N-type MOSFET tube is a gate, the first end of the N-type MOSFET tube is a drain, and the second end of the N-type MOSFET tube is a source.
It should be noted that, in the high-side sampling unit 110 and the low-side sampling unit 120, since the voltages at the three ends of the first sampling tube M3 and the second sampling tube M4 are consistent with the voltage at the three ends of the first power tube M1, the voltages at the three ends of the third sampling tube M5 and the fourth sampling tube M6 are consistent with the voltage at the three ends of the second power tube M2, that is, there is no sampling resistor connected in series at the source of the sampling tube, so that loss can be reduced and sampling accuracy can be improved.
Specifically, the operation module 200 includes a high-side sampling current operation unit 210 and a low-side sampling current operation unit 220,
the high-side sampling current operation unit 210 is configured to perform operation processing on the forward current initial sampling signal under the high-side control signal and the reverse current initial sampling signal under the high-side control signal, respectively, to obtain corresponding current sampling data,
The low-side sampling current operation unit is configured to 220 perform operation processing on the forward current initial sampling signal under the low-side control signal and the reverse current initial sampling signal under the low-side control signal, respectively, to obtain corresponding current sampling data.
Specifically, the high-side sampling current operation unit 210 includes: a first operational amplifier A1, a second operational amplifier A2, a first operational MOS tube NM1, a second operational MOS tube NM2, a third operational MOS tube NM3, a fourth operational MOS tube NM4, a fifth operational MOS tube PM1, a sixth operational MOS tube PM2, a first switch S1, a second switch S2, a third switch S3 and a fourth switch S4,
the non-inverting input terminal SH1 of the first operational amplifier A1 is connected with the first end of the first sampling tube M3, the inverting input terminal V1 of the first operational amplifier A1 is connected with the first end of the first power tube M1, the two ends of the first switch S1 are respectively connected with the non-inverting input terminal SH1 and the inverting input terminal V1 of the first operational amplifier A1,
the driving end of the first operation MOS tube NM1 is connected with the output end of the first operation amplifier A1, the first end of the first operation MOS tube NM1 is connected with the first end of the first sampling tube M3, the second end of the first operation MOS tube NM1 is connected with a signal ground PGND, two ends of the second switch S2 are respectively connected with the driving end of the first operation MOS tube NM1 and the signal ground PGND,
The driving end of the second operation MOS tube NM2 is connected with the driving end of the first operation MOS tube NM1, the first end of the second operation MOS tube NM2 is an operation module output end IMON, the second end of the second operation MOS tube NM2 is connected with a signal ground PGND,
the non-inverting input terminal SH2 of the second operational amplifier A2 is connected with the second terminal of the second sampling tube M4, the inverting input terminal SW of the second operational amplifier A2 is connected with the second terminal of the first power tube M1, the two ends of the third switch S3 are respectively connected with the non-inverting input terminal SH2 and the inverting input terminal SW of the second operational amplifier A2,
the driving end of the third operation MOS tube NM3 is connected with the output end of the second operation amplifier A2, the first end of the third operation MOS tube NM3 is connected with the second end of the second sampling tube M4, the second end of the third operation MOS tube NM3 is connected with the signal ground PGND, the two ends of the fourth switch S4 are respectively connected with the driving end of the third operation MOS tube NM3 and the signal ground PGND,
the driving end of the fourth operation MOS tube NM4 is connected with the driving end of the third operation MOS tube NM3, the second end of the fourth operation MOS tube NM4 is connected with the signal ground PGND,
the driving end and the second end of the fifth operation MOS tube PM1 are both connected with the first end of the fourth operation MOS tube NM4,
The driving end of the sixth operation MOS tube PM2 is connected to the driving end of the fifth operation MOS tube PM1, the first end of the sixth operation MOS tube PM2 is connected to the first end of the fifth operation MOS tube PM1, and the second end of the sixth operation MOS tube PM2 is the operation module output end IMON.
In the embodiment of the invention, the first operation MOS transistor NM1, the second operation MOS transistor NM2, the third operation MOS transistor NM3 and the fourth operation MOS transistor NM4 each include an N-type MOSFET transistor, the fifth operation MOS transistor PM1 and the sixth operation MOS transistor PM2 each include a P-type MOSFET transistor, the driving end of the N-type MOSFET transistor is a gate, the first end of the N-type MOSFET transistor is a drain, the second end of the N-type MOSFET transistor is a source, the driving end of the P-type MOSFET transistor is a gate, the first end of the P-type MOSFET transistor is a source, and the second end of the P-type MOSFET transistor is a drain.
Specifically, the low-side sampling current operation unit 220 includes: a third operational amplifier A3, a fourth operational amplifier A4, a seventh operational MOS tube PM3, an eighth operational MOS tube PM4, a ninth operational MOS tube PM5, a tenth operational MOS tube PM6, an eleventh operational MOS tube NM5, a twelfth operational MOS tube NM6, a fifth switch S5, a sixth switch S6, a seventh switch S7 and an eighth switch S8,
The non-inverting input end SL1 of the third operational amplifier A3 is connected with the first end of the fourth sampling tube M6, the inverting input end SW of the third operational amplifier A3 is connected with the first end of the second power tube M2, the two ends of the fifth switch S5 are respectively connected with the non-inverting input end SL1 and the inverting input end SW of the third operational amplifier A3,
the driving end of the seventh operational MOS tube PM3 is connected with the output end of the third operational amplifier A3, the second end of the seventh operational MOS tube PM3 is connected with the first end of the fourth sampling tube M6, the two ends of the sixth switch S6 are respectively connected with the output end of the third operational amplifier A3 and the first end of the seventh operational MOS tube PM3,
the driving end of the eighth operation MOS tube PM4 is connected with the driving end of the seventh operation MOS tube PM3, the first end of the eighth operation MOS tube PM4 is connected with the first end of the seventh operation MOS tube PM3,
the non-inverting input end SL2 of the fourth operational amplifier A4 is connected with the second end of the third sampling tube M5, the inverting input end of the fourth operational amplifier A4 is connected with the second end of the second power tube M2, the two ends of the seventh switch S7 are respectively connected with the non-inverting input end SL2 and the inverting input end of the fourth operational amplifier A4,
The driving end of the ninth operational MOS tube PM5 is connected with the output end of the fourth operational amplifier A4, the second end of the ninth operational MOS tube PM5 is connected with the second end of the third sampling tube M5, the two ends of the eighth switch S8 are respectively connected with the output end of the fourth operational amplifier A4 and the first end of the ninth operational MOS tube PM5,
the driving end of the tenth operation MOS tube PM6 is connected with the driving end of the ninth operation MOS tube PM5, the first end of the tenth operation MOS tube PM6 is connected with the first end of the ninth operation MOS tube PM5, the second end of the tenth operation MOS tube PM6 is an operation module output end IMON,
the driving end of the eleventh operation MOS tube NM5 is connected with the first end of the eleventh operation MOS tube NM5, the first end of the eleventh operation MOS tube NM5 is connected with the second end of the eighth operation MOS tube PM4, the second end of the eleventh operation MOS tube NM5 is connected with the signal ground PGND,
the driving end of the twelfth operation MOS transistor NM6 is connected to the first end of the eleventh operation MOS transistor NM5, the first end of the twelfth operation MOS transistor NM6 is connected to the second end of the tenth operation MOS transistor PM6, and the second end of the twelfth operation MOS transistor NM6 is connected to the signal ground PGND.
In the embodiment of the present invention, the seventh operation MOS transistor PM3, the eighth operation MOS transistor PM4, the ninth operation MOS transistor PM5, and the tenth operation MOS transistor PM6 each include a P-type MOSFET transistor, the eleventh operation MOS transistor NM5 and the twelfth operation MOS transistor NM6 each include an N-type MOSFET transistor, the driving end of the N-type MOSFET transistor is a gate, the first end of the N-type MOSFET transistor is a drain, the second end of the N-type MOSFET transistor is a source, the driving end of the P-type MOSFET transistor is a gate, the first end of the P-type MOSFET transistor is a source, and the second end of the P-type MOSFET transistor is a drain.
The working principle of the inductor current sampling circuit according to the embodiment of the present invention is described in detail below with reference to fig. 4.
As shown in fig. 4, taking the above-mentioned inductor current sampling circuit as an example applied to BUCK topology (BUCK), the above-mentioned voltage V1 end is an input voltage, the drain electrode of the first power tube M1 is connected with the input voltage, the source electrode of the first power tube M1 is connected with the drain electrode of the second power tube M2 and one end of the inductor, the other end of the inductor is connected with the output end, the gate electrode of the first power tube M1 is connected with the high-side control signal GH of the PWM, the source electrode of the second power tube M2 is connected with the signal ground PGND, the gate electrode of the second power tube M2 is connected with the low-side control signal GL of the PWM, one end of the output capacitor is connected with the output end, the other end of the output capacitor is connected with the ground potential, one end of the load is connected with the output end, and the other end is connected with the signal ground.
The specific working principle is as follows: first, the first sampling tube M3 and the second sampling tube M4 are both kept at 1 with the first power tube M1: n, the third sampling tube M5 and the fourth sampling tube M6 are kept 1 as the second power tube M2: n, aspect ratio relationship; by utilizing the characteristics of 'virtual short' and 'virtual break' of the operational amplifier, the potential of the normal phase input end SH1 and the potential of the reverse phase input end V1 of the first operational amplifier A1 are equal, the potential of the normal phase input end SH2 and the potential of the reverse phase input end SW of the second operational amplifier A2 are equal, the potential of the normal phase input end SL1 and the potential of the reverse phase input end SW of the third operational amplifier A3 are equal, and the potential of the normal phase input end SL2 and the potential of the reverse phase input end of the fourth operational amplifier A4 are equal, so that the voltage of the grid source drain terminal of each sampling tube and the corresponding power tube are consistent, and the sampling current and the inductance current ratio are ensured to be the same as the width-length ratio of the sampling tube and the width-length ratio of the power tube, and are 1: n; the high-side negative sampling current IL/n in the first sampling tube M3 flows from SW to signal ground through the first operation MOS tube NM1, and the first operation MOS tube NM1 and the second operation MOS tube NM2 convert the sampling current into output current IMON through M times proportion mirror image; similarly, the high-side positive sampling current IL/n in the second sampling tube M4 flows from the input voltage to the signal ground through the third operation MOS tube NM3, and the sampling current is converted into the output current IMON through M times proportion mirror images of the third operation MOS tube NM3, the fourth operation MOS tube NM4, the fifth operation MOS tube PM1 and the sixth operation MOS tube PM 2; the low side positive sampling current IL/n in the third sampling tube M5 flows to the SW point from the power supply voltage VDD through the ninth operation MOS tube PM5, and the ninth operation MOS tube PM5 and the tenth operation MOS tube PM6 convert the sampling current into output current IMON (namely the output end of the operation module) through M times proportion mirror image; the low-side negative sampling current IL/n in the fourth sampling tube M6 flows from the power supply voltage VDD to the signal ground through the seventh operation MOS tube PM3, and the sampling current is converted into the output current IMON by the M-time proportional mirror image of the seventh operation MOS tube PM3, the eighth operation MOS tube PM4, the eleventh operation MOS tube NM5, and the twelfth operation MOS tube NM6, (imon=mbil/n). The first operation MOS tube NM1, the third operation MOS tube NM3, the seventh operation MOS tube PM3 and the eleventh operation MOS tube NM5 respectively provide sampling paths for high-side negative current, high-side positive current, low-side negative current and low-side positive current, and compatible sampling of positive and negative currents of high-side power tubes and low-side power tubes of the switching power supply is achieved. Here, the positive and negative directions of the current of the sampling tube are referenced to the direction of the inductor current, and the direction of the inductor current from SW to the output end is positive.
As shown in fig. 5, with buck as an embodiment, under the PWM control signal, the IMON can proportionally reproduce the triangular wave inductor current on the corresponding time axis with the upper and lower power transistors alternately turned on, and the dead time IMON output is 0.
As shown in fig. 6a and 6b, fig. 6a is a layout diagram of the inductor current sampling circuit integrated on the same substrate, fig. 6b is a layout diagram of the inductor current sampling circuit integrated on two substrates, and fig. 4 is a layout diagram of the inductor current sampling circuit shown in fig. 6 b.
The embodiment of the invention adopts a full-integration mode, and integrates the power tube, the sampling tube and the current operation circuit into the chip. Fig. 6a shows that the inductor current sampling circuits are all integrated in the same base island a, fig. 6b shows that the sampling modules in the inductor current sampling circuits are integrated in the base island b, the operation module is integrated in the base island c, the inductor current sampling circuits shown in fig. 4 adopt the layout form of fig. 6b, that is, the sampling modules and the operation module formed by the power tube and the proportional MOS sampling tube are respectively located in two different base islands, and SL1', SL2 and SL2', SH1 and SH1', SH2 and SH2' are respectively output to the sampling current operation circuit through the kelvin connection method, and in both schemes of fig. 6a and 6b, the sampling tube is matched in the middle form of the power tube so as to ensure the sampling precision.
It should be noted that, in the embodiment of the present invention, the current sampling routing mode adopts kelvin connection, so as to effectively avoid the influence of loss in the routing process on sampling precision, for example, SH1 and SH1 'are connected to the drain terminal of M3, but are introduced into two different input terminals of a current sampling operation circuit, where SH1 is connected to the op amp input terminal, and is in a high-resistance state, no current flows through sampling tube M3 to sample current flowing from SH1', so that inconsistent voltages between the drain terminal of sampling tube M3 and the drain terminal of power tube M1 due to routing loss are avoided, and thus sampling precision is ensured.
It should be understood that the inductor current sampling current provided by the present invention is only illustrated by taking the BUCK topology shown in fig. 4 as an example, and is not limited to the BUCK topology type, and is also applicable to other topology types, for example, the inductor current sampling current can be implemented by making adaptive changes to other topology types such as BOOST, BUCK-BOOST, etc. which are well known to those skilled in the art, and will not be repeated herein.
In summary, the inductor current sampling circuit provided by the invention not only can be compatible with high-low side power MOS bidirectional current sampling, but also can effectively improve sampling precision because a common source-level series sampling resistor of MOSFET sampling technology is omitted, loss is reduced, meanwhile, the condition of a proportional MOS sampling tube is kept consistent with the condition of a power tube three-terminal, and no temperature coefficient exists in sampling. In addition, the inductance current sampling circuit provided by the invention is highly integrated, the system is small in volume, no external sampling Pin is arranged, the built-in power tube and the sampling tube are connected with the sampling current operation circuit in a Kelvin mode, and the sampling precision is ensured.
It is to be understood that the above embodiments are merely illustrative of the application of the principles of the present invention, but not in limitation thereof. Various modifications and improvements may be made by those skilled in the art without departing from the spirit and substance of the invention, and are also considered to be within the scope of the invention.
Claims (6)
1. An inductor current sampling circuit, comprising:
the sampling module can collect current initial sampling signals under various control signals according to a preset proportion, wherein the current initial sampling signals comprise a forward current initial sampling signal under a high-side control signal, a forward current initial sampling signal under a low-side control signal, a reverse current initial sampling signal under the high-side control signal and a reverse current initial sampling signal under the low-side control signal;
the operation module is used for respectively carrying out operation processing on the current initial sampling signals under different control signals to obtain corresponding current sampling data;
the sampling module comprises a high-side sampling unit and a low-side sampling unit, and the high-side sampling unit is connected with the low-side sampling unit;
the high-side sampling unit includes: a first power tube, a first sampling tube and a second sampling tube,
The driving end of the first power tube is used for connecting a high-side control signal, the first end and the second end of the first power tube are both connected with the operation module,
the driving end of the first sampling tube is connected with a high-side control signal, the first end and the second end of the first sampling tube are both connected with the operation module, the second end of the first sampling tube is connected with the second end of the first power tube,
the driving end of the second sampling tube is connected with the driving end of the first sampling tube, the first end and the second end of the second sampling tube are both connected with the operation module, and the first end of the second sampling tube is connected with the first end of the first power tube;
the low-side sampling unit includes: a second power tube, a third sampling tube and a fourth sampling tube,
the driving end of the second power tube is used for connecting a low-side control signal, the first end of the second power tube is connected with the operation module, the second end of the second power tube is connected with signal ground, the first end of the second power tube is connected with the second end of the first power tube,
the driving end of the third sampling tube is connected with the driving end of the second power tube, the first end and the second end of the third sampling tube are both connected with the operation module, the first end of the third sampling tube is connected with the first end of the second power tube,
The driving end of the fourth sampling tube is connected with the driving end of the third sampling tube, the first end of the fourth sampling tube is connected with the operation module, and the second end of the fourth sampling tube is connected with the signal ground;
the operation module comprises a high-side sampling current operation unit and a low-side sampling current operation unit;
the high-side sampling current operation unit includes: a first operational amplifier, a second operational amplifier, a first operational MOS tube, a second operational MOS tube, a third operational MOS tube, a fourth operational MOS tube, a fifth operational MOS tube, a sixth operational MOS tube, a first switch, a second switch, a third switch and a fourth switch,
the normal phase input end of the first operational amplifier is connected with the first end of the first sampling tube, the reverse phase input end of the first operational amplifier is connected with the first end of the first power tube, the two ends of the first switch are respectively connected with the normal phase input end and the reverse phase input end of the first operational amplifier,
the driving end of the first operation MOS tube is connected with the output end of the first operation amplifier, the first end of the first operation MOS tube is connected with the first end of the first sampling tube, the second end of the first operation MOS tube is connected with the signal ground, the two ends of the second switch are respectively connected with the driving end of the first operation MOS tube and the signal ground,
The driving end of the second operation MOS tube is connected with the driving end of the first operation MOS tube, the first end of the second operation MOS tube is an output end of the operation module, the second end of the second operation MOS tube is connected with a signal ground,
the normal phase input end of the second operational amplifier is connected with the second end of the second sampling tube, the reverse phase input end of the second operational amplifier is connected with the second end of the first power tube, the two ends of the third switch are respectively connected with the normal phase input end and the reverse phase input end of the second operational amplifier,
the driving end of the third operation MOS tube is connected with the output end of the second operation amplifier, the first end of the third operation MOS tube is connected with the second end of the second sampling tube, the second end of the third operation MOS tube is connected with the signal ground, the two ends of the fourth switch are respectively connected with the driving end of the third operation MOS tube and the signal ground,
the driving end of the fourth operation MOS tube is connected with the driving end of the third operation MOS tube, the second end of the fourth operation MOS tube is connected with the signal ground,
the driving end and the second end of the fifth operation MOS tube are both connected with the first end of the fourth operation MOS tube,
the driving end of the sixth operation MOS tube is connected with the driving end of the fifth operation MOS tube, the first end of the sixth operation MOS tube is connected with the first end of the fifth operation MOS tube, the second end of the sixth operation MOS tube is the output end of the operation module, and the first end of the sixth operation MOS tube and the first end of the fifth operation MOS tube are both connected with a power supply voltage;
The low-side sampling current operation unit includes: a third operational amplifier, a fourth operational amplifier, a seventh operational MOS tube, an eighth operational MOS tube, a ninth operational MOS tube, a tenth operational MOS tube, an eleventh operational MOS tube, a twelfth operational MOS tube, a fifth switch, a sixth switch, a seventh switch and an eighth switch,
the normal phase input end of the third operational amplifier is connected with the first end of the fourth sampling tube, the reverse phase input end of the third operational amplifier is connected with the first end of the second power tube, the two ends of the fifth switch are respectively connected with the normal phase input end and the reverse phase input end of the third operational amplifier,
the driving end of the seventh operation MOS tube is connected with the output end of the third operation amplifier, the second end of the seventh operation MOS tube is connected with the first end of the fourth sampling tube, the two ends of the sixth switch are respectively connected with the output end of the third operation amplifier and the first end of the seventh operation MOS tube,
the driving end of the eighth operation MOS tube is connected with the driving end of the seventh operation MOS tube, the first end of the eighth operation MOS tube is connected with the first end of the seventh operation MOS tube, the first end of the eighth operation MOS tube and the first end of the seventh operation MOS tube are both connected with the power supply voltage,
The positive phase input end of the fourth operational amplifier is connected with the second end of the third sampling tube, the negative phase input end of the fourth operational amplifier is connected with the second end of the second power tube, the two ends of the seventh switch are respectively connected with the positive phase input end and the negative phase input end of the fourth operational amplifier,
the driving end of the ninth operational MOS tube is connected with the output end of the fourth operational amplifier, the second end of the ninth operational MOS tube is connected with the second end of the third sampling tube, the two ends of the eighth switch are respectively connected with the output end of the fourth operational amplifier and the first end of the ninth operational MOS tube,
the driving end of the tenth operation MOS tube is connected with the driving end of the ninth operation MOS tube, the first end of the tenth operation MOS tube is connected with the first end of the ninth operation MOS tube, the second end of the tenth operation MOS tube is an output end of the operation module, the first end of the tenth operation MOS tube and the first end of the ninth operation MOS tube are both connected with the power supply voltage,
the driving end of the eleventh operation MOS tube is connected with the first end of the eleventh operation MOS tube, the first end of the eleventh operation MOS tube is connected with the second end of the eighth operation MOS tube, the second end of the eleventh operation MOS tube is connected with the signal ground,
The driving end of the twelfth operation MOS tube is connected with the first end of the eleventh operation MOS tube, the first end of the twelfth operation MOS tube is connected with the second end of the tenth operation MOS tube, and the second end of the twelfth operation MOS tube is connected with a signal ground;
wherein, first sampling pipe and second sampling pipe all keep 1 with first power tube: n, wherein the third sampling tube and the fourth sampling tube are kept 1 with the second power tube: n, aspect ratio relationship.
2. The inductor current sampling circuit of claim 1 wherein,
the high-side sampling unit is used for collecting current according to a preset proportion under a high-side control signal and obtaining a forward current initial sampling signal under the high-side control signal and a reverse current initial sampling signal under the high-side control signal;
the low-side sampling unit is used for collecting current according to a preset proportion under a low-side control signal and obtaining a forward current initial sampling signal under the low-side control signal and a reverse current initial sampling signal under the low-side control signal.
3. The inductor current sampling circuit of claim 1 wherein,
the high-side sampling current operation unit is used for respectively carrying out operation processing on a forward current initial sampling signal under the high-side control signal and a reverse current initial sampling signal under the high-side control signal to obtain corresponding current sampling data,
The low-side sampling current operation unit is used for respectively carrying out operation processing on the forward current initial sampling signal under the low-side control signal and the reverse current initial sampling signal under the low-side control signal to obtain corresponding current sampling data.
4. The inductor current sampling circuit of claim 1 wherein the first, second, third and fourth operational MOS transistors each comprise an N-type MOSFET transistor, the fifth and sixth operational MOS transistors each comprise a P-type MOSFET transistor, the driving end of the N-type MOSFET transistor is a gate, the first end of the N-type MOSFET transistor is a drain, the second end of the N-type MOSFET transistor is a source, the driving end of the P-type MOSFET transistor is a gate, the first end of the P-type MOSFET transistor is a source, and the second end of the P-type MOSFET transistor is a drain.
5. The inductor current sampling circuit of claim 1 wherein the seventh, eighth, ninth and tenth operational MOS transistors each comprise a P-type MOSFET transistor, the eleventh and twelfth operational MOS transistors each comprise an N-type MOSFET transistor, the drive end of the N-type MOSFET transistor is a gate, the first end of the N-type MOSFET transistor is a drain, the second end of the N-type MOSFET transistor is a source, the drive end of the P-type MOSFET transistor is a gate, the first end of the P-type MOSFET transistor is a source, and the second end of the P-type MOSFET transistor is a drain.
6. The inductor current sampling circuit of claim 1 wherein the first power tube, the second power tube, the first sampling tube, the second sampling tube, the third sampling tube and the fourth sampling tube each comprise an N-type MOSFET tube, the drive end of the N-type MOSFET tube is a gate, the first end of the N-type MOSFET tube is a drain, and the second end of the N-type MOSFET tube is a source.
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