CN115656609A - Inductive current sampling circuit - Google Patents
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- CN115656609A CN115656609A CN202211692537.XA CN202211692537A CN115656609A CN 115656609 A CN115656609 A CN 115656609A CN 202211692537 A CN202211692537 A CN 202211692537A CN 115656609 A CN115656609 A CN 115656609A
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Abstract
The invention relates to the technical field of switching power supplies, and particularly discloses an inductive current sampling circuit, which comprises: the sampling module can acquire current initial sampling signals under various control signals according to a preset proportion, wherein the current initial sampling signals include a forward current initial sampling signal under a high-side control signal, a forward current initial sampling signal under a low-side control signal, a reverse current initial sampling signal under the high-side control signal and a reverse current initial sampling signal under the low-side control signal; and the operation module is used for respectively carrying out operation processing on the current initial sampling signals under different control signals to obtain corresponding current sampling data. The inductive current sampling circuit provided by the invention has the advantage of high sampling precision.
Description
Technical Field
The invention relates to the technical field of switching power supplies, in particular to an inductive current sampling circuit.
Background
Inductor current sampling is one of the important modules of a switching power supply circuit, and resistance sampling, DCR sampling, MOSFET sampling and the like are generally adopted in the prior art.
As shown in fig. 1, the circuit schematic diagram of resistance sampling is shown, wherein the basic principle of resistance sampling is to use the "virtual break" and "virtual short" characteristics of an operational amplifier to make the current flowing through a switching tube be the current generated by the sampling voltage on a resistor R1, and then amplify and output the current. The resistance sampling mode is formed by adopting an operational amplifier structure, and the operational amplifier with a wider bandwidth is needed in order to ensure the sampling speed, so that the sampling circuit has larger size and higher power consumption, and accurate current sampling cannot be obtained.
As shown in fig. 2, a schematic diagram of a DCR sampling circuit is shown, the DCR sampling circuit includes a sampling resistor Rs and a sampling capacitor Cs, rs and Cs are connected in series and then connected in parallel with an inductor L (RL represents an inductor dc resistance), and the basic principle is as follows: when the Rs, cs and L branch time constants are perfectly matched (Cs Rs = L/RL), the voltage signal Vsense across Cs is equal to IL times RL. According to the DCR sampling circuit, due to the fact that the time constant of the sampling circuit is unmatched, compensation adjustment is needed, stability and dynamic response speed are difficult to consider, and the problem of low sampling precision can be caused.
As shown in fig. 3, a schematic diagram of a MOSFET sampling circuit is shown, which is a power supply for valley mode control, and current detection is performed through a sampling resistor at the source of an MOS transistor, and the sampling precision is poor due to the fact that the sampling resistor has a condition that the three terminals of the MOS transistor and the power transistor are inconsistent.
Therefore, how to improve the sampling precision of the sampling circuit becomes an urgent technical problem to be solved by those skilled in the art.
Disclosure of Invention
The invention provides an inductive current sampling circuit, which solves the problem of low sampling precision in the related technology.
As an aspect of the present invention, there is provided an inductor current sampling circuit, including:
the sampling module can acquire current initial sampling signals under various control signals according to a preset proportion, wherein the current initial sampling signals include a forward current initial sampling signal under a high-side control signal, a forward current initial sampling signal under a low-side control signal, a reverse current initial sampling signal under the high-side control signal and a reverse current initial sampling signal under the low-side control signal;
and the operation module is used for respectively performing operation processing on the current initial sampling signals under different control signals to obtain corresponding current sampling data.
Further, the sampling module comprises a high-side sampling unit and a low-side sampling unit, the high-side sampling unit is connected with the low-side sampling unit,
the high-side sampling unit is used for collecting current according to a preset proportion under a high-side control signal and obtaining a forward current initial sampling signal under the high-side control signal and a reverse current initial sampling signal under the high-side control signal;
the low-side sampling unit is used for collecting current according to a preset proportion under the low-side control signal and obtaining a forward current initial sampling signal under the low-side control signal and a reverse current initial sampling signal under the low-side control signal.
Further, the high-side sampling unit includes: a first power tube, a first sampling tube and a second sampling tube,
the driving end of the first power tube is used for connecting a high-side control signal, the first end and the second end of the first power tube are both connected with the operation module,
the driving end of the first sampling tube is connected with a high-side control signal, the first end and the second end of the first sampling tube are both connected with the operation module, the second end of the first sampling tube is connected with the second end of the first power tube,
the driving end of the second sampling tube is connected with the driving end of the first sampling tube, the first end and the second end of the second sampling tube are both connected with the operation module, and the first end of the second sampling tube is connected with the first end of the first power tube.
Further, the low-side sampling unit includes: a second power tube, a third sampling tube and a fourth sampling tube,
the driving end of the second power tube is used for connecting a low-side control signal, the first end of the second power tube is connected with the operation module, the second end of the second power tube is connected with a signal ground, and the first end of the second power tube is connected with the second end of the first power tube,
the driving end of the third sampling tube is connected with the driving end of the second power tube, the first end and the second end of the third sampling tube are both connected with the operation module, the first end of the third sampling tube is connected with the first end of the second power tube,
the driving end of the fourth sampling tube is connected with the driving end of the third sampling tube, the first end of the fourth sampling tube is connected with the operation module, and the second end of the fourth sampling tube is connected with the signal ground.
Further, the operation module comprises a high-side sampling current operation unit and a low-side sampling current operation unit,
the high-side sampling current arithmetic unit is used for respectively carrying out arithmetic processing on a forward current initial sampling signal under the high-side control signal and a reverse current initial sampling signal under the high-side control signal to obtain corresponding current sampling data,
the low-side sampling current arithmetic unit is used for respectively carrying out arithmetic processing on a forward current initial sampling signal under the low-side control signal and a reverse current initial sampling signal under the low-side control signal to obtain corresponding current sampling data.
Further, the high-side sampling current operation unit includes: a first operational amplifier, a second operational amplifier, a first operational MOS transistor, a second operational MOS transistor, a third operational MOS transistor, a fourth operational MOS transistor, a fifth operational MOS transistor, a sixth operational MOS transistor, a first switch, a second switch, a third switch and a fourth switch,
the positive input end of the first operational amplifier is connected with the first end of the first sampling tube, the negative input end of the first operational amplifier is connected with the first end of the first power tube, the two ends of the first switch are respectively connected with the positive input end and the negative input end of the first operational amplifier,
the driving end of the first operational MOS tube is connected with the output end of the first operational amplifier, the first end of the first operational MOS tube is connected with the first end of the first sampling tube, the second end of the first operational MOS tube is connected with a signal ground, the two ends of the second switch are respectively connected with the driving end of the first operational MOS tube and the signal ground,
the driving end of the second operation MOS tube is connected with the driving end of the first operation MOS tube, the first end of the second operation MOS tube is the output end of the operation module, the second end of the second operation MOS tube is connected with a signal ground,
the positive input end of the second operational amplifier is connected with the second end of the second sampling tube, the negative input end of the second operational amplifier is connected with the second end of the first power tube, two ends of the third switch are respectively connected with the positive input end and the negative input end of the second operational amplifier,
the driving end of the third operational MOS tube is connected with the output end of the second operational amplifier, the first end of the third operational MOS tube is connected with the second end of the second sampling tube, the second end of the third operational MOS tube is connected with a signal ground, the two ends of the fourth switch are respectively connected with the driving end of the third operational MOS tube and the signal ground,
the driving end of the fourth operation MOS tube is connected with the driving end of the third operation MOS tube, the second end of the fourth operation MOS tube is connected with a signal ground,
the driving end and the second end of the fifth operation MOS tube are both connected with the first end of the fourth operation MOS tube,
the driving end of the sixth operation MOS tube is connected with the driving end of the fifth operation MOS tube, the first end of the sixth operation MOS tube is connected with the first end of the fifth operation MOS tube, the second end of the sixth operation MOS tube is the output end of the operation module, and the first end of the sixth operation MOS tube and the first end of the fifth operation MOS tube are both connected with a power supply voltage.
Further, the first operation MOS transistor, the second operation MOS transistor, the third operation MOS transistor and the fourth operation MOS transistor all include N-type MOSFET transistors, the fifth operation MOS transistor and the sixth operation MOS transistor all include P-type MOSFET transistors, the driving end of the N-type MOSFET transistor is a gate, the first end of the N-type MOSFET transistor is a drain, the second end of the N-type MOSFET transistor is a source, the driving end of the P-type MOSFET transistor is a gate, the first end of the P-type MOSFET transistor is a source, and the second end of the P-type MOSFET transistor is a drain.
Further, the low-side sampling current operation unit includes: a third operational amplifier, a fourth operational amplifier, a seventh operational MOS transistor, an eighth operational MOS transistor, a ninth operational MOS transistor, a tenth operational MOS transistor, an eleventh operational MOS transistor, a twelfth operational MOS transistor, a fifth switch, a sixth switch, a seventh switch, and an eighth switch,
the positive phase input end of the third operational amplifier is connected with the first end of the fourth sampling tube, the negative phase input end of the third operational amplifier is connected with the first end of the second power tube, two ends of the fifth switch are respectively connected with the positive phase input end and the negative phase input end of the third operational amplifier,
the driving end of the seventh operational MOS tube is connected with the output end of the third operational amplifier, the second end of the seventh operational MOS tube is connected with the first end of the fourth sampling tube, the two ends of the sixth switch are respectively connected with the output end of the third operational amplifier and the first end of the seventh operational MOS tube,
the driving end of the eighth operation MOS tube is connected with the driving end of the seventh operation MOS tube, the first end of the eighth operation MOS tube is connected with the first end of the seventh operation MOS tube, the first end of the eighth operation MOS tube and the first end of the seventh operation MOS tube are both connected with a power supply voltage,
the positive input end of the fourth operational amplifier is connected with the second end of the third sampling tube, the negative input end of the fourth operational amplifier is connected with the second end of the second power tube, two ends of the seventh switch are respectively connected with the positive input end and the negative input end of the fourth operational amplifier,
the driving end of the ninth operation MOS tube is connected with the output end of the fourth operation amplifier, the second end of the ninth operation MOS tube is connected with the second end of the third sampling tube, two ends of the eighth switch are respectively connected with the output end of the fourth operation amplifier and the first end of the ninth operation MOS tube,
the driving end of the tenth operation MOS tube is connected with the driving end of the ninth operation MOS tube, the first end of the tenth operation MOS tube is connected with the first end of the ninth operation MOS tube, the second end of the tenth operation MOS tube is the output end of the operation module, the first end of the tenth operation MOS tube and the first end of the ninth operation MOS tube are both connected with the power supply voltage,
the driving end of the eleventh operation MOS tube is connected with the first end of the eleventh operation MOS tube, the first end of the eleventh operation MOS tube is connected with the second end of the eighth operation MOS tube, the second end of the eleventh operation MOS tube is connected with a signal ground,
the driving end of the twelfth operational MOS tube is connected with the first end of the eleventh operational MOS tube, the first end of the twelfth operational MOS tube is connected with the second end of the tenth operational MOS tube, and the second end of the twelfth operational MOS tube is connected with a signal ground.
Further, the seventh operation MOS transistor, the eighth operation MOS transistor, the ninth operation MOS transistor, and the tenth operation MOS transistor each include a P-type MOSFET transistor, the eleventh operation MOS transistor and the twelfth operation MOS transistor each include an N-type MOSFET transistor, a driving end of the N-type MOSFET transistor is a gate, a first end of the N-type MOSFET transistor is a drain, a second end of the N-type MOSFET transistor is a source, a driving end of the P-type MOSFET transistor is a gate, a first end of the P-type MOSFET transistor is a source, and a second end of the P-type MOSFET transistor is a drain.
Further, the first power tube, the second power tube, the first sampling tube, the second sampling tube, the third sampling tube and the fourth sampling tube all comprise N-type MOSFET tubes, the driving ends of the N-type MOSFET tubes are grids, the first ends of the N-type MOSFET tubes are drain electrodes, and the second ends of the N-type MOSFET tubes are source electrodes.
The inductive current sampling circuit provided by the invention collects current initial sampling signals under various control signals through the sampling module, not only comprises the current initial sampling signals under high-low side control signals, but also can collect forward and reverse currents, and can enable the working condition of each sampling tube to be always consistent with that of the main power tube when the sampling function is realized through a negative feedback structure, so that the collected current initial sampling signals are proportional to the preset sampling current, and the sampling precision can be effectively ensured.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention.
Fig. 1 is a schematic diagram of a prior art resistance sampling circuit.
Fig. 2 is a schematic diagram of a DCR sampling circuit in the prior art.
Fig. 3 is a schematic diagram of a MOSFET sampling circuit in the prior art.
Fig. 4 is a schematic diagram of an inductor current sampling circuit according to the present invention.
Fig. 5 is a schematic diagram of a test characteristic of current sampling by using the inductor current sampling circuit according to the present invention.
Fig. 6a is a layout diagram of an integrated device of the inductor current sampling circuit according to the present invention.
Fig. 6b is a layout diagram of another integrated device of the inductor current sampling circuit according to the present invention.
Detailed Description
It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict. The present invention will be described in detail below with reference to the embodiments with reference to the attached drawings.
In order to make those skilled in the art better understand the technical solution of the present invention, the technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It should be understood that the data so used may be interchanged as appropriate in order to facilitate the embodiments of the invention described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
In this embodiment, an inductor current sampling circuit is provided, and fig. 4 is a schematic circuit diagram of a circuit structure of an inductor current sampling circuit according to an embodiment of the present invention, as shown in fig. 4, including:
the sampling module 100 can collect current initial sampling signals under various control signals according to a preset proportion, wherein the current initial sampling signals include a forward current initial sampling signal under a high-side control signal, a forward current initial sampling signal under a low-side control signal, a reverse current initial sampling signal under the high-side control signal and a reverse current initial sampling signal under the low-side control signal;
and the operation module 200 is used for respectively performing operation processing on the current initial sampling signals under different control signals to obtain corresponding current sampling data.
It should be noted that the high-side control signal in the embodiment of the present invention may be specifically understood as a control signal of the gate driving end of the high-side power transistor, and when the control signal is at a high level, subsequent sampling is performed; the low-side control signal may be specifically understood as a control signal of the gate driving terminal of the low-side power transistor, and the subsequent sampling is performed only when the control signal is at a high level.
It should be understood that the inductor current sampling circuit in the embodiment of the present invention is capable of realizing forward and reverse current sampling under the condition of being compatible with the control signal of the high-low side power tube.
In the embodiment of the invention, the sampling module is used for collecting the initial current sampling signals under various control signals, the initial current sampling signals under high-low side control signals are included, forward and reverse currents can be collected, the working condition of each sampling tube is always consistent with that of the main power tube when the sampling function is realized through the negative feedback structure, and the collected initial current sampling signals are proportional to the preset sampling current, so that the sampling precision can be effectively ensured.
Specifically, as shown in fig. 4, the sampling module 100 includes a high-side sampling unit 110 and a low-side sampling unit 120, the high-side sampling unit 110 is connected with the low-side sampling unit 120,
the high-side sampling unit 110 is configured to collect current according to a preset proportion under the high-side control signal and obtain a forward current initial sampling signal under the high-side control signal and a reverse current initial sampling signal under the high-side control signal;
the low-side sampling unit 120 is configured to collect a current according to a preset proportion under the low-side control signal and obtain a forward current initial sampling signal under the low-side control signal and a reverse current initial sampling signal under the low-side control signal.
It should be understood that the high-side sampling unit 110 is capable of collecting forward and reverse currents according to a preset ratio, and the low-side sampling unit 120 is also capable of collecting forward and reverse currents according to a preset ratio.
In the embodiment of the present invention, as shown in fig. 4, the high-side sampling unit 110 includes: a first power tube M1, a first sampling tube M3 and a second sampling tube M4,
the driving end of the first power tube M1 is used for connecting a high-side control signal GH, the first end and the second end of the first power tube M1 are both connected to the operation module 200,
the driving end of the first sampling tube M3 is connected to a high-side control signal GH, the first end and the second end of the first sampling tube M3 are both connected to the operation module 200, the second end of the first sampling tube M3 is connected to the second end of the first power tube M1,
the driving end of the second sampling tube M4 is connected with the driving end of the first sampling tube M3, the first end and the second end of the second sampling tube M4 are both connected with the operation module 200, and the first end of the second sampling tube M4 is connected with the first end of the first power tube M1.
It should be noted that, since the first sampling tube M3 and the second sampling tube M4 are both held 1: n, and in combination with the virtual short and virtual disconnection characteristics of the operational amplifier in the operational module 200, the three-terminal voltages of the first sampling tube M3 and the second sampling tube M4 can be kept consistent with the three-terminal voltage of the first power tube M1, and the ratio of the sampling current to the inductor current is the same as the ratio of the sampling tube width to the length and the ratio of the power tube width to the length, both being 1: n, thereby helping to improve the current sampling accuracy under the high-side control signal.
In the embodiment of the present invention, the low-side sampling unit 120 includes: a second power tube M2, a third sampling tube M5 and a fourth sampling tube M6,
the driving terminal of the second power transistor M2 is configured to connect to a low-side control signal GL, the first terminal of the second power transistor M2 is connected to the operation module 200, the second terminal of the second power transistor M2 is connected to a signal ground PGND, and the first terminal of the second power transistor M2 is connected to the second terminal of the first power transistor M1,
the driving end of the third sampling tube M5 is connected with the driving end of the second power tube M2, the first end and the second end of the third sampling tube M5 are both connected with the operation module 200, and the first end of the third sampling tube M5 is connected with the first end of the second power tube M2,
the driving end of the fourth sampling tube M6 is connected to the driving end of the third sampling tube M5, the first end of the fourth sampling tube M6 is connected to the operation module 200, and the second end of the fourth sampling tube M6 is connected to the signal ground PGND.
It should be noted that, under the control of the low-side control signal GL, since the third sampling tube M5 and the fourth sampling tube M6 both maintain 1: n, and in combination with the virtual short and virtual disconnection characteristics of the operational amplifier in the operational module 200, the three-terminal voltages of the third sampling tube M5 and the fourth sampling tube M6 can be kept consistent with the three-terminal voltage of the second power tube M2, and the ratio of the sampling current to the inductor current is the same as the ratio of the sampling tube width to the length and the ratio of the power tube width to the length, both being 1: n, thereby helping to improve the current sampling accuracy under the high-side control signal.
In the embodiment of the present invention, each of the first power tube M1, the second power tube M2, the first sampling tube M3, the second sampling tube M4, the third sampling tube M5, and the fourth sampling tube M6 includes an N-type MOSFET, a driving end of the N-type MOSFET is a gate, a first end of the N-type MOSFET is a drain, and a second end of the N-type MOSFET is a source.
It should be further noted that, in the high-side sampling unit 110 and the low-side sampling unit 120, since the three-terminal voltages of the first sampling tube M3 and the second sampling tube M4 are kept consistent with the three-terminal voltage of the first power tube M1, and the three-terminal voltages of the third sampling tube M5 and the fourth sampling tube M6 are kept consistent with the three-terminal voltage of the second power tube M2, that is, there is no serial sampling resistor at the source of the sampling tube, the loss can be reduced, and the sampling accuracy can be improved.
Specifically, the operation module 200 includes a high-side sampling current operation unit 210 and a low-side sampling current operation unit 220,
the high-side sampling current operation unit 210 is configured to perform operation processing on the forward current initial sampling signal under the high-side control signal and the reverse current initial sampling signal under the high-side control signal, respectively, to obtain corresponding current sampling data,
the low-side sampling current arithmetic unit 220 is configured to perform arithmetic processing on the forward current initial sampling signal under the low-side control signal and the reverse current initial sampling signal under the low-side control signal, respectively, to obtain corresponding current sampling data.
Specifically, the high-side sampling current operation unit 210 includes: a first operational amplifier A1, a second operational amplifier A2, a first operational MOS transistor NM1, a second operational MOS transistor NM2, a third operational MOS transistor NM3, a fourth operational MOS transistor NM4, a fifth operational MOS transistor PM1, a sixth operational MOS transistor PM2, a first switch S1, a second switch S2, a third switch S3 and a fourth switch S4,
the positive phase input end SH1 of the first operational amplifier A1 is connected with the first end of the first sampling tube M3, the negative phase input end V1 of the first operational amplifier A1 is connected with the first end of the first power tube M1, two ends of the first switch S1 are respectively connected with the positive phase input end SH1 and the negative phase input end V1 of the first operational amplifier A1,
the driving end of the first operational MOS NM1 is connected to the output end of the first operational amplifier A1, the first end of the first operational MOS NM1 is connected to the first end of the first sampling tube M3, the second end of the first operational MOS NM1 is connected to the signal ground PGND, the two ends of the second switch S2 are respectively connected to the driving end of the first operational MOS NM1 and the signal ground PGND,
the driving end of the second operation MOS tube NM2 is connected with the driving end of the first operation MOS tube NM1, the first end of the second operation MOS tube NM2 is an output end IMON of the operation module, the second end of the second operation MOS tube NM2 is connected with a signal ground PGND,
the positive phase input end SH2 of the second operational amplifier A2 is connected to the second end of the second sampling tube M4, the negative phase input end SW of the second operational amplifier A2 is connected to the second end of the first power tube M1, two ends of the third switch S3 are respectively connected to the positive phase input end SH2 and the negative phase input end SW of the second operational amplifier A2,
the driving end of the third operational MOS NM3 is connected to the output end of the second operational amplifier A2, the first end of the third operational MOS NM3 is connected to the second end of the second sampling tube M4, the second end of the third operational MOS NM3 is connected to the signal ground PGND, two ends of the fourth switch S4 are respectively connected to the driving end of the third operational MOS NM3 and the signal ground PGND,
the driving end of the fourth operational MOS NM4 is connected to the driving end of the third operational MOS NM3, the second end of the fourth operational MOS NM4 is connected to a signal ground PGND,
the driving end and the second end of the fifth operation MOS transistor PM1 are both connected to the first end of the fourth operation MOS transistor NM4,
the driving end of the sixth operation MOS transistor PM2 is connected to the driving end of the fifth operation MOS transistor PM1, the first end of the sixth operation MOS transistor PM2 is connected to the first end of the fifth operation MOS transistor PM1, and the second end of the sixth operation MOS transistor PM2 is the operation module output end IMON.
In the embodiment of the present invention, the first operation MOS transistor NM1, the second operation MOS transistor NM2, the third operation MOS transistor NM3, and the fourth operation MOS transistor NM4 all include N-type MOSFET transistors, the fifth operation MOS transistor PM1 and the sixth operation MOS transistor PM2 all include P-type MOSFET transistors, a driving end of the N-type MOSFET transistor is a gate, a first end of the N-type MOSFET transistor is a drain, a second end of the N-type MOSFET transistor is a source, a driving end of the P-type MOSFET transistor is a gate, a first end of the P-type MOSFET transistor is a source, and a second end of the P-type MOSFET transistor is a drain.
Specifically, the low-side sampling current operation unit 220 includes: a third operational amplifier A3, a fourth operational amplifier A4, a seventh operational MOS transistor PM3, an eighth operational MOS transistor PM4, a ninth operational MOS transistor PM5, a tenth operational MOS transistor PM6, an eleventh operational MOS transistor NM5, a twelfth operational MOS transistor NM6, a fifth switch S5, a sixth switch S6, a seventh switch S7 and an eighth switch S8,
the non-inverting input end SL1 of the third operational amplifier A3 is connected to the first end of the fourth sampling tube M6, the inverting input end SW of the third operational amplifier A3 is connected to the first end of the second power tube M2, two ends of the fifth switch S5 are respectively connected to the non-inverting input end SL1 and the inverting input end SW of the third operational amplifier A3,
a driving end of the seventh operational MOS transistor PM3 is connected to an output end of the third operational amplifier A3, a second end of the seventh operational MOS transistor PM3 is connected to a first end of the fourth sampling transistor M6, two ends of the sixth switch S6 are respectively connected to an output end of the third operational amplifier A3 and a first end of the seventh operational MOS transistor PM3,
the driving end of the eighth operation MOS transistor PM4 is connected to the driving end of the seventh operation MOS transistor PM3, the first end of the eighth operation MOS transistor PM4 is connected to the first end of the seventh operation MOS transistor PM3,
a non-inverting input end SL2 of the fourth operational amplifier A4 is connected to the second end of the third sampling tube M5, an inverting input end of the fourth operational amplifier A4 is connected to the second end of the second power tube M2, two ends of the seventh switch S7 are respectively connected to the non-inverting input end SL2 and the inverting input end of the fourth operational amplifier A4,
the driving end of the ninth operation MOS transistor PM5 is connected to the output end of the fourth operational amplifier A4, the second end of the ninth operation MOS transistor PM5 is connected to the second end of the third sampling transistor M5, two ends of the eighth switch S8 are respectively connected to the output end of the fourth operational amplifier A4 and the first end of the ninth operation MOS transistor PM4,
the driving end of the tenth operation MOS transistor PM6 is connected to the driving end of the ninth operation MOS transistor PM5, the first end of the tenth operation MOS transistor PM6 is connected to the first end of the ninth operation MOS transistor PM5, the second end of the tenth operation MOS transistor PM6 is an operation module output end IMON,
a driving end of the eleventh operation MOS NM5 is connected to a first end of the eleventh operation MOS NM5, a first end of the eleventh operation MOS NM5 is connected to a second end of the eighth operation MOS PM4, a second end of the eleventh operation MOS NM5 is connected to a signal ground PGND,
the driving end of the twelfth operational MOS NM6 is connected to the first end of the eleventh operational MOS NM5, the first end of the twelfth operational MOS NM6 is connected to the second end of the tenth operational MOS PM6, and the second end of the twelfth operational MOS NM6 is connected to the signal ground PGND.
In an embodiment of the present invention, each of the seventh operation MOS transistor PM3, the eighth operation MOS transistor PM4, the ninth operation MOS transistor PM5, and the tenth operation MOS transistor PM6 includes a P-type MOSFET, each of the eleventh operation MOS transistor NM5 and the twelfth operation MOS transistor NM6 includes an N-type MOSFET, a driving end of the N-type MOSFET is a gate, a first end of the N-type MOSFET is a drain, a second end of the N-type MOSFET is a source, the driving end of the P-type MOSFET is a gate, the first end of the P-type MOSFET is a source, and the second end of the P-type MOSFET is a drain.
The operation principle of the inductor current sampling circuit according to the embodiment of the present invention is described in detail with reference to fig. 4.
As shown in fig. 4, for example, when the inductor current sampling circuit is applied to a BUCK topology (BUCK), the voltage V1 end is an input voltage VIN, a drain of the first power transistor M1 is connected to the input voltage VIN, a source of the first power transistor M1 is connected to a drain of the second power transistor M2 and one end of an inductor L, the other end of the inductor L is connected to an output terminal Vout, a gate of the first power transistor M1 is connected to a high-side control signal GH of the PWM, a source of the second power transistor M2 is connected to a signal ground PGND, a gate of the second power transistor M2 is connected to a low-side control signal GL of the PWM, one end of an output capacitor Cout is connected to the output terminal Vout, the other end of the output capacitor Cout is connected to a ground potential, one end of a load Rload is connected to the output terminal Vout, and the other end of the load Rload is connected to the signal ground.
The specific working principle is as follows: firstly, the first sampling tube M3 and the second sampling tube M4 are both kept 1: n, the third sampling tube M5 and the fourth sampling tube M6 both keep 1: n width to length ratio relationship; by utilizing the characteristics of operational amplifier 'virtual short' and 'virtual disconnection', the potentials of a positive phase input end SH1 and a negative phase input end V1 of a first operational amplifier A1 are equal, the potentials of a positive phase input end SH2 and a negative phase input end SW of a second operational amplifier A2 are equal, the potentials of a positive phase input end SL1 and a negative phase input end SW of a third operational amplifier A3 are equal, and the potentials of a positive phase input end SL2 and a negative phase input end of a fourth operational amplifier A4 are equal, so that the voltages of three grid source drain ends of each sampling tube and the corresponding power tube are consistent, and the proportion of sampling current to inductive current is the same as the proportion of the width-length ratio of the sampling tube and the proportion of the width-length ratio of the power tube, and the proportion of the sampling tube to the power tube is 1: n; a high-side negative sampling current IL/n in the third sampling tube M3 flows to a signal ground from SW through the first operation MOS tube NM1, and the first operation MOS tube NM1 and the second operation MOS tube NM2 convert the sampling current into an output current IMON through M times of proportional mirroring; similarly, a high-side positive sampling current IL/n in the second sampling tube M4 flows from the input voltage VIN to the signal ground through the third operation MOS tube NM3, and the sampling current is converted into an output current IMON through M times of proportional images of the third operation MOS tube NM3, the fourth operation MOS tube NM4, the fifth operation MOS tube PM1 and the sixth operation MOS tube PM 2; a low-side positive sampling current IL/n in the third sampling tube M5 flows to a SW point from a power voltage VDD through a ninth operation MOS tube PM5, and the ninth operation MOS tube PM5 and a tenth operation MOS tube PM6 convert the sampling current into an output current IMON (namely an output end of an operation module) through M times of proportional mirroring; the low-side negative sampling current IL/n in the fourth sampling tube M6 flows from the power supply voltage VDD to the signal ground through the seventh operation MOS transistor PM3, and the sampling current is converted into the output current IMON (IMON = mIL/n) through the M-fold proportional mirror images of the seventh operation MOS transistor PM3, the eighth operation MOS transistor PM4, the eleventh operation MOS transistor NM5, and the twelfth operation MOS transistor NM 6. The first operation MOS tube NM1, the third operation MOS tube NM3, the seventh operation MOS tube PM3 and the eleventh operation MOS tube PM5 respectively provide sampling paths for a high-side negative current, a high-side positive current, a low-side negative current and a low-side positive current, and compatible sampling of the positive and negative currents of the high-side and low-side power tubes of the switching power supply is achieved. It should be noted that, the positive and negative directions of the current of the sampling tube are referred to as the direction of the inductor current, and the direction of the inductor current from SW to Vout is referred to as the positive current.
As shown in fig. 5, in the embodiment of buck, under the PWM control signal, as the upper and lower power transistors are turned on alternately, IMON can proportionally reproduce the triangular wave inductor current on the corresponding time axis, and the dead time IMON output is 0.
As shown in fig. 6a and 6b, fig. 6a is a layout diagram of the inductor current sampling circuit integrated in the same base island, fig. 6b is a layout diagram of the inductor current sampling circuit integrated in two base islands, and the inductor current sampling circuit shown in fig. 4 adopts the layout diagram shown in fig. 6 b.
The embodiment of the invention adopts a full integration mode, and integrates the power tube, the sampling tube and the current operation circuit in the chip. Fig. 6a shows that the inductor current sampling circuits are all integrated in the same base island a, fig. 6b shows that the sampling modules in the inductor current sampling circuits are integrated in the base island b, the operation module is integrated in the base island c, the inductor current sampling circuit shown in fig. 4 adopts the layout form of fig. 6b, that is, the sampling modules and the operation module composed of the power tube and the proportional MOS sampling tube are respectively located in two different base islands, and SL1, SL1', SL2', SH1', SH2, and SH2' are respectively output to the sampling current operation circuit by the kelvin connection method, in both the schemes of fig. 6a and fig. 6b, the sampling tube is placed in the middle of the power tube for matching, so as to ensure the sampling precision.
It should be noted here that the current sampling and routing manner in the embodiment of the present invention employs kelvin connection, which effectively avoids the influence on the sampling accuracy due to loss in the routing process, for example, SH1 and SH1 'are both connected to the drain terminal of M3, but are introduced by two different input terminals of a current sampling operation circuit, where SH1 is connected to the operational amplifier input terminal and is in a high-impedance state, no current flows through the sampling tube M3, and the sampling current flows through SH1', which avoids the voltage inconsistency between the drain terminal of the sampling tube M3 and the drain terminal of the power tube M1 due to loss of the routing, so as to ensure the sampling accuracy.
It should be understood that the inductor current sampling current provided by the present invention is illustrated only by taking the BUCK topology shown in fig. 4 as an example, and is not limited to the BUCK topology type, and is also applicable to other topology types, for example, for other topology types such as BOOST, BUCK-BOOST, etc., which are well known to those skilled in the art, adaptive changes of the circuit can be implemented, and details are not described here.
In conclusion, the inductive current sampling circuit provided by the invention not only can be compatible with high-low side power MOS bidirectional current sampling, but also can reduce the loss due to the fact that a common source-level series sampling resistor in the MOSFET sampling technology is omitted, meanwhile, the working conditions of a proportional MOS sampling tube and three ends of a power tube are kept consistent, and no temperature coefficient exists in sampling, so that the sampling precision can be effectively improved. In addition, the inductive current sampling circuit provided by the invention is highly integrated, the system is small in size, no external sampling Pin is provided, the built-in power tube and the sampling tube are connected with the sampling current arithmetic circuit in a Kelvin mode, and the sampling precision is ensured.
It will be understood that the above embodiments are merely exemplary embodiments taken to illustrate the principles of the present invention, which is not limited thereto. It will be apparent to those skilled in the art that various modifications and improvements can be made without departing from the spirit and substance of the invention, and these modifications and improvements are also considered to be within the scope of the invention.
Claims (10)
1. An inductor current sampling circuit, comprising:
the sampling module can acquire current initial sampling signals under various control signals according to a preset proportion, wherein the current initial sampling signals include a forward current initial sampling signal under a high-side control signal, a forward current initial sampling signal under a low-side control signal, a reverse current initial sampling signal under the high-side control signal and a reverse current initial sampling signal under the low-side control signal;
and the operation module is used for respectively performing operation processing on the current initial sampling signals under different control signals to obtain corresponding current sampling data.
2. The inductor current sampling circuit of claim 1,
the sampling module comprises a high-side sampling unit and a low-side sampling unit, the high-side sampling unit is connected with the low-side sampling unit,
the high-side sampling unit is used for collecting current according to a preset proportion under a high-side control signal and obtaining a forward current initial sampling signal under the high-side control signal and a reverse current initial sampling signal under the high-side control signal;
the low-side sampling unit is used for collecting current according to a preset proportion under the low-side control signal and obtaining a forward current initial sampling signal under the low-side control signal and a reverse current initial sampling signal under the low-side control signal.
3. The inductor current sampling circuit according to claim 2, wherein the high-side sampling unit comprises: a first power tube, a first sampling tube and a second sampling tube,
the driving end of the first power tube is used for connecting a high-side control signal, the first end and the second end of the first power tube are both connected with the operation module,
the driving end of the first sampling tube is connected with a high-side control signal, the first end and the second end of the first sampling tube are both connected with the operation module, the second end of the first sampling tube is connected with the second end of the first power tube,
the driving end of the second sampling tube is connected with the driving end of the first sampling tube, the first end and the second end of the second sampling tube are both connected with the operation module, and the first end of the second sampling tube is connected with the first end of the first power tube.
4. The inductor current sampling circuit according to claim 3, wherein the low side sampling unit comprises: a second power tube, a third sampling tube and a fourth sampling tube,
the driving end of the second power tube is used for connecting a low-side control signal, the first end of the second power tube is connected with the operation module, the second end of the second power tube is connected with a signal ground, and the first end of the second power tube is connected with the second end of the first power tube,
the driving end of the third sampling tube is connected with the driving end of the second power tube, the first end and the second end of the third sampling tube are both connected with the operation module, the first end of the third sampling tube is connected with the first end of the second power tube,
the driving end of the fourth sampling tube is connected with the driving end of the third sampling tube, the first end of the fourth sampling tube is connected with the operation module, and the second end of the fourth sampling tube is connected with the signal ground.
5. The inductor current sampling circuit of claim 4, wherein the operational block comprises a high-side sampled current operational unit and a low-side sampled current operational unit,
the high-side sampling current arithmetic unit is used for respectively carrying out arithmetic processing on a forward current initial sampling signal under the high-side control signal and a reverse current initial sampling signal under the high-side control signal to obtain corresponding current sampling data,
the low-side sampling current arithmetic unit is used for respectively carrying out arithmetic processing on a forward current initial sampling signal under the low-side control signal and a reverse current initial sampling signal under the low-side control signal to obtain corresponding current sampling data.
6. The inductor current sampling circuit according to claim 5, wherein the high-side sampling current operation unit comprises: a first operational amplifier, a second operational amplifier, a first operational MOS transistor, a second operational MOS transistor, a third operational MOS transistor, a fourth operational MOS transistor, a fifth operational MOS transistor, a sixth operational MOS transistor, a first switch, a second switch, a third switch and a fourth switch,
the positive input end of the first operational amplifier is connected with the first end of the first sampling tube, the negative input end of the first operational amplifier is connected with the first end of the first power tube, the two ends of the first switch are respectively connected with the positive input end and the negative input end of the first operational amplifier,
the driving end of the first operational MOS tube is connected with the output end of the first operational amplifier, the first end of the first operational MOS tube is connected with the first end of the first sampling tube, the second end of the first operational MOS tube is connected with a signal ground, the two ends of the second switch are respectively connected with the driving end of the first operational MOS tube and the signal ground,
the driving end of the second operation MOS tube is connected with the driving end of the first operation MOS tube, the first end of the second operation MOS tube is the output end of the operation module, the second end of the second operation MOS tube is connected with a signal ground,
the positive input end of the second operational amplifier is connected with the second end of the second sampling tube, the negative input end of the second operational amplifier is connected with the second end of the first power tube, two ends of the third switch are respectively connected with the positive input end and the negative input end of the second operational amplifier,
the driving end of the third operational MOS tube is connected with the output end of the second operational amplifier, the first end of the third operational MOS tube is connected with the second end of the second sampling tube, the second end of the third operational MOS tube is connected with a signal ground, the two ends of the fourth switch are respectively connected with the driving end of the third operational MOS tube and the signal ground,
the driving end of the fourth operation MOS tube is connected with the driving end of the third operation MOS tube, the second end of the fourth operation MOS tube is connected with a signal ground,
the driving end and the second end of the fifth operation MOS tube are both connected with the first end of the fourth operation MOS tube,
the driving end of the sixth operation MOS tube is connected with the driving end of the fifth operation MOS tube, the first end of the sixth operation MOS tube is connected with the first end of the fifth operation MOS tube, the second end of the sixth operation MOS tube is the output end of the operation module, and the first end of the sixth operation MOS tube and the first end of the fifth operation MOS tube are both connected with a power supply voltage.
7. The inductor current sampling circuit according to claim 6, wherein the first, second, third and fourth operation MOS transistors each comprise an N-type MOSFET, the fifth and sixth operation MOS transistors each comprise a P-type MOSFET, the driving end of the N-type MOSFET is a gate, the first end of the N-type MOSFET is a drain, the second end of the N-type MOSFET is a source, the driving end of the P-type MOSFET is a gate, the first end of the P-type MOSFET is a source, and the second end of the P-type MOSFET is a drain.
8. The inductor current sampling circuit according to claim 5, wherein the low-side sampling current operation unit comprises: a third operational amplifier, a fourth operational amplifier, a seventh operational MOS transistor, an eighth operational MOS transistor, a ninth operational MOS transistor, a tenth operational MOS transistor, an eleventh operational MOS transistor, a twelfth operational MOS transistor, a fifth switch, a sixth switch, a seventh switch and an eighth switch,
the positive phase input end of the third operational amplifier is connected with the first end of the fourth sampling tube, the negative phase input end of the third operational amplifier is connected with the first end of the second power tube, two ends of the fifth switch are respectively connected with the positive phase input end and the negative phase input end of the third operational amplifier,
the driving end of the seventh operational MOS tube is connected with the output end of the third operational amplifier, the second end of the seventh operational MOS tube is connected with the first end of the fourth sampling tube, the two ends of the sixth switch are respectively connected with the output end of the third operational amplifier and the first end of the seventh operational MOS tube,
the driving end of the eighth operation MOS tube is connected with the driving end of the seventh operation MOS tube, the first end of the eighth operation MOS tube is connected with the first end of the seventh operation MOS tube, the first end of the eighth operation MOS tube and the first end of the seventh operation MOS tube are both connected with a power supply voltage,
the positive input end of the fourth operational amplifier is connected with the second end of the third sampling tube, the negative input end of the fourth operational amplifier is connected with the second end of the second power tube, two ends of the seventh switch are respectively connected with the positive input end and the negative input end of the fourth operational amplifier,
the driving end of the ninth operation MOS tube is connected with the output end of the fourth operation amplifier, the second end of the ninth operation MOS tube is connected with the second end of the third sampling tube, two ends of the eighth switch are respectively connected with the output end of the fourth operation amplifier and the first end of the ninth operation MOS tube,
the driving end of the tenth operation MOS tube is connected with the driving end of the ninth operation MOS tube, the first end of the tenth operation MOS tube is connected with the first end of the ninth operation MOS tube, the second end of the tenth operation MOS tube is the output end of the operation module, the first end of the tenth operation MOS tube and the first end of the ninth operation MOS tube are both connected with the power supply voltage,
the driving end of the eleventh operation MOS tube is connected with the first end of the eleventh operation MOS tube, the first end of the eleventh operation MOS tube is connected with the second end of the eighth operation MOS tube, the second end of the eleventh operation MOS tube is connected with a signal ground,
the driving end of the twelfth operational MOS tube is connected with the first end of the eleventh operational MOS tube, the first end of the twelfth operational MOS tube is connected with the second end of the tenth operational MOS tube, and the second end of the twelfth operational MOS tube is connected with a signal ground.
9. The inductor current sampling circuit according to claim 8, wherein the seventh operation MOS transistor, the eighth operation MOS transistor, the ninth operation MOS transistor and the tenth operation MOS transistor each include a P-type MOSFET transistor, the eleventh operation MOS transistor and the twelfth operation MOS transistor each include an N-type MOSFET transistor, the driving end of the N-type MOSFET transistor is a gate, the first end of the N-type MOSFET transistor is a drain, the second end of the N-type MOSFET transistor is a source, the driving end of the P-type MOSFET transistor is a gate, the first end of the P-type MOSFET transistor is a source, and the second end of the P-type MOSFET transistor is a drain.
10. The inductor current sampling circuit according to claim 4, wherein the first power transistor, the second power transistor, the first sampling transistor, the second sampling transistor, the third sampling transistor and the fourth sampling transistor each comprise an N-type MOSFET, a driving terminal of the N-type MOSFET is a gate, a first terminal of the N-type MOSFET is a drain, and a second terminal of the N-type MOSFET is a source.
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