CN111313670A

CN111313670A - BUCK converter and internal ripple compensation circuit thereof

Info

Publication number: CN111313670A
Application number: CN202010274832.8A
Authority: CN
Inventors: 朱亮
Original assignee: Shenzhen Yunxi Semiconductor Co ltd
Current assignee: Shenzhen Yunxi Semiconductor Co ltd
Priority date: 2020-04-09
Filing date: 2020-04-09
Publication date: 2020-06-19

Abstract

The invention provides a BUCK converter and an internal ripple compensation circuit thereof, comprising: at least two ripple compensation modules and a selection trigger module; the selection trigger module is respectively connected with a feedback node at the output side of the BUCK converter and the at least two ripple compensation modules, and the at least two ripple compensation modules are connected with one feedback node at the output side of the BUCK converter and the selection trigger module; the selection triggering module is used for: triggering a current ripple compensation module in the at least two ripple compensation modules to perform ripple compensation according to the output voltage of the BUCK converter; when the ripple compensation module is used as the current ripple compensation module to perform the ripple compensation, the ripple compensation module is configured to: and generating ripple compensation current matched with voltage ripples in the BUCK converter, and superposing the ripple compensation current to a feedback node of the output side of the BUCK converter.

Description

BUCK converter and internal ripple compensation circuit thereof

Technical Field

The invention relates to the field of converters, in particular to a BUCK converter and an internal ripple compensation circuit thereof.

Background

The BUCK converter is also called a step-down converter, and is a single-tube non-isolated direct current converter with output voltage smaller than input voltage. Compared with the traditional voltage mode and current mode, the BUCK converter based on the COT constant conduction time does not need an operational amplifier and loop compensation, so that the circuit is simpler and has higher response speed. However, the COT mode in the conventional sense needs a large output voltage ripple, so that an output capacitor needs to have a large ESR resistance, and if the ESR resistance of the output capacitor is small, subharmonic oscillation is caused, loop stability is affected, and applicability is limited.

Therefore, an internal ripple compensation circuit can be configured for the BUCK converter, and in the related art, the internal texture compensation circuit usually only adopts one way to perform texture compensation, which cannot meet the overall requirements of the circuit, for example, it is difficult to meet the compensation requirement of the full input range, and further, it is difficult to ensure the stability of the output voltage within the full input range.

Disclosure of Invention

The invention provides a BUCK converter and an internal ripple compensation circuit thereof, which aim to solve the problem that the comprehensive requirements of the circuit cannot be met by only adopting one mode to perform texture compensation.

According to a first aspect of the present invention, there is provided an internal ripple compensation circuit of a BUCK converter, the internal ripple compensation circuit comprising: at least two ripple compensation modules and a selection trigger module; the selection trigger module is respectively connected with a feedback node at the output side of the BUCK converter and the at least two ripple compensation modules, and the at least two ripple compensation modules are connected with one feedback node at the output side of the BUCK converter and the selection trigger module;

the selection triggering module is used for: triggering a current ripple compensation module in the at least two ripple compensation modules to perform ripple compensation according to the output voltage of the BUCK converter;

when the ripple compensation module is used as the current ripple compensation module to perform the ripple compensation, the ripple compensation module is configured to: generating ripple compensation current matched with voltage ripples in the BUCK converter, and superposing the ripple compensation current to a feedback node of the output side of the BUCK converter; wherein the process of generating the ripple compensation current by different ripple compensation modules is different.

Optionally, the internal ripple compensation circuit of the BUCK converter further includes a voltage ripple sampling module, where the voltage ripple sampling module includes a first filtering unit and a second filtering unit, and waveforms of open nodes in the BUCK converter can be filtered by the first filtering unit and the second filtering unit in sequence; the ripple compensation module is respectively connected with the first filtering unit and the second filtering unit so as to collect a first voltage filtered by the first filtering unit and a second voltage filtered by the second filtering unit; the voltage ripple is characterized by a difference between the first voltage and the second voltage;

when the ripple compensation module generates the ripple compensation current matched with the voltage ripple, the ripple compensation module is specifically used for:

forming a first intermediate voltage at two ends of the resistor with the target resistance value according to the first voltage to obtain a corresponding first current; the difference between the first voltage and the first intermediate voltage is a first voltage difference;

forming a second intermediate voltage at two ends of the resistor with the target resistance value according to the second voltage to obtain a corresponding second current, wherein the difference between the second voltage and the second intermediate voltage is a second voltage difference;

according to the first current and the second current, determining ripple compensation current matched with the voltage ripple;

superimposing the ripple compensation current to a feedback node of an output side of the BUCK converter;

in different ripple compensation modules, the first voltage difference is different, and the second voltage difference is also different; in the same ripple compensation module, the first voltage difference and the second voltage difference are the same.

Optionally, the ripple compensation current is a difference between the first current and the second current, the at least two ripple compensation modules include a first ripple compensation module and a second ripple compensation module, a first voltage difference and a second voltage difference in the first ripple compensation module are zero, and a first voltage difference and a second voltage difference in the second ripple compensation module are not zero.

Optionally, the at least two ripple compensation modules include a first ripple compensation module, and the first ripple compensation module includes a first resistor, a second resistor, a first PNP triode, a second PNP triode, a first P-type MOS transistor, a second P-type MOS transistor, a third P-type MOS transistor, a fourth P-type MOS transistor, a fifth P-type MOS transistor, a sixth P-type MOS transistor, a seventh P-type MOS transistor, a first N-type MOS transistor, a second N-type MOS transistor, a first NPN triode, a second NPN triode, and three first enable switches; the first resistor and the second resistor have the same resistance value;

the grids of the three first enabling switches are all connected with the selection trigger module; the grid electrode of the third P-type MOS tube and the grid electrode of the fourth P-type MOS tube are connected with a first enabling switch, the grid electrode of the fifth P-type MOS tube and the grid electrode of the sixth P-type MOS tube are connected with a second first enabling switch, and the grid electrode of the first N-type MOS tube and the grid electrode of the second N-type MOS tube are connected with a third first enabling switch; the three first enabling switches are connected to the selective triggering module to control the conduction of the third P-type MOS transistor, the fourth P-type MOS transistor, the fifth P-type MOS transistor, the sixth P-type MOS transistor, the first N-type MOS transistor and the second N-type MOS transistor when triggered by the selective triggering module; the base electrode of the first PNP triode is used for being connected with the first voltage, and the base electrode of the second PNP triode is used for being connected with the second voltage;

the first ends of the first P-type MOS tube, the second P-type MOS tube, the third P-type MOS tube and the fourth P-type MOS tube are connected with an analog power supply, the grids of the first P-type MOS tube, the second P-type MOS tube and the seventh P-type MOS tube are connected with each other, and the grid of the first P-type MOS tube is in short circuit with the second end; the second end of the second P-type MOS tube is connected with the emitting electrode of the first PNP triode, the base electrode of the first PNP triode is connected with the first filter capacitor so as to be connected with the first voltage, the collector electrode of the first PNP triode is connected with an analog ground, the emitting electrode of the first PNP triode is also connected with the base electrode of the first NPN triode, the collector electrode of the first PNP triode is connected with the second end of the third P-type MOS tube, and the emitting electrode of the first PNP triode is connected with the analog ground through the first resistor; the grid electrode of the third P-type MOS tube is in short circuit with the second end, the second end of the fourth P-type MOS tube is connected with the first end of the first N-type MOS tube, and the second end of the first N-type MOS tube is connected with the analog ground;

the fifth P-type MOS tube, the sixth P-type MOS tube and the seventh P-type MOS tube are connected with an analog power supply, the second end of the fifth P-type MOS tube is connected with the first end of the second N-type MOS tube, the second end of the second N-type MOS tube is connected with an analog ground, the second end of the sixth P-type MOS tube is connected with the collector electrode of the second NPN triode, the emitter electrode of the second NPN triode is connected with the analog ground through the second resistor, the second end of the seventh P-type MOS tube is connected with the base electrode of the second PNP triode and is connected with the second filter capacitor so as to be connected with the second voltage, and the emitter electrode of the second PNP triode is connected with the analog ground; the grid electrode of the second N-type MOS tube is in short circuit with the first end, and the grid electrode of the sixth P-type MOS tube is in short circuit with the second end;

the third P-type MOS transistor and the second P-type MOS transistor are one-to-one mirror image P-type MOS transistors, the first N-type MOS transistor and the second N-type MOS transistor are one-to-one mirror image N-type MOS transistors, and the fifth P-type MOS transistor and the sixth P-type MOS transistor are one-to-one mirror image P-type MOS transistors;

the first current of the first ripple compensation module refers to the current of the fourth P-type MOS tube, the second current of the first ripple compensation module refers to the current of the first N-type MOS tube, and a feedback node of the output side of the BUCK converter is connected between the second end of the fourth P-type MOS tube and the first end of the first N-type MOS tube to receive the ripple compensation current generated by the first ripple compensation module.

Optionally, the at least two ripple compensation modules include a second ripple compensation module, and the second ripple compensation module includes a third resistor, a fourth resistor, an eighth P-type MOS transistor, a ninth P-type MOS transistor, a tenth P-type MOS transistor, an eleventh P-type MOS transistor, a third N-type MOS transistor, a fourth N-type MOS transistor, a fifth N-type MOS transistor, a sixth N-type MOS transistor, a seventh N-type MOS transistor, a third NPN triode, a fourth NPN triode, a fifth NPN triode, a sixth NPN triode, and three first enable switches; the third resistor and the fourth resistor have the same resistance value;

the grids of the three second enabling switches are all connected with the selection trigger module; the grid electrode of the eighth P-type MOS tube and the grid electrode of the ninth P-type MOS tube are connected with a first second enable switch, the grid electrode of the tenth P-type MOS tube and the grid electrode of the eleventh P-type MOS tube are connected with a second enable switch, and the grid electrode of the third N-type MOS tube and the grid electrode of the fourth N-type MOS tube are connected with a third second enable switch; the three second enabling switches are all connected to the selective triggering module to control conduction of the eighth P-type MOS transistor, the ninth P-type MOS transistor, the tenth P-type MOS transistor, the eleventh P-type MOS transistor, the third N-type MOS transistor and the fourth N-type MOS transistor when triggered by the selective triggering module, a base of the third NPN triode is used for connecting the first voltage, and a base of the sixth NPN triode is used for connecting the second voltage;

a collector of the third NPN triode, a first end of the eighth P-type MOS transistor, and a first end of the ninth P-type MOS transistor are all connected to an analog power supply, the sixth N-type MOS transistor, the seventh N-type MOS transistor, and a gate of the fifth N-type MOS transistor are connected to each other, the gate of the sixth N-type MOS transistor is shorted to the first end, the gate of the seventh N-type MOS transistor is shorted to the second end, the first end of the seventh N-type MOS transistor is connected to an emitter of the third NPN triode, the second end of the seventh N-type MOS transistor and the second end of the sixth N-type MOS transistor are both connected to an analog ground, a base of the fourth NPN triode is connected to an emitter of the third NPN triode, and the emitter of the fourth NPN triode is connected to the analog ground through the third resistor;

the first end of the ninth P-type MOS tube is connected with an analog power supply, the second end of the ninth P-type MOS tube is connected with the first end of the third N-type MOS tube, the first end of the tenth P-type MOS tube is connected with the analog power supply, the second end of the tenth P-type MOS tube is connected with the first end of the fourth N-type MOS tube, and the second end of the fourth N-type MOS tube and the second end of the third N-type MOS tube are both connected to an analog ground;

a first end of the eleventh P-type MOS transistor is connected to an analog power supply, a second end of the eleventh P-type MOS transistor is connected to a collector of the fifth NPN triode, an emitter of the fifth NPN triode is connected to an analog ground through the fourth resistor, a base of the fifth NPN triode is connected to an emitter of the sixth NPN triode, a collector of the sixth NPN triode is connected to the analog power supply, an emitter of the sixth NPN triode is connected to a first end of the fifth N-type MOS transistor, and a second end of the fifth N-type MOS transistor is connected to the analog ground;

the eighth P-type MOS transistor and the ninth P-type MOS transistor are one-to-one mirror image P-type MOS transistors, the third N-type MOS transistor and the fourth N-type MOS transistor are one-to-one mirror image N-type MOS transistors, and the tenth P-type MOS transistor and the eleventh P-type MOS transistor are one-to-one mirror image P-type MOS transistors;

the first current of the second ripple compensation module refers to the current of the ninth P-type MOS tube, the second current of the second ripple compensation module refers to the current of the third N-type MOS tube, and a feedback node of the output side of the BUCK converter is connected between the second end of the ninth P-type MOS tube and the first end of the third N-type MOS tube to receive the ripple compensation current generated by the second ripple compensation module.

Optionally, the first filtering unit includes a first filtering resistor and a first filtering capacitor, and the second filtering unit includes a second filtering resistor and a second filtering capacitor;

the first end of the first filter resistor is connected with the switch node, the first end of the first filter capacitor is connected with the second end of the first filter resistor, the first end of the second filter resistor is connected with the second end of the first filter resistor, the second end of the second filter resistor is connected with the first end of the second filter capacitor, and the second end of the first filter capacitor and the second end of the second filter capacitor are both connected with an analog ground;

the ripple compensation module is connected with the first end of the first filter capacitor to collect the first voltage;

the ripple compensation module is connected with the first end of the second filter capacitor to stimulate the second voltage.

Optionally, the number of the ripple compensation modules is two, and the ripple compensation modules are respectively a first ripple compensation module and a second ripple compensation module; the selection triggering module is further connected with a feedback node on the input side of the BUCK converter, and the selection triggering module is specifically configured to:

if the difference between the output voltage and the input voltage of the BUCK converter exceeds a preset range, selecting the first ripple compensation module as the current ripple compensation module;

and if the difference between the output voltage and the input voltage of the BUCK converter does not exceed a preset range, selecting the second ripple compensation module as the current ripple compensation module.

Optionally, the selection trigger module includes a comparing unit and at least one transmission gate;

the transmission gate is respectively connected with a feedback node at the output side of the BUCK converter and a first input end of the comparator;

a second input end of the comparison unit is connected with a feedback node of the input side of the BUCK converter;

one output end of the comparison unit is connected with the first ripple compensation module, and the other output end of the comparison unit is connected with the second ripple compensation module;

the comparison unit is used for comparing the voltages of the first input end and the second input end and triggering the first ripple compensation module or the second ripple compensation module as the current ripple compensation module according to the comparison result.

Optionally, the comparing unit includes a comparator, a first inverter, a second inverter, a third inverter, and a fourth inverter;

the transmission gate is connected between a feedback node at the output side of the BUCK converter and the first input end of the comparator;

a second input end of the comparator is connected with a feedback node of the input side of the BUCK converter;

the output end of the comparator, the first phase inverter, the second phase inverter, the third phase inverter and the fourth phase inverter are sequentially connected;

one control end of the transmission gate is connected between the first phase inverter and the second phase inverter, the other control end of the transmission gate is connected between the second phase inverter and the third phase inverter, the first ripple compensation module is connected between the third phase inverter and the fourth phase inverter to be triggered by a signal output by the third phase inverter, and the second ripple compensation module is connected with an output end of the fourth phase inverter to be triggered by a signal output by the fourth phase inverter.

According to a second aspect of the present invention, there is provided a BUCK converter comprising the internal ripple compensation circuit according to the first aspect and its alternatives.

Optionally, the BUCK converter is a COT-controlled BUCK converter.

In the BUCK converter and the internal ripple compensation circuit thereof provided by the invention, the ripple compensation current corresponding to the ripple voltage is superposed to the feedback node (for example, a certain feedback resistor), so that a signal fed back by the feedback node can have information of the ripple voltage, which is beneficial to ensuring the working stability of the BUCK converter.

In a further aspect of the present invention, when the output voltage of the BUCK converter is low, the first ripple compensation module may be triggered to operate, and when the output voltage of the BUCK converter is high (for example, close to the input VIN voltage), the second ripple compensation module may be triggered to operate, which may ensure the stability of the output voltage within the full input range, for example, ripple compensation may be implemented within the operating range of 0V to VIN.

In addition, in the circuits of the first ripple compensation module and the second ripple compensation module provided by the optional scheme of the present invention, the compensated ripple compensation current is easy to calculate and generate, and the circuit structure is simpler than that of the prior art.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.

Fig. 1 is a first schematic diagram illustrating the configuration of an internal ripple compensation circuit according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of a portion of an output voltage detection control circuit of the BUCK converter according to an embodiment of the present invention;

fig. 3 is a second schematic diagram illustrating the configuration of the internal ripple compensation circuit according to an embodiment of the present invention;

FIG. 4 is a circuit diagram of a voltage ripple sampling circuit according to an embodiment of the present invention;

FIG. 5 is a waveform diagram of the switch node, the first voltage and the second voltage according to an embodiment of the present invention;

fig. 6 is a schematic circuit diagram of a first ripple compensation module and a second ripple compensation module according to an embodiment of the present invention;

FIG. 7 is a first schematic circuit diagram of a select trigger module according to an embodiment of the present invention;

fig. 8 is a second circuit diagram of the selection trigger module according to an embodiment of the present invention.

Description of reference numerals:

1-selecting a trigger module;

11-a comparison unit;

111-a first inverter;

112-a second inverter;

113-a third directioner;

114-a fourth inverter;

115-a comparator;

12-a transmission gate;

121-first transmission gate;

122-a second transmission gate;

2-a ripple compensation module;

21-a first ripple compensation module;

22-a second ripple compensation module;

3-a voltage ripple sampling module;

31-a first filtering unit;

32-a second filtering unit;

4-a comparator;

r11 — first filter resistance;

c1 — first filter capacitance;

r12 — first filter resistance;

c2 — second filter capacitance;

SW-switch node;

PM 1-first P type MOS tube;

PM 2-second P type MOS tube;

PM 3-third P type MOS tube;

PM 4-fourth P type MOS tube;

PM 5-fifth P type MOS tube;

PM 6-sixth P type MOS tube;

PM 7-seventh P type MOS tube;

PM 8-eighth P type MOS tube;

PM 9-ninth P type MOS tube;

PM 10-tenth P type MOS tube;

PM 11-eleventh P type MOS tube;

NM 1-first N type MOS tube;

NM 2-second N type MOS tube;

NM 3-third N type MOS tube;

NM 4-fourth N type MOS tube;

q11-a first PNP transistor;

q12-a second PNP transistor;

q21-a first NPN transistor;

q22-a second NPN transistor;

q23-third NPN triode;

q24-fourth NPN triode;

q25-fifth NPN triode;

q26-sixth NPN triode;

q31-first enable switch;

q32-second enable switch;

r21 — first resistance;

r22 — second resistance;

r23 — third resistance;

r24-fourth resistor.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The terms "first," "second," "third," "fourth," and the like in the description and in the claims, as well as in the drawings, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in sequences other than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

The technical solution of the present invention will be described in detail below with specific examples. The following several specific embodiments may be combined with each other, and details of the same or similar concepts or processes may not be repeated in some embodiments.

Fig. 1 is a first schematic diagram illustrating the configuration of an internal ripple compensation circuit according to an embodiment of the present invention; FIG. 2 is a schematic diagram of a portion of an output voltage detection control circuit in the BUCK converter according to an embodiment of the present invention.

Referring to fig. 1, the internal ripple compensation circuit includes: at least two ripple compensation modules 2 and a selection trigger module 1.

The selection trigger module 1 is connected with a feedback node of the output side of the BUCK converter, the at least two ripple compensation modules 2 are connected with the corresponding feedback nodes, the voltage of the corresponding feedback nodes can be collected, and the feedback nodes can be nodes between any two resistors of the output side.

In a specific implementation process, one or more feedback nodes for acquiring the voltage may be provided, and if one feedback node for acquiring the voltage is provided, the acquired voltage may be characterized as VOUT _ FB, and if two feedback nodes for acquiring the voltage are provided, the acquired voltage may be characterized as VOUT _ FB1 and VOUT _ FB 2. Regardless of whether one or more feedback nodes need to collect voltage, the collected voltage can be regarded as a representation of the output voltage, and further, when the BUCK converter controls the output, the BUCK converter can be controlled accordingly. Taking fig. 2 as an example, the output voltage detection control circuit may include a comparator 4, where the comparator 4 may output a PWM signal according to a comparison result between the collected voltage VOUT _ FB of the feedback node and the reference voltage VREF, and a switch in the BUCK converter may be turned on or off according to the PWM signal to control the output voltage.

In this embodiment, referring to fig. 1, the at least two ripple compensation modules 2 are connected to a feedback node on the output side of the BUCK converter and the selection trigger module 1.

The selection triggering module 2 is configured to: triggering a current ripple compensation module of the at least two ripple compensation modules for ripple compensation according to an output voltage of the BUCK converter (which may be characterized by a voltage sampled from a feedback node as referred to above).

When the ripple compensation module 2 is used as the current ripple compensation module to perform the ripple compensation, the ripple compensation module is configured to: generating ripple compensation current matched with voltage ripples in the BUCK converter, and superposing the ripple compensation current to a feedback node of the output side of the BUCK converter; wherein the process of generating the ripple compensation current by different ripple compensation modules is different.

In the above scheme, the ripple compensation current with matched ripple voltage is superimposed on the feedback node (e.g. at a certain feedback resistor), and then the signal fed back by the feedback node may have information of the ripple voltage, and taking fig. 2 as an example, the voltage VOUT _ FB fed back to the comparator 4 may have information of the ripple voltage, which may be beneficial to ensuring the stability of the operation of the BUCK converter.

Meanwhile, at least two ripple compensation modules and a selection trigger module are configured in the embodiment, and then the corresponding ripple compensation modules can be selectively triggered to perform ripple compensation according to actual circuit requirements, so that the situation that the overall requirements are difficult to meet due to the fact that only one ripple compensation module is adopted is avoided.

In addition, the circuit related to the embodiment can realize ripple compensation inside a chip without an external sampling circuit.

Fig. 3 is a second schematic diagram illustrating the configuration of the internal ripple compensation circuit according to an embodiment of the present invention; FIG. 4 is a circuit diagram of a voltage ripple sampling circuit according to an embodiment of the present invention; fig. 5 is a waveform diagram of the switch node, the first voltage and the second voltage according to an embodiment of the invention.

Referring to fig. 3 and 4, the internal ripple compensation circuit further includes a voltage ripple sampling module 3, the voltage ripple sampling module 3 includes a first filtering unit 31 and a second filtering unit 32, and a waveform of the switching node SW in the BUCK converter can be filtered by the first filtering unit 31 and the second filtering unit 32 in sequence.

Through the first filtering unit 31 and the second filtering unit 32, the required voltage ripple or the related information thereof can be acquired by the ripple compensation module, and any filtering unit that can realize the function does not depart from the description of the embodiment shown in fig. 3.

The ripple compensation module 2 is respectively connected to the first filtering unit 31 and the second filtering unit 32 to collect a first voltage VINP filtered by the first filtering unit 31 and a second voltage VINN filtered by the second filtering unit 32, where the voltage ripple may be represented by a difference between the first voltage and the second voltage.

In an implementation process, referring to fig. 4, the first filter unit 31 includes a first filter resistor R11 and a first filter capacitor C1, and the second filter unit 32 includes a second filter resistor R12 and a second filter capacitor C2.

A first end of the first filter resistor R11 is connected to the switch node SW, a first end of the first filter capacitor C1 is connected to a second end of the first filter resistor R11, a first end of the second filter resistor R12 is connected to a second end of the first filter resistor R11, a second end of the second filter resistor 12 is connected to a first end of the second filter capacitor C2, and a second end of the first filter capacitor C1 and a second end of the second filter capacitor C2 are both connected to an analog ground AGND;

the ripple compensation module 2 is connected with a first end of the first filter capacitor to collect the first voltage VINP; the ripple compensation module 2 is connected to a first end of the second filter capacitor to stimulate the second voltage VINN.

Furthermore, the waveform of the switch node SW, the waveform of the first voltage VINP filtered by the first filtering unit 31, and the waveform of the second voltage VINN filtered by the second filtering unit 32 may be as shown in fig. 5, and output voltage ripple information may be obtained through VINP-VINN, and as can be seen, the ripple compensation module 2 may respectively sample the first voltage VINP and the second voltage VINN, and further, in a specific calculation process, may not directly calculate VINP-VINN, but respectively convert it into a current, and further obtain a ripple compensation current associated with VINP-VINN.

In one embodiment, according to the first voltage, a first intermediate voltage is formed across the resistor with the target resistance value, and a corresponding first current is obtained; the difference between the first voltage and the first intermediate voltage is a first voltage difference;

In one embodiment, the ripple compensation current may be a difference between the first current and the second current, and in other embodiments, it is not excluded that other currents are introduced to participate in the calculation.

In one embodiment, the at least two ripple compensation modules include a first ripple compensation module 21 and a second ripple compensation module 22, a first voltage difference and a second voltage difference in the first ripple compensation module 21 are zero, and a first voltage difference and a second voltage difference in the second ripple compensation module 22 are not zero, for example, Vth + Vth may be mentioned later, but embodiments such as Vth + Vth, and the like are not excluded.

Fig. 6 is a schematic circuit diagram of the first ripple compensation module and the second ripple compensation module according to an embodiment of the invention.

Referring to fig. 6, the at least two ripple compensation modules 2 include a first ripple compensation module 21, where the first ripple compensation module 21 includes a first resistor R21, a second resistor R22, a first PNP transistor Q11, a second PNP transistor Q12, a first P-type MOS transistor PM1, a second P-type MOS transistor PM2, a third P-type MOS transistor PM3, a third P-type MOS transistor PM3, a fourth P-type MOS transistor PM4, a fifth P-type MOS transistor PM5, a sixth P-type MOS transistor PM6, a seventh P-type MOS transistor PM7, a first N-type MOS transistor NM1, a second N-type MOS transistor NM2, a first NPN transistor Q21, a second NPN transistor Q22, and three first enable switches Q31; the first resistor R21 and the second resistor R22 have the same resistance;

the gates of the three first enabling switches Q31 are all connected with the selection trigger module; the gate of the third P-type MOS transistor PM3 and the gate of the fourth P-type MOS transistor PM4 are connected to a first enable switch Q31, the gate of the fifth P-type MOS transistor PM5 and the gate of the sixth P-type MOS transistor PM6 are connected to a second first enable switch Q31, and the gate of the first N-type MOS transistor NM1 and the gate of the second N-type MOS transistor NM2 are connected to a third first enable switch Q31; the three first enable switches Q31 are all connected to the selective triggering module to control conduction of the third P-type MOS transistor PM3, the fourth P-type MOS transistor PM4, the fifth P-type MOS transistor PM5, the sixth P-type MOS transistor PM6, the first N-type MOS transistor NM1 and the second N-type MOS transistor NM2 when triggered by the selective triggering module, a base of the first PNP triode Q11 is used for accessing the first voltage, and a base of the second PNP triode Q12 is used for accessing the second voltage;

the first ends of the first P-type MOS transistor PM1, the second P-type MOS transistor PM2, the third P-type MOS transistor PM3 and the fourth P-type MOS transistor PM4 are connected with an analog power supply, the gates of the first P-type MOS transistor PM1, the second P-type MOS transistor PM2 and the seventh P-type MOS transistor PM7 are connected with each other, and the gate and the second end of the first P-type MOS transistor PM1 are in short circuit; a second end of the second P-type MOS transistor PM2 is connected to an emitter of the first PNP transistor Q11, a base of the first PNP transistor Q11 is connected to the first filter capacitor to receive the first voltage, a collector of the first PNP transistor Q11 is connected to an analog ground, an emitter of the first PNP transistor Q11 is further connected to a base of the first NPN transistor Q21, a collector of the first PNP transistor Q11 is connected to a second end of the third P-type MOS transistor PM3, and an emitter of the first PNP transistor Q11 is connected to the analog ground through the first resistor R21; the gate of the third P-type MOS transistor PM3 is shorted with the second end, the second end of the fourth P-type MOS transistor PM4 is connected to the first end of the first N-type MOS transistor NM1, the second end of the first N-type MOS transistor NM1 is connected to the analog ground, and the base of the first PNP triode is used for connecting the first voltage;

the fifth P-type MOS transistor PM5, the sixth P-type MOS transistor PM6 and the seventh P-type MOS transistor PM7 are connected to an analog power supply at a first end, the second end of the fifth P-type MOS transistor PM5 is connected to the first end of the second N-type MOS transistor NM2, the second end of the second N-type MOS transistor NM2 is connected to an analog ground, the second end of the sixth P-type MOS transistor PM6 is connected to the collector of the second NPN transistor Q22, the emitter of the second NPN transistor Q22 is connected to the analog ground through the second resistor R22, the second end of the seventh P-type MOS transistor PM7 is connected to the base of the second PNP transistor Q12 and connected to the second filter capacitor to connect the second voltage, and the emitter of the second PNP transistor Q12 is connected to the analog ground; the grid electrode of the second N-type MOS transistor NM2 is in short circuit with the first end, and the grid electrode of the sixth P-type MOS transistor PM6 is in short circuit with the second end;

the third P-type MOS transistor PM3 and the second P-type MOS transistor PM2 are one-to-one mirror image P-type MOS transistors, the first N-type MOS transistor NM1 and the second N-type MOS transistor NM2 are one-to-one mirror image N-type MOS transistors, and the fifth P-type MOS transistor PM5 and the sixth P-type MOS transistor PM6 are one-to-one mirror image P-type MOS transistors;

the first current of the first ripple compensation module 21 refers to the current of the fourth P-type MOS transistor PM4, the second current of the first ripple compensation module 21 refers to the current of the first N-type MOS transistor NM1, and the feedback node at the output side of the BUCK converter is connected between the second end of the fourth P-type MOS transistor PM4 and the first end of the first N-type MOS transistor NM1 to receive the ripple compensation current generated by the first ripple compensation module.

The circuit state of the first ripple compensation module 21 during operation will be described below, where Vth refers to the threshold voltage of a triode, and taking a PNP type triode made of a certain material as an example, when the emitter is greater than the base electrode by 0.3V, the triode can be turned on, where 0.3V is the threshold point, and the resistance value can be represented by using the reference numeral of a resistor.

When the first ripple compensation module 21 is in operation:

the voltage of the point A is VINP + Vth; the voltage at the point B is the voltage-Vth at the point A, namely VINP; therefore, the current of the path of the third P-type MOS transistor PM3 is VINP/R21, and further, since the fourth P-type MOS transistor PM4 and the third P-type MOS transistor PM3 are 1:1, the current is mirrored, so that the current of the fourth P-type MOS transistor PM4 is equal to the current of the third P-type MOS transistor PM3, and is VINP/R21;

the voltage at the point C is VINN + Vth, and the voltage at the point D is the voltage-Vth at the point C, namely VINN, so that the current of the sixth P-type MOS tube PM6 is VINN/R22, the fifth P-type MOS tube PM5 and the sixth P-type MOS tube PM6 are 1:1 current mirror images, meanwhile, the current of the first N-type MOS tube NM1 and the current of the second N-type MOS tube NM2 are 1:1 mirror images, the current of the first N-type MOS tube NM1, the current of the second N-type MOS tube PM2, the current of the fifth P-type MOS tube PM5 and the current of the sixth P-type MOS tube PM6 are equal to VINN/R22;

then, for point S1: the output current is the difference between the current of the fourth P-type MOS transistor PM4 and the current of the first N-type MOS transistor NM1, that is: VINP/R21-VINN/R22, and R21 ═ R22, if its resistance value is characterized by R, the current at S1 (i.e., ripple compensation current) is: (VINP-VINN)/R, namely: converting ripple voltage information obtained by the ripple sampling circuit into current information;

it can be seen that the process of generating the ripple compensation current can be characterized as: (VINP + Vth-Vth)/R- (VINN + Vth-Vth)/R ═ VINP-VINN)/R ═ IOUT. The IOUT refers to the current of ripple compensation current, and the magnitude of the current IOUT can be adjusted by adjusting the resistance value R of the resistor. Where (VINP + Vth-Vth) is the voltage applied to the resistor, which can be considered as the first intermediate voltage referred to above, and where (VINN + Vth-Vth) is the voltage applied to the resistor, which can be considered as the second intermediate voltage referred to above. Correspondingly, the first voltage difference and the second voltage difference are Vth-Vth equal to 0.

Furthermore, by connecting the point to a feedback node, the current can be added to the feedback resistor of VOUT _ FB again, and then the ripple information of the output voltage is obtained at VOUT _ FB, thereby controlling the stability of the output voltage.

Referring to fig. 6, the at least two ripple compensation modules include a second ripple compensation module 22, and the second ripple compensation module 22 includes a third resistor R23, a fourth resistor R24, an eighth P-type MOS transistor PM8, a ninth P-type MOS transistor PM9, a tenth P-type MOS transistor PM10, an eleventh P-type MOS transistor PM11, a third N-type MOS transistor NM3, a fourth N-type MOS transistor NM4, a fifth N-type MOS transistor NM5, a sixth N-type MOS transistor NM6, a seventh N-type MOS transistor NM7, a third NPN triode Q23, a fourth NPN triode Q24, a fifth NPN triode Q25, a sixth NPN triode Q26, and three first enable switches Q31; the third resistor R23 and the fourth resistor R24 have the same resistance;

the gates of the three second enabling switches Q32 are all connected with the selection trigger module; the gate of the eighth P-type MOS transistor PM8 and the gate of the ninth P-type MOS transistor PM9 are connected to a first second enable switch Q32, the gate of the tenth P-type MOS transistor PM10 and the gate of the eleventh P-type MOS transistor PM11 are connected to a second enable switch Q32, and the gate of the third N-type MOS transistor NM3 and the gate of the fourth N-type MOS transistor NM4 are connected to a third second enable switch Q32; the three second enabling switches Q32 are all connected to the selective triggering module to control the conduction of the eighth P-type MOS transistor PM8, the ninth P-type MOS transistor PM9, the tenth P-type MOS transistor PM10, the eleventh P-type MOS transistor PM11, the third N-type MOS transistor NM3 and the fourth N-type MOS transistor NM4 when triggered by the selective triggering module; the base of the third NPN triode Q23 is used for connecting the first voltage, and the base of the sixth NPN triode Q26 is used for connecting the second voltage;

a collector of the third NPN transistor Q23, a first end of the eighth P-type MOS transistor PM8, and a first end of the ninth P-type MOS transistor PM9 are all connected to an analog power supply, gates of the sixth N-type MOS transistor NM6, the seventh N-type MOS transistor NM7, and the fifth N-type MOS transistor NM5 are connected to each other, a gate of the sixth N-type MOS transistor NM6 is shorted to the first end, a gate of the seventh N-type MOS transistor NM7 is shorted to the second end, a first end of the seventh N-type MOS transistor NM7 is connected to an emitter of the third NPN transistor Q23, a second end of the seventh N-type MOS transistor NM7 and a second end of the sixth N-type MOS transistor NM6 are both connected to an analog ground, a base of the fourth NPN transistor Q24 is connected to an emitter of the third NPN transistor Q23, and an emitter of the fourth NPN transistor Q24 is connected to an analog resistance via the third NPN resistor 23;

a first end of the ninth P-type MOS transistor PM9 is connected to an analog power supply, a second end of the ninth P-type MOS transistor PM9 is connected to a first end of the third N-type MOS transistor NM3, a first end of the tenth P-type MOS transistor PM10 is connected to the analog power supply, a second end of the tenth P-type MOS transistor PM10 is connected to a first end of the fourth N-type MOS transistor NM4, and a second end of the fourth N-type MOS transistor NM4 and a second end of the third N-type MOS transistor NM3 are both connected to an analog ground;

a first end of the eleventh P-type MOS transistor PM11 is connected to an analog power supply, a second end of the eleventh P-type MOS transistor PM11 is connected to a collector of the fifth NPN transistor Q25, an emitter of the fifth NPN transistor Q25 is connected to an analog ground through the fourth resistor R24, a base of the fifth NPN transistor Q25 is connected to an emitter of the sixth NPN transistor Q26, a collector of the sixth NPN transistor Q26 is connected to the analog power supply, an emitter of the sixth NPN transistor Q26 is connected to a first end of the fifth N-type MOS transistor NM5, and a second end of the fifth N-type MOS transistor NM5 is connected to the analog ground;

the eighth P-type MOS transistor PM8 and the ninth P-type MOS transistor PM9 are one-to-one mirror image P-type MOS transistors, the third N-type MOS transistor NM3 and the fourth N-type MOS transistor NM4 are one-to-one mirror image N-type MOS transistors, and the tenth P-type MOS transistor PM10 and the eleventh P-type MOS transistor PM11 are one-to-one mirror image P-type MOS transistors;

the first current of the second ripple compensation module refers to the current of the ninth P-type MOS transistor PM9, the second current of the second ripple compensation module refers to the current of the third N-type MOS transistor NM3, and the feedback node at the output side of the BUCK converter is connected between the second end of the ninth P-type MOS transistor PM9 and the first end of the third N-type MOS transistor NM3 to receive the ripple compensation current generated by the second ripple compensation module.

When the second ripple compensation module 22 is in operation:

the voltage of the point E is VINP-Vth; the voltage at the point F is the voltage-Vth at the point E, namely VINP-Vth-Vth; therefore, the current of the eighth P-type MOS transistor PM8 is (VINP-Vth)/R23, and further, since the eighth P-type MOS transistor PM8 and the ninth P-type MOS transistor PM9 are 1:1, the current is mirrored, so that the current of the ninth P-type MOS transistor PM9 is equal to the current of the eighth P-type MOS transistor PM8, and is (VINP-Vth-Vth)/R23;

the voltage at the point G is VINN-Vth, the voltage at the point H is the voltage-Vth at the point G, namely VINN-Vth-Vth, so that the current of the eleventh P-type MOS tube PM11 is (VINN-Vth-Vth)/R24, the eleventh P-type MOS tube PM11 and the tenth P-type MOS tube PM10 are 1:1 current mirror images, meanwhile, the current of the third N-type MOS tube NM3, the current of the fourth N-type MOS tube NM4, the current of the tenth P-type MOS tube PM10 and the current of the eleventh P-type MOS tube PM11 are equal to each other and are (VINN-Vth-Vth)/R24 through the 1:1 mirror images of the third N-type MOS tube NM3 and the fourth N-type MOS tube NM 4;

then, for point S2: the output current is the difference value between the current of the ninth P-type MOS transistor PM9 and the current of the third N-type MOS transistor NM3, that is: VINP/R23-VINN/R24, and R23 ═ R24 ═ R21 ═ R22, if its resistance value is characterized as R, the current at point S2 is: (VINP-VINN)/R, namely: the ripple voltage information obtained by the ripple sampling circuit is converted into current information, and then the current can be superposed to the VOUT _ FB feedback resistor by connecting the point to a feedback node, so that the VOUT _ FB can obtain the ripple information of the output voltage, and the stability of the output voltage is controlled.

It can be seen that the process of generating the ripple compensation current can be characterized as: (VINP-Vth)/R- (VINN-Vth)/R ═ VINP-VINN/R ═ IOUT. The IOUT refers to ripple compensation current, and the magnitude of the current IOUT can be adjusted by adjusting the resistance value R of the resistor. Where (VINP-Vth) is the voltage applied to the resistor, which can be considered as the first intermediate voltage referred to above, and where (VINN-Vth) is the voltage applied to the resistor, which can be considered as the second intermediate voltage referred to above. Correspondingly, the first voltage difference and the second voltage difference are Vth + Vth.

In addition, in the above-described circuit, of the first enable switch Q31 and the second enable switch Q32, the first enable switch Q31 and the second enable switch Q32 connected to the analog power source may employ P-type MOS transistors, and the first enable switch Q31 and the second enable switch Q32 connected to the analog ground may employ N-type MOS transistors.

The first ripple compensation module 21 can be applied when the output voltage is small, and the second ripple compensation module 22 can be applied when the output voltage is large (for example, when the output voltage is close to the input voltage).

In the circuits of the first ripple compensation module and the second ripple compensation module, the compensated ripple compensation current is easy to calculate and generate, and the circuit structure is simpler than that of the prior art.

Meanwhile, in the ripple compensation module, the first voltage and the second voltage are input by using the triode, compared with the prior art, the ripple compensation circuit is usually input by using a MOS transistor, and at this time, the common-mode input voltage range of the circuit determines that the ripple compensation circuit cannot work when the output voltage of the BUCK converter is close to the input voltage, so that the ripple compensation module cannot be applied to the BUCK converter with a large duty ratio. In contrast, the ripple compensation module in the above embodiment is suitable for such a situation, and can ensure stability in the full voltage range.

In other embodiments of the present embodiment, an embodiment with three or more ripple compensation modules is not excluded, for example, in other ripple compensation modules, other manners similar to fig. 6 may also be adopted, and the procedures may be, for example, (VINP-Vth)/R- (VINN-Vth)/R ═ i (VINP-VINN)/R ═ IOUT, (VINP + Vth)/R- (VINN + Vth)/R ═ i (VINP-VINN)/R ═ IOUT, and the like, and the above procedures may be implemented by configuring corresponding triodes, MOS transistors, current mirrors, and the like.

FIG. 7 is a first schematic circuit diagram of a select trigger module according to an embodiment of the present invention; fig. 8 is a second circuit diagram of the selection trigger module according to an embodiment of the present invention.

Referring to fig. 7 and fig. 8 in combination with fig. 6, in one embodiment, the number of the ripple compensation modules 2 is two, which are the first ripple compensation module 21 and the second ripple compensation module 22 described above; the selection triggering module 1 is further connected to a feedback node on the input side of the BUCK converter, and the selection triggering module 1 is specifically configured to:

The output voltage of the BUCK converter can be characterized by the voltage VIN _ FB of the feedback node on the output side, and the output voltage of the BUCK converter can be characterized by the voltage VIN _ FB of the feedback node on the input side.

In the specific implementation process, please refer to fig. 7 and 8, the selection triggering module 1 includes a comparing unit 11 and at least one transmission gate 12; the number of the transmission gates 12 may be one as shown in fig. 7, or two as shown in fig. 8, and if the number of the transmission gates 12 is two, the transmission gates are the first transmission gate 121 and the second transmission gate 122, respectively.

The transmission gate 12 is respectively connected with a feedback node at the output side of the BUCK converter and a first input end of the comparison unit; a second input end of the comparison unit 11 is connected with a feedback node of the input side of the BUCK converter; one output end of the comparing unit 11 is connected to the first ripple compensating module 21, and the other output end is connected to the second ripple compensating module 22.

The comparison unit is configured to compare voltages of the first input terminal and the second input terminal, and trigger the first ripple compensation module 21 or the second ripple compensation module 22 as the current ripple compensation module according to a comparison result.

Since the output voltage of the BUCK converter should be smaller than the input voltage, the difference between the output voltage and the input voltage is larger than a predetermined range, which means that the output voltage is smaller than the input voltage and the output voltage is at a relatively lower voltage, and the difference between the output voltage and the input voltage is smaller than the predetermined range, which means that the output voltage is smaller than the input voltage and the output voltage is at a relatively higher voltage, for example, a voltage close to the input voltage. Furthermore, different ripple compensation modules can be triggered to work under different output voltages through the comparison unit.

It can be seen that the embodiments shown in fig. 7 and 8 can accurately select the matched ripple compensation module to work based on the relationship between the output voltage and the input voltage, and meet the requirement of the full voltage range.

In one implementation, referring to fig. 7, the comparing unit 11 includes a comparator 115, a first inverter 111, a second inverter 112, a third inverter 113, and a fourth inverter 114.

The transmission gate 12 is connected between a feedback node on the output side of the BUCK converter and a first input terminal of the comparator 115; the first input terminal may be a non-inverting input terminal.

The second input terminal of the comparator 115 is connected to the feedback node of the input side of the BUCK converter, which may correspond to the voltage VOUT _ FB (or VOUT _ FB1, VOUT _ FB2), and the second input terminal thereof may be an inverting input terminal.

The output end of the comparator 115, the first inverter 111, the second inverter 112, the third inverter 113, and the fourth inverter 114 are sequentially connected.

One control terminal of the transmission gate 12 is connected between the first inverter 111 and the second inverter 112, and the other control terminal is connected between the second inverter 112 and the third inverter 113, which can be characterized as a C terminal and a

And (4) an end.

The first ripple compensation module 21 is connected between the third inverter 113 and the fourth inverter 114 to be triggered by a signal ENH1 output by the third inverter 113, and the second ripple compensation module 22 is connected to the output end of the fourth inverter 114 to be triggered by a signal ENH2 output by the fourth inverter 114.

In another embodiment, referring to fig. 8, the number of the transmission gates 12 is two, and the two transmission gates are the first transmission gate 121 and the second transmission gate 122 respectively.

The first transmission gate 121 is connected between the feedback node of the output side of the BUCK converter and the first input terminal of the comparator, and the second transmission gate 122 is also connected between the feedback node of the output side of the BUCK converter and the first input terminal of the comparator.

The first transmissionFirst control terminal (e.g. C terminal or)

Terminal) is connected between the third inverter 113 and the fourth inverter 114, a second control terminal is connected to the output terminal of the fourth inverter 114, a second control terminal (e.g., terminal) of the second transmission gate

Terminal or C terminal) is connected between the third inverter 113 and the fourth inverter 114, and the first control terminal is connected to the output terminal of the fourth inverter 114, it can be seen that the first control terminal of the first transmission gate 121 and the second control terminal of the second transmission gate 122 are connected at the same position, and the second control terminal of the first transmission gate 121 and the first control terminal of the second transmission gate 122 are connected at the same position.

The first transmission gate and the second transmission gate are connected to different feedback nodes, and for example, as shown in fig. 8, the feedback node with the voltage VOUT _ FB1 and the feedback node with the voltage VOUT _ FB2 can be connected respectively.

In addition, except that different ripple compensation modules 2 are selected based on the output voltage and the input voltage, in other schemes, different ripple compensation modules 2 can be selected to work by comparing the output voltage with a preset threshold value, and different ripple compensation modules 2 can be selected to work by combining other factors, for example, the ripple compensation modules 2 can be automatically selected to perform ripple compensation by combining factors such as time and environment, so that actual requirements are met.

In summary, in the BUCK converter and the internal ripple compensation circuit thereof provided in this embodiment, the ripple compensation current corresponding to the ripple voltage is superimposed on the feedback node (e.g., at a certain feedback resistor), so that a signal fed back by the feedback node may have information of the ripple voltage, which is beneficial to ensuring the stability of the BUCK converter in operation.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. An internal ripple compensation circuit of a BUCK converter, comprising: at least two ripple compensation modules and a selection trigger module; the selection trigger module is respectively connected with a feedback node at the output side of the BUCK converter and the at least two ripple compensation modules, and the at least two ripple compensation modules are connected with one feedback node at the output side of the BUCK converter and the selection trigger module;

2. The internal ripple compensation circuit of the BUCK converter according to claim 1, further comprising a voltage ripple sampling module, wherein the voltage ripple sampling module includes a first filtering unit and a second filtering unit, and a waveform of an open joint in the BUCK converter can be filtered by the first filtering unit and the second filtering unit in sequence; the ripple compensation module is respectively connected with the first filtering unit and the second filtering unit so as to collect a first voltage filtered by the first filtering unit and a second voltage filtered by the second filtering unit; the voltage ripple is characterized by a difference between the first voltage and the second voltage;

3. The internal ripple compensation circuit of the BUCK converter according to claim 2, wherein the ripple compensation current is a difference between the first current and the second current, the at least two ripple compensation modules include a first ripple compensation module and a second ripple compensation module, a first voltage difference and a second voltage difference in the first ripple compensation module are zero, and a first voltage difference and a second voltage difference in the second ripple compensation module are not zero.

4. The internal ripple compensation circuit of the BUCK converter according to claim 3, wherein the at least two ripple compensation modules include a first ripple compensation module, the first ripple compensation module including a first resistor, a second resistor, a first PNP triode, a second PNP triode, a first P-type MOS transistor, a second P-type MOS transistor, a third P-type MOS transistor, a fourth P-type MOS transistor, a fifth P-type MOS transistor, a sixth P-type MOS transistor, a seventh P-type MOS transistor, a first N-type MOS transistor, a second N-type MOS transistor, a first NPN triode, a second NPN triode, and three first enable switches; the first resistor and the second resistor have the same resistance value;

5. The internal ripple compensation circuit of the BUCK converter according to claim 3, wherein the at least two ripple compensation modules include a second ripple compensation module, the second ripple compensation module including a third resistor, a fourth resistor, an eighth P-type MOS transistor, a ninth P-type MOS transistor, a tenth P-type MOS transistor, an eleventh P-type MOS transistor, a third N-type MOS transistor, a fourth N-type MOS transistor, a fifth N-type MOS transistor, a sixth N-type MOS transistor, a seventh N-type MOS transistor, a third NPN triode, a fourth NPN triode, a fifth NPN triode, a sixth NPN triode, and three first enable switches; the third resistor and the fourth resistor have the same resistance value;

6. The internal ripple compensation circuit of the BUCK converter according to any one of claims 2 to 5, wherein the first filter unit includes a first filter resistor and a first filter capacitor, and the second filter unit includes a second filter resistor and a second filter capacitor;

7. The internal ripple compensation circuit of the BUCK converter according to any one of claims 1 to 5, wherein the number of the ripple compensation modules is two, namely a first ripple compensation module and a second ripple compensation module; the selection triggering module is further connected with a feedback node on the input side of the BUCK converter, and the selection triggering module is specifically configured to:

8. The internal ripple compensation circuit of the BUCK converter according to claim 7, wherein the selection trigger module includes a comparison unit and at least one transmission gate;

the transmission gate is respectively connected with a feedback node at the output side of the BUCK converter and a first input end of the comparison unit;

9. The internal ripple compensation circuit of the BUCK converter according to claim 8, wherein the comparison unit includes a comparator, a first inverter, a second inverter, a third inverter, and a fourth inverter;

10. A BUCK converter, characterized by comprising an internal ripple compensation circuit according to any one of claims 1 to 9.