CN113534884B - Circuit for sampling current of MOSFET power tube with low power consumption - Google Patents
Circuit for sampling current of MOSFET power tube with low power consumption Download PDFInfo
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- CN113534884B CN113534884B CN202110912742.1A CN202110912742A CN113534884B CN 113534884 B CN113534884 B CN 113534884B CN 202110912742 A CN202110912742 A CN 202110912742A CN 113534884 B CN113534884 B CN 113534884B
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is dc
- G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
- G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
- G05F3/26—Current mirrors
- G05F3/262—Current mirrors using field-effect transistors only
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Abstract
The invention discloses a circuit for sampling MOSFET power tube current with low power consumption, which comprises: amplifier 1 and sampling tube M 1 Power tube M 0 And MOS transistor M 2 MOS transistor M 3 And a voltage dividing resistor R 5 A voltage dividing resistor R 6 Divider resistor R 5 And a voltage dividing resistor R 6 Is connected in series to the power tube M 0 Between the source and the drain, a voltage dividing resistor R 5 And a voltage dividing resistor R 6 The common contact is connected with the positive input end of the amplifier 1; MOS transistor M 3 And MOS tube M 2 A common gate and a common source to form a current mirror, so that the sampling tube M 1 The original sampling current is redistributed, most of the sampling current can return to output and become output current, a small part of the sampling current flows into the ground through the sampling resistor, and the power consumption caused by the part of the current can be adjusted by adjusting the proportion of the voltage dividing resistor and the MOS transistor M 3 And MOS transistor M 2 The proportion of the current mirror is used for achieving the purpose of reducing the sampling power consumption; when the area ratio of the power tube to the sampling tube is relatively small, for example: the MOSFET power tube is designed by adopting a separated device process, and the structure is most suitable for being adopted.
Description
Technical Field
The invention relates to an electronic component, a semiconductor and an integrated circuit, in particular to a circuit for sampling MOSFET power tube current with low power consumption.
Background
In the design of a DC/DC converter, sampling the current of a MOSFET power tube is essential regardless of which control method is used, for example: under valley bottom current and peak current mode, need the electric current of power tube and last power tube under every cycle collection respectively to combine corresponding ramp compensation, form the current ramp, the current ramp intersects with transconductance amplifier's output, produces the PWM signal, the switch of control power tube, the slope of current ramp needs accurate control in the within range of setting for, just can guarantee control loop's stability, for example: in peak current mode, the ramp-compensated rising slope (M) and the sampled inductor current falling slope (M) 2 ) The following relationship needs to be satisfied:
the control loop can be stabilized, where D represents the duty cycle.
If the current sampling deviates from the designed value too high, which is equivalent to insufficient slope compensation, subharmonic oscillation occurs; on the contrary, if the current sampling deviates from the design value and is too low, the slope of the synthesized current ramp wave mainly consists of slope compensation, the control mode is changed into a voltage mode, and the zero pole in the loop cannot be correctly compensated by the frequency compensation designed according to the current mode, so that unstable oscillation is caused, and therefore, accurate current sampling is the basis for keeping the stability of the DC/DC converter.
FIG. 1 is a block diagram of a current sample using an exemplary top power transistor, including a power transistor M 0 Sampling tube M 1 Amplifier 1, resistor R 4 And P type MOS tube M 2 Power tube M 0 The power tube sampling device can be an upper power tube or a lower power tube, and selects a proper power tube for sampling according to different control modes.
When the inductive current flows through the power tube M 0 The current of which needs to be sampled, a sampling tube M 1 And power tube M 0 Is of the same type except that the size area ratio power tube M 0 Small, sampling tube M 1 And power tube M 0 One of the common gate, source or drain is also connected together, and the other, unconnected, is held at the same potential by the action of the amplifier 1; for example: sampling the N-type upper power tube in figure 1, sampling tube M 1 And power M 1 Transistor common grid and drain, power transistor M 0 Is connected to the positive input end of the amplifier 1, and the output of the amplifier 1 is connected with a P-type MOS tube M 2 Grid of (2), sampling tube M 1 Source electrode and MOS tube M 2 Are connected together to the inverting input of an amplifier 1, the amplifier 1 and a MOS transistor M 2 Forming a complete negative feedback control loop, under the action of which the sampling tube M 1 And power tube M 0 The source electrode of the power tube M is kept at the same voltage 0 And a sampling tube M 1 When the transistor is turned on, the electrical characteristic between the drain and the source is equivalent to a resistance, the voltage difference between the drain and the source divided by the resistance is equal to the current flowing between the two poles, and since the voltage difference between the drain and the source of the two transistors is equal, the current flowing through each transistor is in an inverse relationship with the equivalent resistance, for example: power tube M 0 And a sampling tube M 1 The equivalent resistance ratio of (a) is 1: N,
R 1 ＝N*R 0 ，
R 0 representative power tube M 0 Equivalent resistance of R 1 Sampling tube M 1 Then the power tube M 0 And a sampling tube M 1 The current ratio of (a) to (b) is N:1, i.e.:
I SMPL ＝I OUT /N
power tube M 0 And a sampling tube M 1 The equivalent resistance of (a) is not a fixed value and is affected by external factors, such as: the resistance value decreases with the increase of the voltage difference between the gate and the source and increases with the increase of the ambient temperature, but the percentage of the effect of these changes on the resistance value is the same, so the ratio of the resistance values of the two transistors can be kept constant, and the ratio of the currents is also kept constant, the ratio is determined by the respective areas, the larger the area is, the smaller the resistance value is, and finally, the power transistor M and the transistor M are connected 0 The sampling current with the current kept in a fixed proportion can be converted into sampling voltage through a resistor for processing by a downstream circuit.
Power tube M 0 The self-consumed power during working is as follows:
P M0 ＝(V IN -V OUT )*I OUT
the power consumed to sample this current is:
P SAMPLE ＝V IN *I OUT /N
sampling current from V IN Passing through a sampling tube M 1 MOS transistor M 2 And a sampling resistor R 4 Up to ground, the power consumption required for sampling is not just the sampling tube M 1 But the consumption of the sample current over the entire path if the power transistor M 0 By means of integrated circuit process design, sampling tube M 1 The sampling current has great flexibility, and is usually easy to realize from tens of ohms to thousands of ohms, so that a great sampling proportion can be freely selected according to the requirement of power consumption, a very small sampling current is obtained, and the sampling power consumption is reduced, for example: power tube M 0 When the on-resistance of (2) is 100M Ω and N is 10000, M is 1 Has an on-resistance of 1000 omega at V IN ＝5V，I OUT When 1A is satisfied, M 0 The power consumed is 100mW, the extra power consumption caused by sampling is 0.5mW, i.e. 0.5%,however, the power transistor M designed by the integrated circuit technology 0 The structure is complicated, for example: the 20V withstand voltage power LDMOS (Lateraly Double-Diffused MOSFET) under the current 0.18um process needs 18 layers of light masks to be manufactured, and the power tube M is used for better performance and more competitive cost at present 0 Process designs for separating semiconductor devices are often used, for example: power tube M with 20V withstand voltage 0 Only 5 layers of light masks are needed under the process of separating devices, the cost advantage is obvious, and the sampling tube M 1 Needs and power tube M 0 The same process is used to ensure matching of the various electrical properties, and therefore, the sampling tube M 1 And a power tube M 0 On the same Wafer (Wafer), the control circuit must be designed by using integrated circuit technology, another Wafer is needed, and when packaging, the dies (Die) from the two wafers are inevitably packaged together, as shown in fig. 2, the power tube M 0 And a sampling tube M 1 The source electrodes of (a) are connected to the control circuit by bonding wires, which require bonding pads (Bond Pad) with a size proportional to the wire diameter of the bonding wires, for example: a 1.2mil (═ 30.48um) wire diameter copper wire requires a 90um x 90um pad. The size of the bonding pad cannot be larger than that of the source electrode of the MOSFET, because then a large free area is left under the bonding pad, thereby reducing the sample Density (Pattern Density) of the source electrode and affecting the electrical characteristics thereof, i.e. the sampling tube M 1 Is limited by the size of the pad, for example: power tube M with withstand voltage of 20V shown in FIG. 3 0 The equivalent resistance of (1) is 15M omega, and the power tube M 0 And a sampling tube M 1 Is about 64 at V IN ＝5V，I OUT When 1A, the power tube M 0 The consumed power is 15mW, the extra power consumption caused by sampling is 78mW, and the power consumption is higher than that of the power tube M 0 Is also large!
Disclosure of Invention
Conventional current sampling methods generate a large amount of power consumption because the sampled current flows from the input stream to ground. Although the sampling current is small relative to the output current, the voltage difference on the path is large, resulting in large sampling power consumption. Excessive sampling power consumption can reduce the overall efficiency of the system, and even trigger thermal protection, which affects the normal operation of the system, so that the sampling power consumption is reduced, or the sampling current is reduced, or the voltage difference on the path is reduced. The structure for sampling the current of the MOSFET power tube with low power consumption provided by the invention starts from the two aspects, realizes low power consumption sampling, and gets rid of the limitation of the size ratio of the power tube and the sampling tube.
The technical scheme adopted by the invention is as follows: the method comprises the following steps: amplifier 1 and sampling tube M 1 Power tube M 0 And MOS transistor M 2 Sampling tube M 1 And a power tube M 0 Common grid, sampling tube M 1 And a power tube M 0 Common drain for inputting V IN Voltage, sampling tube M 1 The source electrode of the MOS transistor is a sampling electrode, the sampling electrode and the MOS transistor M 2 Connected and commonly connected to the inverting input terminal of the amplifier 1, and the output terminal of the amplifier 1 is connected with the MOS transistor M 2 Grid of (3), MOS transistor M 2 The output end is connected with a sampling resistor R 4 (ii) a Power tube M 0 Is an output stage for outputting V OUT A voltage; further comprising: MOS transistor M 3 A voltage dividing resistor R 5 A voltage dividing resistor R 6 Divider resistor R 5 And a voltage dividing resistor R 6 Is connected in series to the power tube M 0 Between the source and the drain, a voltage dividing resistor R 5 And a voltage dividing resistor R 6 The common contact is connected with the positive input end of the amplifier 1; MOS transistor M 3 Drain electrode of the MOS transistor M is connected with the output electrode 3 And MOS transistor M 2 Common gate and common source, MOS transistor M 3 And MOS transistor M 2 Constituting a current mirror.
Further, two independent bare chips are used as the substrate of the device, and the power tube M 0 And a sampling tube M 1 On the die 1; amplifier 1 and MOS tube M 3 MOS transistor M 2 Sampling resistor R 4 A voltage dividing resistor R 5 And a voltage dividing resistor R 6 Distributed on the bare chip 2, and the voltage-dividing resistor R 5 Non-parallel voltage-dividing resistor R 6 One end of the connection is connected into V IN A voltage.
Further, a power tube M 0 And a sampling tube M 1 The MOS tubes of the same type are selected from N-type MOS tubes.
Further, the MOS tube M 2 And MOS tube M 3 The types are the same, and all adopt P type MOS tube, MOS tube M 2 The source of the sampling resistor is connected with the sampling electrode, and the drain of the sampling resistor is connected with the sampling resistor R4.
Further, the MOS tube M 3 And MOS transistor M 2 A control loop is connected between the MOS tube M and the MOS tube M for ensuring the MOS tube M 3 And MOS transistor M 2 The drain voltages are the same, the control loop comprising: amplifier 2, P type MOS tube M 4 MOS transistor M 2 And MOS tube M 3 The drain electrode of the amplifier 2 is respectively connected with the reverse input end and the forward input end of the amplifier 2, and the output end of the amplifier 2 is connected with the MOS tube M 4 Grid, MOS transistor M 4 Source electrode connected MOS transistor M 2 The drain electrode is connected with the sampling resistor R 4 。
Further, the MOS tube M 4 N-type MOS transistor M can also be selected 2 And MOS transistor M 3 The drain electrode of the amplifier is respectively connected with the positive input end and the negative input end of the amplifier 2, and the output end of the amplifier 2 is connected with the MOS tube M 4 Grid, MOS transistor M 4 Drain electrode connected with MOS transistor M 2 The drain electrode and the source electrode are connected with a sampling resistor R 4 。
The technical scheme shows that the invention has the following advantages: the current sampling circuit is added with a divider resistor R 5 A voltage dividing resistor R 6 By lowering the voltage dividing resistance R 5 And R 6 Can reduce the sampling tube M 1 The original sampling current is obtained, which is equivalent to increasing the area ratio of the power tube and the sampling tube; on the basis, the MOS transistor M 2 And MOS transistor M 3 Current mirrors formed so that the sampling tube M 1 The original sampling current is redistributed, and the MOS tube M is enlarged 2 And MOS transistor M 3 According to the current mirror proportion, most of the original sampling current can be returned to be output current, and a small part of the original sampling current flows into the ground through the sampling resistor to be final sampling current, which is equivalent to further increasing the area proportion of the power tube and the sampling tube, so that the problem of overlarge sampling power consumption is solved by the structure in the invention under the condition that the area proportion of the power tube and the sampling tube is smaller.
Simultaneously, as the area ratio of power tube and sampling pipe diminishes, the ratio of original sampling current and power tube electric current is more accurate, and the joining of divider resistance and current mirror can produce certain influence to the accuracy of final sampling current, however, resistance partial pressure and current mirror degree of accuracy all rely on the matching between the device, under the integrated circuit technology, be better than the separation device far away to the control of matching, consequently, the joining of divider resistance and current mirror can be ignored to the accuracy influence of final sampling current.
Drawings
FIG. 1 is a diagram of a prior art current sampling architecture;
FIG. 2 is a diagram of a conventional seal structure when different technologies are used to design MOSFETs and control circuits;
FIG. 3 is a layout of a power MOSFET and a sampling MOSFET designed by a conventional discrete device process;
FIG. 4 is a schematic circuit diagram of the present patent;
FIG. 5 is a control loop of the present patent for ensuring that the drain voltages of the current mirrors are the same;
fig. 6 is yet another control loop of the present patent with respect to ensuring that the current mirror drain voltages are the same.
Detailed Description
The following detailed description of embodiments of the invention refers to the accompanying drawings.
FIG. 4 is a schematic diagram of the present invention, including: amplifier 1 and sampling tube M 1 Power tube M 0 And MOS tube M 2 Sampling tube M 1 And a power tube M 0 The two are of the same type, both are of N type, and share a grid electrode and a drain electrode, and the drain electrode inputs V IN Voltage, sampling tube M 1 The source electrode of the MOS transistor is a sampling electrode, the sampling electrode and the MOS transistor M 2 Connected and commonly connected to the inverting input terminal of the amplifier 1, and the output terminal of the amplifier 1 is connected with the MOS transistor M 2 Grid of (3), MOS transistor M 2 Is connected with the sampling resistor R 4 (ii) a Power tube M 0 Is an output electrode for outputting V OUT A voltage; further comprising: MOS transistor M 3 A voltage dividing resistor R 5 A voltage dividing resistor R 6 The circuit adopts two independent bare chipsThe chip is used as the substrate of the device, and the power tube M shown in FIG. 4 0 And a sampling tube M 1 On the bare chip 1, an amplifier 1 and a MOS transistor M 3 MOS transistor M 2 Sampling resistor R 4 A voltage dividing resistor R 5 And a voltage dividing resistor R 6 Distributed on the bare chip 2, and the voltage-dividing resistor R 5 And a voltage dividing resistor R 6 Is connected in series to the power tube M 0 Between source and drain of for sampling V IN And V OUT A voltage difference therebetween; voltage dividing resistor R 5 And a voltage dividing resistor R 6 Voltage V of the common junction FB Equal to:
V FB ＝(V IN –V OUT )*R 6 /(R 5 +R 6 )+V OUT
voltage dividing resistor R 5 And a voltage dividing resistor R 6 Is connected to the positive input of the amplifier 1, the voltage V FB Connected to the positive input end of the amplifier 1, and a sampling tube M 1 Voltage V of the sampling electrode S1 Is connected to the reverse input end of the amplifier 1 and the P-type MOS tube M 2 Source electrode of MOS transistor M 2 Is connected with the output end of the amplifier 1, and an MOS tube M 2 As the output of the final sampling current, is connected to a sampling resistor R 4 (ii) a Composed of an amplifier 1 and a MOS transistor M 2 The negative feedback loop formed ensures that:
V S1 ＝V FB ，
sampling tube M 1 The current of (a) is:
I 1 ＝(V IN -V S1 )/R 1 ，
can be simplified as follows:
I 1 ＝I 0 /N/(1+R 6 /R 5 )，
MOS transistor M 2 The amplifier can also be an N-type MOS tube, and if the N-type MOS tube is selected, the forward input end and the reverse input end of the amplifier 1 need to exchange connection modes.
MOS transistor M 3 And MOS transistor M 2 The common gate is connected with the common source to form a current mirror, and the MOS transistor M 3 Is connected with the output electrode, and a MOS tube M is assumed 3 MOS transistor M 2 The area ratio of (A) is M: 1, corresponding toThe current ratio of (a) is:
I 2 ＝I 3 /M，
wherein, I 2 Is a MOS transistor M 2 Current of (I) 3 Is a MOS tube M 3 Due to:
I 1 ＝I 2 +I 3 ，
therefore:
I 2 ＝I 0 /N/(1+R 6 /R 5 )/(1+M)，
compared with the traditional mode, the final sampling current is reduced by a multiple of the current of the power tube:
K＝(1+R 6 /R 5 )*(1+M)，
because, another part of the sampling tube M 1 Via MOS transistor M 3 To the drain of V OUT ：
I 3 ＝I 0 *M/(1+M)/N/(1+R 6 /R 5 )，
The power consumption generated by the improved sampling circuit can be divided into R 5 And R 6 In connection therewith:
P R ＝(V IN -V OUT )*(V IN -V OUT )/(R 5 +R 6 )，
and with I 3 In connection therewith:
P I3 ＝I 3 *(V IN -V OUT )，
and with I 2 In connection therewith:
P I2 ＝I 2 *V IN ，
voltage dividing resistor R 5 And a voltage dividing resistor R 6 To V is outputted to OUT ，I 3 Is also finally output to V OUT Both currents become I OUT The final output current is their sum:
I OUT ＝I 0 *[1+M/(1+M)/N/(1+R 6 /R 5 )+R 0 /(R 5 +R 6 )]
thus, P R And P I3 Although generated by the sampling circuit, the power consumption of the part is equal to M 0 The same power consumption is generated, and the same power consumption is attributed to the power consumption caused by the output current, and in addition, R 5 And R 6 Is a voltage dividing resistor, the value of which is usually large, for example: tens of k Ω to hundreds of k Ω, resulting in R 0 /(R 5 +R 6 )<<1, the current and power consumption produced are negligible, so that it can be seen that the extra power consumption caused by sampling is only P I2 It is connected with the power tube M 0 The proportion of power consumption generated is:
P I2 /P M0 ＝V IN /(V IN –V OUT )/N/K，
in the case of N being constant, P I2 Can be adjusted by adjusting the divider resistance R 5 And a voltage dividing resistor R 6 Is reduced while increasing the current mirror M 3 And M 2 Ratio of (d) to the final sampled current I flowing to ground 2 Further reduction to meet power consumption requirements, such as: if the voltage dividing resistor R is used 5 And a voltage dividing resistor R 6 In a ratio of 1: 2, MOS transistor M 3 And MOS transistor M 2 In a ratio of 50: 1, in the same case V IN ＝5V，I OUT ＝1A，R 0 The power consumed by the output current is still about 15mW when N is 64 and 15m Ω, and the extra power consumption P caused by sampling I2 Is 0.51mW, i.e., 3.4%. Compared with the additional power consumption of 78mW under the traditional method, the additional power consumption is reduced by 153 times, and actually I OUT ≠I 0 Is instead I OUT ＝1.005*I 0 However, in the above calculation, I OUT Is approximately I 0 The error caused by this simplification is negligible.
Voltage dividing resistor R 5 And a voltage dividing resistor R 6 Ratio of (1) and MOS transistor M 3 And MOS transistor M 2 The ratio of (a) to (b) is adjusted not only in consideration of power consumption but also to ensure circuit performance, for example: if the voltage dividing resistor R is used 6 And a voltage dividing resistor R 5 Is too high, sampling tube M 1 The voltage drop between the drain and the source is very small, and the sampled voltage needs the amplifier to have lower input offset voltage, otherwise the power tube M 0 And a sampling tube M 1 The current ratio of (a) cannot be guaranteed, which undoubtedly increases the design difficulty of the amplifier; conversely, if the ratio is decreased, the sampling tube M is increased 1 Voltage drop between drain and source, sampling tube M 1 The source of the transistor M is very close to the output voltage, and when the voltage difference is too small, the MOS transistor M 3 Will not have enough space to ensure the normal operation of the current mirror, and therefore, the divider resistor R is optimized 6 And a voltage dividing resistor R 5 The ratio of (a) to (b) should be balanced in terms of power consumption and accuracy while ensuring normal operation of the circuit.
MOS transistor M 3 And MOS transistor M 2 Forming a current mirror structure such that the current mirror can be mounted on the MOS transistor M 3 And MOS transistor M 2 Area ratio shunting sampling pipe M 1 Current of MOS transistor M 3 And MOS transistor M 2 The MOSFET needs to work in the same working area, and under the working state, the MOSFET has 2 working areas, namely a linear area and a constant current area, so as to ensure that the MOS transistor M 3 And MOS transistor M 2 In the same operating region, their drain voltages are the same, which usually requires adding a control loop for ensuring the drain voltages are the same, as shown in fig. 5, the MOS transistor M 2 And MOS transistor M 3 The drain electrodes of the two transistors are respectively connected with the reverse input end and the forward input end of the amplifier 2, and the control loop passes through the amplifier 2 and the P-type MOS transistor M 4 The negative feedback loop is formed to force the MOS transistor M 2 And MOS transistor M 3 The drain electrode of the MOS transistor M always keeps equal voltage, thereby ensuring that the MOS transistor M is in a state of being in a non-contact state 2 And MOS transistor M 3 The same as the working area of the working area; FIG. 6 shows that if MOS transistor M 4 The control loop can still work by selecting the N-type MOS tube, and the MOS tube M 2 And MOS transistor M 3 The drain electrodes of the two transistors are respectively connected to the positive input end and the negative input end of the amplifier 2, and the output end of the amplifier 2 is connected with the MOS tube M 4 Grid, MOS transistor M 4 Drain electrode connected with MOS transistor M 2 The drain electrode and the source electrode are connected with a sampling resistor R 4 。
Enlarged MOS transistor M 3 And MOS transistor M 2 By a ratio of (A) to (B) which can reduce P I2 However, too large a proportion would result in I 2 Becomes very small at low output currents, I 2 Not only by the use ofOne of the branch currents of the current mirror also plays an important role in the two feedback loops of amplifier 1 and amplifier 2, if I 2 Too low, the two loops have the problems of instability or too slow response, so the MOS transistor M is optimized 3 And MOS transistor M 2 In proportions that balance power consumption and proper operation of the loop under various conditions.
Claims (6)
1. A circuit for sampling MOSFET power tube current with low power consumption comprises: amplifier 1 and sampling tube M 1 Power tube M 0 And MOS transistor M 2 Sampling tube M 1 And a power tube M 0 Common grid, sampling tube M 1 And a power tube M 0 Common drain for inputting V IN Voltage, sampling tube M 1 Source and MOS transistor M 2 Connected and commonly connected to the inverting input terminal of the amplifier 1, and the output terminal of the amplifier 1 is connected with the MOS transistor M 2 Grid of (3), MOS transistor M 2 The output end is connected with a sampling resistor R 4 (ii) a Power tube M 0 Source for outputting V OUT A voltage; the method is characterized in that: further comprising: MOS transistor M 3 A voltage dividing resistor R 5 A voltage dividing resistor R 6 Divider resistor R 5 And a voltage dividing resistor R 6 Is connected in series to the power tube M 0 Between the source and the drain, a voltage dividing resistor R 5 And a voltage dividing resistor R 6 The common contact is connected with the positive input end of the amplifier 1; MOS transistor M 3 Drain electrode of the power transistor M is connected with the power transistor M 0 Source, MOS transistor M 3 And MOS transistor M 2 Common gate and common source, MOS transistor M 3 And MOS transistor M 2 A current mirror is constructed.
2. The circuit for sampling MOSFET power tube current with low power consumption of claim 1, wherein: the power tube M adopts two independent bare chips as the substrate of the device 0 And a sampling tube M 1 Is positioned on the bare chip 1; amplifier 1 and MOS tube M 3 MOS transistor M 2 Sampling resistor R 4 A voltage dividing resistor R 5 And a voltage dividing resistor R 6 Distributed on the bare chip 2, and the voltage-dividing resistor R 5 Non-parallel voltage-dividing resistor R 6 Connection ofIs connected with a terminal V IN A voltage.
3. The circuit for sampling MOSFET power tube current with low power consumption of claim 1, wherein: power tube M 0 And a sampling tube M 1 The MOS tubes of the same type are selected from N-type MOS tubes.
4. The circuit for sampling MOSFET power tube current with low power consumption of claim 1, wherein: the MOS tube M 2 And MOS transistor M 3 The types are the same, and all adopt P type MOS tube, MOS tube M 2 The source electrode is connected with the sampling electrode, the drain electrode is connected with the sampling resistor R 4 。
5. The circuit for sampling MOSFET power tube current with low power consumption of claim 4, wherein: the MOS tube M 3 And MOS transistor M 2 A control loop is connected between the MOS tube M and the MOS tube M for ensuring the MOS tube M 3 And MOS transistor M 2 The drain voltages are the same, the control loop comprising: amplifier 2, P type MOS tube M 4 MOS transistor M 2 Drain electrode of (1) and MOS transistor M 3 The drain electrode of the amplifier 2 is respectively connected with the reverse input end and the forward input end of the amplifier 2, and the output end of the amplifier 2 is connected with the MOS tube M 4 Grid, MOS transistor M 4 Source electrode connected MOS transistor M 2 The drain electrode is connected with the sampling resistor R 4 。
6. The circuit for sampling MOSFET power tube current with low power consumption of claim 5, wherein: the MOS tube M 4 N-type MOS transistor M can also be selected 2 Drain electrode of (1) and MOS transistor M 3 The drain electrodes of the two transistors are respectively connected to the positive input end and the negative input end of the amplifier 2, and the output end of the amplifier 2 is connected with the MOS tube M 4 Grid, MOS transistor M 4 Drain electrode connected with MOS transistor M 2 The drain electrode and the source electrode are connected with a sampling resistor R 4 。
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| CN105223412A (en) * | 2014-05-30 | 2016-01-06 | 展讯通信（上海）有限公司 | A kind of current detection circuit and power management chip |
| CN111474975A (en) * | 2020-05-18 | 2020-07-31 | 成都市易冲半导体有限公司 | L DO output current sampling circuit and sampling precision adjusting method |
| CN112710886A (en) * | 2020-12-02 | 2021-04-27 | 江苏应能微电子有限公司 | Current sampling circuit |
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| CN113534884A (en) | 2021-10-22 |
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