CN115629299B - Semiconductor chip testing method for realizing isolation Kelvin test - Google Patents
Semiconductor chip testing method for realizing isolation Kelvin test Download PDFInfo
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- CN115629299B CN115629299B CN202211629554.9A CN202211629554A CN115629299B CN 115629299 B CN115629299 B CN 115629299B CN 202211629554 A CN202211629554 A CN 202211629554A CN 115629299 B CN115629299 B CN 115629299B
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- 238000012360 testing method Methods 0.000 title claims abstract description 90
- 239000004065 semiconductor Substances 0.000 title claims abstract description 13
- 238000002955 isolation Methods 0.000 title claims description 8
- 239000000523 sample Substances 0.000 claims abstract description 61
- 238000000034 method Methods 0.000 claims description 10
- 238000005259 measurement Methods 0.000 claims description 7
- 238000004891 communication Methods 0.000 claims description 6
- 230000003287 optical effect Effects 0.000 claims description 6
- 238000001514 detection method Methods 0.000 claims description 4
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- 230000001360 synchronised effect Effects 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 4
- 238000013461 design Methods 0.000 description 3
- 238000010998 test method Methods 0.000 description 2
- 230000009471 action Effects 0.000 description 1
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- 230000002457 bidirectional effect Effects 0.000 description 1
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2886—Features relating to contacting the IC under test, e.g. probe heads; chucks
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
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Abstract
The invention provides a semiconductor chip testing method for realizing isolated Kelvin test, wherein a probe card is arranged on a probe station, and a wafer is arranged on a wafer chuck; connecting a single chip microcomputer on a probe card, and arranging 2-16 parallel test groups on the probe card, wherein Hi and Shi channels of each parallel test group are welded on a probe together, slo channels of the parallel test groups are connected to a wafer chuck through leads, and the probes are in contact with different chips on a wafer; one group of parallel test groups is controlled by the singlechip to be switched on, and all other groups are in a closed state; on-off control of Hi, shi and Slo is realized, and the singlechip transmits data to the terminal for storage; the invention can realize the switching and testing of the chip under the condition of reducing the movement of the probe station as much as possible and reduce the time consumption of mechanical movement of the probe station.
Description
Technical Field
The invention belongs to the technical field of semiconductor laser testing, and particularly relates to a semiconductor chip testing method for realizing isolation Kelvin testing.
Background
A probe card is a component designed specifically for wafer testing that supplies power or signals. When the probe card works, the probes are required to contact the electrodes of the chip, so that the functions of supplying power, providing signals and testing are realized. The probe card needs to be installed on a probe station, and the chips are tested one by matching with the movement of the probe station.
Since there may be tens of thousands to hundreds of thousands of chips on a wafer, how to improve the test efficiency (UPH) of a single chip is an important issue of research in the industry. In the traditional method, each test of the chip requires the movement of a plurality of motors of the probe station to realize the replacement of the tested chip, so in order to improve the wafer test efficiency, the mainstream method is to improve the running speed of the motors as much as possible on the premise of ensuring the motion precision of the motors. However, for the requirement of high-speed testing, the testing time is not long as the movement time required by the motor, so that the testing efficiency is difficult to greatly improve.
Disclosure of Invention
The invention aims to solve the problem of improving the testing efficiency of a single chip on a wafer, provides a semiconductor chip testing method for realizing isolated Kelvin testing, and realizes the purpose of testing a plurality of chips in a single step, thereby greatly improving the testing efficiency.
The technical scheme adopted by the invention for solving the technical problems is as follows:
a semiconductor chip testing method for realizing isolation Kelvin test comprises a probe card, a wafer and a wafer chuck, wherein the probe card is arranged on a probe station, and the wafer is arranged on the wafer chuck; the method comprises the following steps:
connecting a singlechip based on an ARM (advanced RISC machine) on a probe card, and setting 2-16 parallel test groups on the probe card, wherein Hi and Shi channels of each parallel test group are welded on a probe together, and Slo channels of each parallel test group are connected to a wafer chuck through leads and each probe is contacted with different chips on the wafer;
based on the fact that each probe is in contact with the corresponding chip, the single chip microcomputer controls one group of parallel test groups to be conducted, and all other groups are in a closed state;
in response to the parallel test group in a conducting state, the terminal respectively controls three paths of isolating switch power supplies through the optocouplers, so that the switching control of three channels of Hi, shi and Slo is realized, the power supply and the measurement of chips in the parallel test group are completed, and the data are transmitted to the terminal by the single chip microcomputer to be stored;
and in response to the completion of the chip test in the parallel test set, closing the parallel test set, and conducting the next parallel test set until the chips communicated with each probe are measured.
Preferably, the three channels Hi, shi and Slo respectively adopt three MOS transistors as switching devices to realize isolated driving and switching.
Preferably, the Hi channel is a power supply positive electrode, the Shi channel is a voltmeter measurement positive electrode, the Slo channel is a voltmeter measurement negative electrode, and the three isolating switch power supplies share a positive electrode or a negative electrode with the Hi channel, the Shi channel and the Slo channel respectively to realize synchronous opening and closing of detection lines at two ends of a detected piece.
Preferably, the single chip microcomputer is responsible for receiving terminal commands and conducting and closing corresponding channels, and programmable multi-channel testing is achieved.
Preferably, the single chip microcomputer and the terminal are in serial communication by adopting 115200 baud rate.
Preferably, after all the chips corresponding to the parallel test sets on the probe card are measured, the probe station automatically moves to the next measurement area of the wafer to measure the next set of chips.
Compared with the prior art, the invention has the following beneficial effects:
1. according to the invention, the movement times of the motor are reduced by testing the plurality of chips without moving the positions, so that the time consumed by the probe station in the moving process is reduced, and the testing efficiency of the wafer is greatly improved;
2. the probe card can realize microsecond-level switching among all detection chips, so that the switching time is greatly reduced;
3. the invention uses three paths of isolating switch power supplies as the control power supply of the MOS tube, thereby realizing that the three MOS tubes can realize integral control under any potential to meet the Kelvin test method under the condition of multiple channels.
Drawings
The invention is further illustrated with reference to the following figures and examples.
FIG. 1 is a diagram of a three-way isolated power supply for driving MOS transistor according to an embodiment of the present invention;
FIG. 2 is a schematic circuit diagram of a three-channel isolator switch according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a probe connection according to an embodiment of the present invention;
FIG. 4 is a system connection diagram of an embodiment of the present invention;
in the figure: 1. a source table output line Hi; 2. A source meter test line SHI; 3. a source meter test line SLo; 4. a source table output line Lo; 5. a wafer chuck; 6. a probe card; 7. a communication line; 8. a terminal; 9. SMU source table.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1-4, as shown in the system of fig. 4, the main apparatus of the present invention includes 1, a source table output line Hi; 2. A source meter test line SHi; 3. a source meter test line SLo; 4. a source table output line Lo; 5. a wafer chuck; 6. a probe card; 7. a communication line; 8. a terminal; 9. an SMU source table; the Source Meter (SMU) is used to add current and voltage source functionality to the probe card 6, allowing accurate acquisition and measurement of voltage and/or current values simultaneously.
The specific test flow is as follows: a probe card 6 is arranged on a probe station, a wafer is arranged on a wafer chuck 5, the probe card 6 is connected with an ARM-based singlechip, 4 groups of parallel test groups are arranged on the probe card 6, hi and Shi channels of each group of parallel test groups are commonly welded on a probe, slo channels of each group of parallel test groups are connected to the wafer chuck through leads, and each probe is contacted with different chips on the wafer, namely 4 probes are communicated with 4 chips. At the moment, the terminal sends a signal to the single chip microcomputer, the single chip microcomputer controls 1 group of parallel test groups to be conducted, the other 3 groups of parallel test groups are closed, the three paths of isolating switch power supplies in the conducted parallel test groups drive the MOS tube to achieve the opening of the three channels of Hi, shi and Slo, after the test is finished, the single chip microcomputer transmits data to the terminal 8 to be stored, and the conduction and the test of the next group are continued.
In the invention, the MOS tube is used as a main switching device, and the conventional switching device adopts a relay, mainly because the relay is simple to control and bidirectional current can pass through. However, because the service life of the relay is short, the common relay has the switching service life of only 10 ten thousand times, and the repeated switching of the high-end relay does not exceed 100 ten thousand times at most. Therefore, in the field of wafer testing, 10 ten thousand switch lifetimes are far from satisfactory, and are therefore unsuitable for use as switching devices. In addition, the switching speed of the relay is also slow, generally more than 5ms, which is not in accordance with the object of the present invention to improve the detection efficiency.
In contrast, the MOS transistor is a voltage type device, and has almost no influence on the current of the channel when conducting; meanwhile, when the MOS tube is conducted, both the forward current and the reverse current can flow normally; and the switching life of the MOS tube is very long, and the MOS tube is switched for almost infinite times. And the switching speed is very fast, and can be 1 mus even less than 1 mus. Both speed and service life are well suited for the application of the present invention.
Meanwhile, the invention is designed aiming at the Kelvin test method, so that the switch device not only simply controls the on-off of the power supply end, but also controls the on-off of the power supply and the on-off of two test wires in a single power supply loop. The three switches are all at uncertain electric potential and are mutually associated, so that the three MOS tubes cannot be simultaneously turned on or off by performing voltage control on the three switches in a common ground mode.
Although the MOS transistor can realize the switching action, the MOS transistor is controlled by voltage, and therefore needs to be in common potential with a current channel to realize the switching on and off. And the Kelvin test is realized, the opening and closing of four channels are controlled on the loop of each tested piece, namely at least 3 MOS tubes are superposed to realize the Kelvin test.
In order to realize Kelvin test of the MOS tubes, the invention adopts three sets of isolation power supplies to be respectively responsible for the on-off of the three MOS tubes on the same loop. Therefore, the problem that the MOS transistor can be started only by common potential is solved. No matter how the potential in the loop changes, the three MOS tubes can be controlled to be switched on and off at will, and the Kelvin test is really realized. The circuit designs a three-way isolating switch power supply which is used as a control power supply of the MOS tube, and the three-way power supply is isolated from each other and does not interfere with each other. And meanwhile, the optical couplers are adopted to respectively control the potentials of the MOS tubes driven by the three-way switching power supply, so that the three MOS tubes can be integrally controlled at any potential.
Hi is the positive supply, as shown in fig. 2. Shi is the voltmeter measuring positive pole, and SLo is the voltmeter measuring negative pole. Three mutually isolated power supplies respectively share the positive pole or the negative pole with Hi, shi and SLo so as to realize the switch control of the three channels. And the isolation control is realized by controlling a switch signal through an optical coupler.
When SET Hi0, SET Shi0 and SETSLo0 are all high levels, the optocoupler can be driven to conduct, so that the three MOS tubes are respectively conducted in the mutually isolated state. The chip to be tested of the channel can supply power and measure.
The number of output groups of the probe card is different according to the size of the chip, each group can realize the isolation and conduction of three channels, and the probe card 6 with 2-path output can be designed for a chip with a larger size of 300 mu m; and for a chip of 70um, the probe card 6 with 8 outputs can be designed.
In order to realize automatic testing, a singlechip based on an ARM inner core is arranged on the probe card 6 and is used for channel selection control and communication with an upper computer. The system is responsible for communicating with the industrial control host, receiving commands of the industrial control host and opening and closing corresponding channels. Gates of MOS transistors of Hi, shi, and Slo of different channels are connected through the IO port for controlling on and off, and a specific probe card 6SN number is implanted for identifying whether or not it is an original probe card 6 matched with the system. In order to achieve the fastest control speed, the single chip microcomputer and the upper computer are in serial port communication by adopting 115200 baud rate.
FIG. 3 is a probe card design for testing 4 chips in parallel. Where Hi, shi of each group is soldered to the probe on the probe card and SLo of each group is connected to the wafer chuck by a wire. Thereby realizing accurate power supply and voltage testing.
The PCB of the probe card needs to meet the requirement of higher rigidity so as not to influence the pricking force of the probe, therefore, a PCB substrate with the thickness of more than 4mm is adopted for design, and in order to be compatible with the optical test of an optical chip, the surface of the PCB needs to be covered with a black solder mask.
In light of the foregoing description of the preferred embodiment of the present invention, many modifications and variations will be apparent to those skilled in the art without departing from the spirit and scope of the invention. The technical scope of the present invention is not limited to the content of the specification, and must be determined according to the scope of the claims.
Claims (6)
1. A semiconductor chip testing method for realizing isolation Kelvin testing comprises a probe card, a wafer and a wafer chuck, wherein the probe card is arranged on a probe station, and the wafer is arranged on the wafer chuck; the method is characterized by comprising the following steps:
connecting a singlechip based on an ARM (advanced RISC machine) on a probe card, and setting 2-16 parallel test groups on the probe card, wherein Hi and Shi channels of each parallel test group are welded on a probe together, and Slo channels of each parallel test group are connected to a wafer chuck through leads and each probe is contacted with different chips on the wafer;
based on the fact that each probe is in contact with the corresponding chip, the single chip microcomputer controls one group of parallel test groups to be conducted, and all other groups are in a closed state;
in response to the parallel test group in a conducting state, the terminal respectively controls three paths of isolating switch power supplies through the optical couplers, so that the switching control of three channels, namely Hi, shi and Slo is realized, the power supply and the measurement of chips in the parallel test group are completed, and the data are transmitted to the terminal by the single chip microcomputer to be stored;
the system comprises a power supply anode, a voltmeter measuring anode, a voltage meter measuring cathode, a voltage meter measuring anode and a Slo, wherein Hi is the power supply anode, shi is the voltmeter measuring anode, and Slo is the voltmeter measuring cathode; three mutually isolated power supplies respectively share a positive pole or a negative pole with Hi, shi and Slo to realize the on-off control of the three channels, and the on-off control is realized by controlling a switching signal through an optical coupler;
and in response to the completion of the chip test in the parallel test set, closing the parallel test set, and conducting the next parallel test set until the chips communicated with each probe are measured.
2. The method for testing a semiconductor chip implementing an isolated kelvin test according to claim 1, wherein: and the Hi channel, the Shi channel and the Slo channel respectively adopt three MOS tubes as switching devices to realize isolated driving and switching.
3. The method for testing a semiconductor chip implementing an isolated kelvin test according to claim 2, wherein: the Hi channel is a power supply anode, the Shi channel is a voltmeter measuring anode, the Slo channel is a voltmeter measuring cathode, and the three isolating switch power supplies share an anode or a cathode with the three channels of Hi, shi and Slo respectively to realize synchronous opening and closing of detection lines at two ends of a detected piece.
4. The method for testing a semiconductor chip implementing an isolated kelvin test according to claim 1, wherein: the single chip microcomputer is responsible for receiving terminal commands and conducting and closing corresponding channels, and programmable multi-channel testing is achieved.
5. The method for testing a semiconductor chip implementing an isolated kelvin test according to claim 4, wherein: the single chip microcomputer and the terminal are in serial communication by adopting 115200 baud rate.
6. The method for testing a semiconductor chip implementing an isolated kelvin test according to claim 1, wherein: when the chips corresponding to all the parallel test groups on the probe card are measured, the probe station can automatically move to the next measurement area of the wafer to measure the next group of chips.
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| JP2008187023A (en) * | 2007-01-30 | 2008-08-14 | Toshiba Corp | Test method and test device for semiconductor wafer |
| CN103547934A (en) * | 2011-05-19 | 2014-01-29 | 塞勒林特有限责任公司 | Parallel concurrent test system and method |
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Denomination of invention: A semiconductor chip testing method for implementing isolated Kelvin testing Granted publication date: 20230317 Pledgee: Bank of Nanjing Co.,Ltd. Changzhou Branch Pledgor: Ketai optical core (Changzhou) Testing Technology Co.,Ltd. Registration number: Y2024980025700 |
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