CN109473361B - Parallel test method of semiconductor power device - Google Patents

Abstract

The invention discloses a parallel test method of semiconductor power devices, which is used for carrying out parallel test on the semiconductor power devices on the whole lead frame through a chip packaging test device in a packaging test procedure, wherein the chip packaging test device comprises a test head (100), a test bracket (110) and an operation machine table (111). The parallel test method comprises the following steps: pre-rib cutting step S1, chip fixing step S2, probe arranging step S3, loop establishing step S3, device grouping step S4, and parallel testing step S5: the switch control bit of the switch control module (108) controls the parallel test of the semiconductor power devices on the group A test stations according to a ping-pong test mode; after the group A test is finished, the switch control bit of the switch control module (108) controls the parallel test of the semiconductor power devices on the group B test station according to a ping-pong test mode. The invention achieves the technical effect of improving the testing efficiency.

Description

Parallel test method of semiconductor power device

Technical Field

The invention relates to the technical field of testing or measuring methods or devices specially adapted for use in the manufacture or handling of semiconductor or solid state devices or parts thereof (H01L 21/66), and in particular to a method for parallel testing of semiconductor power devices.

Background

The production flow of the conventional semiconductor power device is shown in fig. 1:

the wafer is adhered to a blue film at a wafer loading station, the whole wafer is cut into independent chips through a wafer cutting station, the chips are adhered to a frame at the chip adhering station, the cushion type welding points on the chips on the frame are welded and connected to the appointed terminal pins on the frame at a chip wire welding station by high-purity metal wires, then the whole is subjected to thermal hardening and injection molding solidification, and the chips after being subjected to rib cutting and molding of the electroplating pins are placed in a pipe and then subjected to grain sorting, testing, good product printing and packaging.

The following aspects are described for the limitations of the single-grain chip test of the conventional test station at present:

(1) the testing speed of a single chip is slow, and the cumulative production period of the chip conveying time is long.

(2) Individual factors of a single chip lead to an increased quality risk of human interference factors.

(3) The single-grain chip universal golden finger needs to be independently positioned, so that the testing yield is reduced easily due to poor contact, and unnecessary cost waste is caused.

Patent document CN102253324B discloses a method for testing hot carrier effect by applying the parallel test structure, which includes the following steps: s1, testing a single device stage, S2, testing a stress loading stage, S3, repeatedly and alternately testing the step S1 and the step S2, and comparing the electrical performance parameters measured for multiple times. The invention can improve the testing efficiency of the MOS device hot carrier.

Patent document CN101702005B discloses a parallel test circuit of Time Dependent Dielectric Breakdown (TDDB). The TDDB parallel test circuit provided by the invention can greatly shorten the TDDB detection time of the transistor device, greatly improve the detection efficiency of the transistor device and effectively reduce the production cost.

Patent document CN106788441A discloses a DAC array control circuit for driving a MOS thin-film resistor array, which includes an image data FIFO, a timing control circuit, and a DAC array connected in sequence; the DAC array is of an m multiplied by n structure, namely m DACs are in one group, and n groups are in total; m and n are both natural numbers not containing 0; the data input ends of the m DACs in each group are connected in parallel, and the n groups of DACs are respectively and independently connected with the time sequence control circuit; the output end of the DAC array is used for being connected with the MOS thin-film resistor array, and the number of the channels of the DAC is consistent with that of the analog signal input ends of the MOS thin-film resistor array and corresponds to that of the analog signal input ends of the MOS thin-film resistor array one by one; the time sequence control circuit is in a double-buffer control mode; the DAC array control circuit for driving the MOS thin film resistor array ensures the loading correctness of multi-path DAC data, improves the refreshing efficiency of image data and ensures the conversion reliability and real-time performance of the image data DAC.

Patent document CN101728293B discloses a method for Gate Oxide Integrity (GOI) test of a MOS transistor device, comprising the following steps: providing a test power supply; respectively connecting a plurality of MOS transistor devices to be tested to the test power supply; detecting the current leakage of the MOS transistor device; and when the leakage current changes suddenly, starting a detection device to detect a failure point on the MOS transistor device. By utilizing the method, when the reliability of the gate oxide layer of the MOS transistor device is tested, particularly when the parallel Time Dependent Dielectric Breakdown (TDDB) test is adopted, the service life of the device to be tested can be evaluated, and the specific condition of the failure point on the gate oxide layer of the MOS transistor device to be tested can be synchronously, timely and accurately reflected, so that the device is further subjected to failure analysis.

Patent document CN205670168U discloses a voltage testing device based on a voltage meter head, which includes a voltage access unit, a PLC unit and a voltage meter head detection display unit, where the voltage access unit includes a first dc amplitude voltage input interface, a second dc amplitude voltage input interface and an ac voltage input interface; the PLC unit comprises a ping-pong switch array, a ship-type switch array and an air switch array; the voltage meter head detection display unit comprises a three-wire direct current voltage meter head unit, a two-wire direct current voltage meter head unit and a two-wire alternating current voltage meter head unit. The utility model tests the voltage value to be tested through the voltage meter head unit, which can save the development time and cost; the whole testing process is simple and clear, the result is displayed visually, the testing time is short, the accuracy is high, the testing device is compact in structure and simple to operate, and the personalized testing requirements of users can be met.

Patent document CN203084151U discloses a ping-pong tester based on a power-off technology, which includes a plurality of test heads, and a power control module electrically connected to the test heads; the utility model has the advantages that: the tester overcomes the defect that the test efficiency and the accuracy are influenced because a large number of signals need to be cut off in the alternate test switching process of the existing tester based on the ping-pong test principle, and has high test efficiency and high accuracy.

Patent document CN202903908U discloses a PCB circuit board testing device, in particular to a novel ping-pong mode vacuum double-station PCB circuit board testing device. The novel ping-pong mode vacuum double-station PCB testing equipment is characterized by comprising a testing equipment body (1), an upper cover jig (2) and a lower cover jig (3), wherein the upper cover jig (2) and the lower cover jig (3) are arranged on the testing equipment body (1), and one end of the upper cover jig (2) is hinged with one end of the lower cover jig (3); a handle (4) is arranged on the upper cover jig (2); a labor-saving component is arranged behind the upper cover jig (2); the labor-saving assembly is fixedly connected with the handle (4). Therefore, the utility model has the advantages of as follows: 1. the design is reasonable, the structure is simple and the device is completely practical; 2. the degree of automation is high, and simultaneously, the physical consumption and fatigue of operators can be reduced, so that the working efficiency is improved by more than 30 percent, and the accuracy of product judgment is improved by more than 20 percent.

Patent document CN201637797U discloses a testing machine, which includes a plurality of test heads, and further includes a control module connected to the plurality of test heads through data interfaces, the control module receives test signals, instructs the plurality of test heads to start testing in sequence through the data interfaces, sends test results to the control module through the data interfaces after the test of each test head is completed, and after all test heads have completed a test, collectively outputs all test results through the control module. The testing machine is provided with a plurality of testing heads, the wafers can test chips with the same number as the testing heads once when moving and contacting with the probe card, and the testing speed and the testing efficiency are greatly improved compared with the traditional single-chip testing machine which can only test one chip once when moving and contacting with the probe card. And only one probe station is needed to be matched for testing, and compared with a tester which needs to be matched with two probe stations for performing ping-pong testing, the cost can be saved.

Patent document CN103311143B discloses a chip package testing device and a lead frame used by the same, the device includes a testing processing unit, a contactor support and a plurality of contactor units, the lead frame is fixed on the contactor support, the contactor units are provided with probe arrays composed of a plurality of contact probes, the spacing size between the contact probes is matched with the spacing size between the package chip pins on the lead frame in the transverse direction and the longitudinal direction, the contact probes are arranged on the contactor support in a platform contact manner and are electrically connected with the package chip pins, and the number of the package chips is an integral multiple of the number of the contact probes contained in the contact probe arrays; the injection molding rubber channel on the lead frame comprises a plurality of capsule-shaped slots, the connection intervals of the two capsule-shaped slots are positioned at the positions of the pins of the chip, the capsule-shaped slots are positioned at the end parts of the chip and form a one-to-one correspondence relationship, and the injection molding rubber channel is positioned on the upper surface of the lead frame. The invention not only improves the parallel test efficiency, but also improves the utilization rate of the lead frame and the molding material.

Patent document CN101702005B discloses a parallel test circuit including a plurality of MOS transistor devices with time dependent dielectric breakdown, and is not a parallel test apparatus for testing MOS transistor devices.

Patent document CN102253324B discloses a parallel test structure for hot carrier effect of MOS devices, but does not disclose a ping-pong mode of the control circuit.

Patent document CN101728293B discloses a method for Gate Oxide Integrity (GOI) testing of MOS transistor devices, but does not disclose a ping-pong mode of control circuitry.

Patent document CN106788441A discloses a DAC array control circuit that drives a MOS thin film resistor array, and is not a parallel test apparatus for testing MOS transistor devices.

Patent documents CN201637797U, CN202903908U, CN203084151U, and CN205670168U disclose a ping-pong mode of a control circuit, but do not disclose a test of a semiconductor power device.

Patent document CN103311143B discloses a chip package testing apparatus and a lead frame used for the same, but does not disclose a specific structural design of a parallel testing apparatus.

Disclosure of Invention

In order to overcome the defects of the prior art, one of the purposes of the invention is to provide a parallel test method of a semiconductor power device, which can perform parallel test on devices on the whole frame, is applied to a final packaging test procedure, conveniently performs high, low and normal temperature tests, improves the production capacity and reduces the test cost.

The second objective of the present invention is to provide a parallel test method for semiconductor power devices, which can controllably perform a ping-pong mode test mode through a logic circuit and a program code, and simultaneously test a plurality of power devices in parallel, thereby fully utilizing limited resources and intelligently improving the utilization efficiency.

To this end, the present invention provides a parallel test method of semiconductor power devices, which is used to perform parallel test of semiconductor power devices on the whole lead frame by a chip package test apparatus in a package test process, wherein,

the semiconductor power devices are molded packaging units distributed on the lead frame;

the chip packaging test device comprises a test head, a test support and an operating machine table, wherein the test head comprises a contact circuit board, a main control circuit board, a TIB test resource interface board, a programmable load loading board and a probe contact device;

the probe contacting device comprises a plurality of probes and a bracket, wherein the probes are assembled on the bracket;

the contact circuit board is provided with copper foil printed circuit contact points which are electrically connected with all chip pins of all the packaging units on the lead frame at the same time;

the method is characterized in that: the parallel test method comprises the following steps:

pre-rib-cutting step S1: cutting and separating a part of chip pins of each packaging unit from the lead frame, and keeping the other part of chip pins of each packaging unit connected with the lead frame;

chip fixing step S2: fixedly mounting the lead frame on a strip type chip tray of the operating machine table;

probe alignment step S3: forming a plurality of probes of the probe contact device into a probe array, wherein the spacing size between the probes is matched with the spacing size between chip pins of a packaging unit on the lead frame in the transverse direction and the longitudinal direction, and the second end part of each probe is electrically connected with a corresponding copper foil printed circuit contact point of the contact circuit board;

loop establishment step S3: the probe adopts a platform contact mode and is electrically connected with the chip pins of the packaging units, so that all the chip pins of all the packaging units on the lead frame are electrically connected with the first end parts of the corresponding probes, a test loop is established for each semiconductor power device on the lead frame, and the test loop of each semiconductor power device corresponds to one test station in the test head;

device grouping step S4: dividing the test stations with the established test loops into two groups: the test system comprises a group A test station and a group B test station, wherein the serial number of the group A test station is an odd number which is equal to the odd number, the serial number of the group B test station is an even number which is equal to the even number, and I is more than or equal to 1;

parallel test step S5: the switch control bit of the switch control module controls the group A test stations to be in a state to be tested according to a ping-pong test mode, and the test head performs parallel test on the semiconductor power devices on the group A test stations; after the group A test is finished, the switch control bit of the switch control module controls the group B test stations to be in a to-be-tested state according to a ping-pong test mode, and the test head performs parallel test on the semiconductor power devices on the group B test stations.

According to other technical solutions of the present invention, it may further include one or more of the following technical features. As long as such a combination of features is practicable, new technical solutions formed therefrom are part of the present invention.

Compared with the prior art, the invention has the beneficial effects that:

the strip test of the semiconductor power device meets the requirement that a product for testing devices on a whole frame in parallel is applied to a final packaging test procedure by connecting the test system and the plurality of semiconductor power devices, conveniently performs high, low and normal temperature tests, improves the production capacity and reduces the test cost.

Drawings

The features, advantages and characteristics of the present invention are better understood by the following description of the detailed description with reference to the accompanying drawings, in which:

FIG. 1: an improved chip packaging process flow diagram is shown in which a strip-wise parallel test step is added to the process flow;

FIG. 2: a schematic diagram of a lead frame is shown, in which the legs 1 and 2 of the chip are cut and separated from the lead frame;

FIG. 3: the method comprises the steps of showing a real object diagram of a lead frame, wherein the connection of each chip in the lead frame is shown, the lead frame is provided with unique two-dimensional code identification, and an array coordinate is arranged on a chip unit in the frame;

FIG. 4: a schematic structural diagram illustrating an embodiment of a chip package testing apparatus is shown;

FIG. 5: showing the encapsulation units cut from the lead frame and formed by the presser foot;

FIG. 6: a schematic diagram illustrating a preferred embodiment of a parallel test apparatus for semiconductor power devices;

FIG. 7: fig. 6 is a schematic structural diagram of a test head of the parallel test equipment for semiconductor power devices;

FIG. 8: FIG. 6 is a schematic diagram of a system architecture of a parallel test apparatus for semiconductor power devices;

FIG. 9: fig. 6 is a schematic diagram illustrating a connection principle between a main control board and internal resources of a test head of the parallel test apparatus and a chip to be tested;

FIG. 10: fig. 9 is a schematic diagram of the structure and principle of a DCS integrated module circuit board of the main control panel;

FIG. 11: fig. 9 is a schematic diagram illustrating the structure and principle of a load programmable board card of the main control panel;

FIG. 12: FIG. 6 is a schematic diagram of the structure and principle of a programmable load plate of a test head of the parallel test apparatus;

FIG. 13: FIG. 9 is a block diagram of the switch control modules of the main control board;

FIG. 14: fig. 9 is a schematic diagram illustrating the structure and principle of the floating driving board 1071 of the main control board;

FIG. 15: fig. 6 is a schematic structural and schematic diagram of a TIB test resource interface board 103 of a test head of the parallel test device;

FIG. 16: FIG. 6 is a schematic diagram of a parallel test apparatus with a test head connected to a product under test;

FIG. 17: FIG. 6 is a schematic diagram of a contact circuit board 101 of a test head of the parallel test apparatus connected to a product to be tested;

FIG. 18: fig. 6 is a schematic diagram illustrating the principle of parallel testing, grouping testing and grouping ping-pong testing performed by a testing head of the parallel testing apparatus;

FIG. 19: FIG. 6 is a schematic diagram of a hardware block connection principle of an external high-power voltage current source of the parallel test apparatus;

FIG. 20: FIG. 6 is a schematic diagram of a hardware packet connection principle of a digital channel of a TIB test resource interface board of a test head of the parallel test device;

FIG. 21: fig. 6 is a schematic diagram of the working principle of a test head of the parallel test equipment for testing the electrical parameter IDSS of the PowerMOS device by programming a dynamically composed test circuit;

FIG. 22: fig. 6 is a schematic diagram of the working principle of a test head of the parallel test equipment for testing the electrical parameter VTH of the PowerMOS device by programming a dynamically composed test circuit;

FIG. 23: fig. 6 is a schematic diagram of the operating principle of a testing head of the parallel testing apparatus for testing an electrical parameter VDSON of a PowerMOS device by programming a dynamically composed testing circuit;

FIG. 24: the schematic diagram of the lead frame after the PowerMOS chip is molded, wherein all pins of the PowerMOS chip are not cut and are connected with the lead frame;

FIG. 25: the schematic diagram of the lead frame after the PowerMOS chip is molded, wherein a G pole pin and an S pole pin of the PowerMOS chip are cut and separated and are not connected with the lead frame;

FIG. 26: the schematic diagram of the PowerMOS chip on the lead frame is that a G pole pin and an S pole pin are cut and separated;

FIG. 27 is a schematic view showing: a finished product schematic diagram of the PowerMOS device;

FIG. 28: FIG. 25: another schematic diagram of the lead frame after the PowerMOS chip is molded and formed;

FIG. 29: FIG. 6 is a schematic circuit diagram of a parallel test apparatus with a test head connected to a single PowerMOS chip to be tested;

FIG. 30: a schematic diagram of a parallel test summary circuit of a PowerMOS chip of a 96 test station;

FIG. 31: parallelly testing another summary circuit schematic diagram of the PowerMOS chip of the 96 test station;

FIG. 32: picking a schematic diagram of a parallel test circuit of a PowerMOS chip of a 96 test station;

FIG. 33: the test head of the parallel test equipment shown in fig. 6 is a graphical table of partial source codes for programming a dynamically composed test circuit for testing the electrical parameter IDSS of the PowerMOS device;

FIG. 34: a circuit schematic of a hardware control response corresponding TO the source code databiton (DCS _ TO _ GATE1) of fig. 33;

FIG. 35: FIG. 33 is a circuit schematic of a hardware control response of the source code micro. Beast. pins ("DRAIN _ bearings"). Voltage (Vdrain);

FIG. 36: FIG. 33 is a chart of test results for the source codes Mysequence- > test (idss1) and Mysequence- > test (idss 2);

FIG. 37: the test head of the parallel test equipment shown in fig. 6 is a graphical table of partial source codes for programming a dynamically composed test circuit to test an electrical parameter VTH of a PowerMOS device;

FIG. 38: a circuit schematic corresponding TO the hardware control response of the source code micro.connectivity.setdata (1,14, DatabitOn) and databioff (DCS _ TO _ GATE1) of fig. 37;

FIG. 39: test result charts of the source codes mysequence- > test (vth1), mysequence- > test (vth2), and mysequence- > test (deltavth) of fig. 37;

FIG. 40: the test head of the parallel test equipment shown in fig. 6 is used for testing a part of source code illustration table of an electrical parameter VDSON of the PowerMOS device by programming a dynamically composed test circuit;

FIG. 41: a circuit schematic of a hardware control response corresponding to a portion of the source code of FIG. 40;

FIG. 42: FIG. 6 is a table listing the maximum load current and other parameters of the test head of the parallel test apparatus;

FIG. 43: FIG. 40 is a test result chart of source code;

FIG. 44: another circuit schematic of the hardware control response corresponding to a portion of the source code of fig. 40.

FIG. 45: a parallel test result list of the PowerMOS chip of the 96 test station;

FIG. 46: a test result judgment table of the PowerMOS chip;

FIG. 47: a schematic diagram of a resource allocation table part with 96 test bits;

in the drawings, identical or similar elements are provided with the same reference numerals, and different elements are provided with different reference numerals, wherein: 100. a test head; 101. a contact circuit board; 102. a main control circuit board; 103. TIB testing resource interface board; 104. a programmable load plate; 1041. an inductive load; 1042. a resistive load; 105. a probe contacting device; 1051. a probe; 1052. a bracket; 106. a DCS integrated module circuit board; 1061. a DCS module; 107. floating the driving board card; 1071. a floating drive measurement source; 108. a switch control module; 109. loading the programmable board card; 1091. a load programmable module; 1092. a load programmable unit; 1093. a differential instrument channel; 1094. a time measuring unit; 110. testing the bracket; 111. operating the machine table; 112. a strip-type chip tray; 113. a strip chip to be tested; 114. testing the heating device at high temperature; 200. connecting a cable; 300. a high power voltage current source; 400. testing the computer; 500. a board card working power supply; 900. and (5) testing the product to be tested.

Detailed Description

The invention is further described below in conjunction with the appended drawings and the detailed description.

The design concept of the invention is as follows:

the invention fully utilizes high-density chips on the lead frame to carry out centralized processing, as shown in figure 1, pre-cutting ribs are carried out after the lead frame is molded, electroplated and baked, as shown in figure 2, the cutting of specific pins ensures the realization of electrical test, partial chip pins of each packaging unit are separated from the lead frame in a cutting way, and the packaging units are integrally tested in parallel by matching with unique two-dimensional identification codes and corresponding longitudinal and transverse coordinates on the frame.

Parallel testing is performed by connecting the chip terminals to the lead frame.

The chip package testing device comprises a testing processing unit, a contactor support and a plurality of contactor units. The test handling unit is also referred to as a parallel test apparatus or tester, the contactor rack is also referred to as a test rack 110, and the plurality of contactor units are also referred to as probe contact devices 105.

The lead frame is fixedly arranged on the contactor support, the contactor unit is provided with a probe array consisting of a plurality of contact probes 1051, the spacing size between the contact probes 1051 is matched with the spacing size between the pins of the packaged chips on the lead frame in the transverse direction and the longitudinal direction, the contact probes 1051 adopt a platform contact mode, are arranged on the contactor support and are electrically connected with the pins of the packaged chips, the number of the packaged chips is consistent with the number of the contact probes 1051 contained in the contact probe array, and the number of the packaged chips is 96 for example. The contact probe 1051 is also referred to as a probe 1051, and the packaged chip is also referred to as a packaging unit.

Uploading the corresponding test result to a server for printing the good chips at the next station; after the strip test, the whole lead frame is arranged at the next laser printing station, laser printing is carried out on good products according to the test result of the server, the product of the whole lead frame is used for cutting pins at the cutting and forming station, after the pin is pressed and formed, the pin is cut independently, as shown in figure 5, then, after the quick test item test of the leakage on-off part is carried out on the packaging machine, the product passes the appearance detection of the product, and then the product is packaged in a pipe or a packaging roll.

Chip package testing device and design of lead frame used by same

The design of the lead frame comprises:

the connection and cutting design of each chip in the lead frame aiming at the Power MOS test is shown in figure 3, which is a forming diagram of the lead frame, the connection of each chip in the frame, the unique two-dimensional code identification of the lead frame and the chip unit array coordinate in the frame;

designing a unique two-dimensional code identification and in-frame chip unit array coordinate identification system of a lead frame, as shown in fig. 3;

the design of the lead frame positioning matching test contactor is, as shown in fig. 4, a chip packaging test device, also called a parallel test equipment of a semiconductor power device, which includes a test head 100, the test support 110, and an operating machine 111, wherein the test head 100 includes a contact unit and a probe 1051 integrated module, also called a probe contact device 105, and the chip packaging test device further includes a frame image positioning system for automatically positioning a probe array.

Fig. 5 shows the package unit such as a semiconductor power device being cut and separated from the lead frame and being foot-formed.

The design of the chip packaging test device comprises the following steps:

contact unit the probe 1051 is an integrated module;

the design of the probe 1051 integrated module and lead frame matching part of the contact unit;

the design of the contact unit, the probe 1051 integrated module and the lead frame image positioning system;

the design introduction of the chip packaging test device and the test platform for testing the key parameter resource allocation is as follows:

overview of System architecture and functionality

As shown in fig. 6, the test system or the parallel test apparatus is composed of the test head 100, a connection cable 200, a voltage current source 300, and a test computer 400, wherein the test head 100 has integrated resources such as a voltage circuit source and a clock digital instrument used for testing, and the connection cable 200 includes a communication cable connected to the test computer 400, a cable connected to an external large voltage current source, and a control cable of the test head 100. The parallel test equipment for the semiconductor power device shown in fig. 6 is limited to electrical performance test of a chip and output of a test result, and needs to be matched with another equipment to perform connection test and test output after loading and transmission of a lead frame and automatic positioning of an image, so that a large number of product tests are completed.

The test head 100 can design a dynamic circuit combination of a chip interface board to be tested through programming, and is used for testing various types of chips; the ability to test chips in parallel; the chip interface board to be tested can be configured to connect various resources. The chip interface board to be tested is also referred to as a contact circuit board 101.

The test computer 400 is capable of running test programs; control of the tester and external equipment, such as external power supplies, etc.; storing the data; communicate with the product operating machine 111. The tester is also referred to as a parallel test apparatus. The operating machine 111 of the product is, for example, a strip chip test platform of a high-power MOS transistor.

The extended configuration of the test system is as follows:

● 1 high voltage sources of 3 kilovolts;

● LCR meters with more than 48 channels;

● more than 48 high precision measuring instruments;

● the probe 1051 is measured over 48 high speed currents;

test head structure

As shown in fig. 7, the test head 100 includes the contact circuit board 101, a master circuit board 102, a TIB test resource interface board 103, and a programmable load loading board 104, where the contact circuit board 101 is used for contact testing of various products, and is connected to the master circuit board 102 and the TIB test resource interface board 103. The contact circuit Board 101 is also called a test product contact Board, a product test connection circuit Board, or a Family Board, the Main control circuit Board 102 is also called a Main control Board, or a Main Board, and the TIB test resource interface Board 103 is also called a test resource interface Board, a TIB circuit Board, or a TIB Board.

As shown in fig. 8, the test head 100 further includes the probe contact device 105, wherein the probe contact device 105 is configured to be electrically connected to the product 900 to be tested, so as to facilitate parameter measurement of the product 900 to be tested.

The main control circuit board 102 includes a timing measurement unit, a differential measurement instrument, and a loadable program module. Optionally, the main control circuit board 102 includes 48 timing measurement units, 48 differential measurement meters, and 48 loadable program modules, which are also referred to as loader units.

The main control circuit board 102 further includes a current voltage source and a test quantity meter, a floating driving measurement source 1071, and a switch control module 108, wherein the number of the current voltage source and the test quantity meter is, for example, 48, the number of the floating driving measurement source 1071 is, for example, 192, and the number of the switch control bits of the switch control module 108 is, for example, 240.

The test system further comprises an external power supply or board working power supply 500 for supplying energy for the board working.

The main control circuit board 102, the internal resources and the chip to be tested are formed and connected

As shown in fig. 9, the main control circuit board 102 is also called a main control board or a main control board, and the main control circuit board 102 functions as follows:

1. a master control center for all components;

2. the communication center of all the components, and the communication mode is USB/PCI Express for example;

3. all component connection interfaces except for external extension sources;

the main control circuit board 102 includes:

TIB board card interface;

a TIB circuit board, also referred to as said TIB test resource interface board 103, the number of which is for example 1;

the TIB test resource interface board 103 includes digital channels and PPMU units, for example, 64 PPMUs units and 320 digital channels, wherein the PPMU unit includes 8 channels, and each PPMU can be individually connected to 48 test stations in a system configured with 48 parallel test stations; each digital channel can be directly controlled by FPGAs; each test station may use 5 digital channels. PPMU is referred to as a per pin parameter measurement unit module.

Described in terms of the manner from the area where the product 900 to be tested is fed to the product testing station, the testing station comprises:

● to each chip pin;

● define means for packaging each chip to facilitate accurate positioning of the contactor contacts;

● contact is connected to a corresponding test bit on the Family board of the tester.

6.192 independent floating drive sources, grouped in a4 x 48 manner;

7. a connection means of the digital channel and the PPMU, also called first connection means;

8.48 direct current output Sources and measuring instruments, wherein the assembly of the direct current output Sources and the measuring instruments or the circuit Board is also called as DC-Sources Board or DCS NG;

9.48 programmable load modules, each programmable load module comprising 1 programmably loaded load, also known as LoadProg NG, 1 differential meter unit or differential meter channel, also known as DiffMeter, and 1 timing clock meter unit, also known as timing measurement unit or TMU;

10. the switch control module 108, which provides 240 switch control bits; dividing the voltage into 5 groups, wherein each group comprises 48 switch control bits;

the switch control bits can drive either a micro test transceiver or a micro transceiver, each with 16 switches individually programmed with a Single wire protocol frame or Single wire ptocol frame, or MOS semiconductor switches, e.g. for relay use;

the 240 switch control bits are fully controllable to each test station by circuit setting, however, it is proposed to divide into 5 groups, the first 4 groups being used as connections for resources, the 5 th group being used as a common connection;

conventionally, up to four different micro-test transceivers are used to test station-related connections. Each micro-test transceiver is controlled by one data bit, which is associated as follows:

first group (1-48): controlled by transceiver number 1

Second group (49-96): controlled by transceiver number 2

Third group (97-144): controlled by transceiver No. 3

Fourth group (145-192): controlled by transceiver No. 4

Fifth group (193- & 240): controlled by a common transceiver

Working principle of 48 voltage current sources and test quantity instrument DCS NG

As shown in fig. 10, a total of 4 DCS integrated module circuit boards 106 are mounted on the main control circuit board 102, each DCS integrated module circuit board 106 is interchangeable, 12 DCS modules 1061 are fixedly mounted in each DCS integrated module circuit board 106 by screws, and a total of 48 DCS modules of 12 × 4 support 48 test sites to work simultaneously. The DCS module 1061 has the functions of a current voltage source and a test volume meter. The DCS integrated module circuit board 106 is also called DCS Boards, and the DCS module 1061 is also called DCS MP NG.

Specification parameters of the DCS module 1061:

v function has 4-quadrant output VI

The functions of the V are FV, FI, FHIZ, MV, MI

Output current range of √ 20uA, 200uA, 2mA, 20mA, 200mA, 4A

Output voltage range of 1V, 3V, 5V, 10V, 30V and 80V

Alarming function for abnormal V shape

V. time measurement function

Programmable loading load and connection measuring instrument principle

As shown in fig. 11, the main control circuit board 102 includes load programmable boards 109, where the number of the load programmable boards 109 is, for example, 4. The load programmable board 109 includes load programmable modules 1091, wherein each of the load programmable board 109 includes, for example, 12 load programmable modules 1091. The Load Programmable Board 109 is also called a Load Prog Board, and the Load Programmable module 1091 is called a Load programable NG.

The load programmable module 1091 includes a load programmable unit 1092, a differential meter channel 1093, and a timing measurement unit. The load programmable unit 1092 is also called as an additional programmable channel, loadable program module, the differential meter channel 1093 is also called as a differential measurement meter, and the timing measurement unit is also called as a time measurement unit 1094, timing measurement unit.

Thus, the master circuit board 102 has more than 48 of the load programmable modules 1091, each of the load programmable modules 1091 including, for example, 1 of the load programmable units 1092, 1 of the differential instrument channels 1093, and 1 of the time measurement units 1094.

The load programmable unit 1092 is shown in functional block diagram form in fig. 11.

The differential meter channel 1093 is shown in functional block diagram form in fig. 11.

The time measurement unit 1094 is shown in functional block diagram form in fig. 11.

Programmable load plate

The programmable load board 104 includes a programmable inductive load 1041 and a programmable resistive load 1042. As shown in fig. 12, the programmable load board 104 includes, for example, 48 × 2 programmable inductive loads 1041 and 48 × 4 programmable resistive loads 1042. The programmable load loading board 104 is mainly provided with load inductance resistors with various parameter values, and these loads cannot be directly connected to the circuit of the chip to be measured all at once, and need to be accessed as required under the control of the program through the load programmable board card 109 to participate in the measurement.

The programmable load loading board 104 is connected to the circuit board through the main control board and the product test, and loads the programmable inductor and the programmable resistor required for the test as loads into the measurement, so that at present, 48 parallel test stations are provided, and an inductive load 1041 and a resistive load 1042 of each test station are provided at the same time. The product test connection circuit board is also referred to as said contact circuit board 101.

As shown in fig. 12, each test station is configured with a programmable connection load, with 4 standard resistors and 2 inductors on the load board, which can be connected to 4 different locations.

Control bit principle of 240-bit switch

As shown in fig. 13, the system provides 64 data bits, or control bits, or data bits. The 64 control bits are driven directly by the FPGA digital signal and the 64 control bits output a 0v or 3.3v signal, thus enabling the MOSFETs to drive the coils of the relay directly or possibly configured to drive the transceiver MSW05 described below.

The switch control module 108MSW05 is applied to control transceivers of 16 control channels with high voltage and high precision, and 16 independent solid state relays are packaged in an LQFP44 packaging module. The switch control module 108MSW05 may turn on/off each channel in various modes of a high speed immediate response type or a low speed delay type through a serial or parallel mode.

240 individual control bits may be provided and may be divided into 5 groups, controlled by 48 individual control bits.

The 240 switch control bits mean that the tester currently has 240 switch control bits to control 240 switches, the 240 control bits are composed of a plurality of MSW05 chips, and each MSW05 is provided with 16 MOS semiconductor switches.

The floating drive measurement source principle

The main control circuit board 102 includes a floating driver board card 107. As shown in fig. 14, the main control circuit board 102 includes, for example, 4 floating driver boards 107.

Each test station is equipped with 4 different floating drive sources.

Each floating drive source is digitally driven by an optically isolated and programmable floating voltage.

The floating drive source is connected to the first 4-bit digital channel.

Referring to the circuit schematic in fig. 14, wherein,

the grade DRV +/DRV-difference of the programmable high potential is as follows: 4-18V;

the level DRV +/DRV-difference of the programmable low potential is as follows: -5-2V and 0V;

the programmable output current precision is 50mA when outputting 300 mV.

Connection of digital channel of TIB circuit board and PPMU

The TIB circuit board, also referred to as the TIB test resource interface board 103, includes PPMUs and digital channels. As shown in fig. 15, the TIB test resource interface board 103 includes, for example, 64 PPMUs and 320 digital channels. The TIB test resource interface board 103 is installed on the main control board, and provides 2 PPMU analog output sources and 10 digital channel access for each test station.

Function of PPMU and description of its composition

Each PPMU can provide a voltage-current output channel source with 4-quadrant output;

the V is provided with output voltage and output current; outputting a certain frequency waveform; the function of measuring voltage and current;

the range of the output voltage and the measured voltage is +/-11.25V;

abnormal alarm is given when the output current and the measured current range is +/-5 uA +/-20 uA +/-200 uA +/-2 mA +/-60 mA;

v. providing a Kelvin measurement device connection;

external DGS connection;

each PPMU can be directly connected to the outputs and measurements of 5 digital channels;

working principle of digital channel

320 digital channels are directly controlled by FPGAs and embedded into the main control board by a TIB circuit board; 320 digital channels can be understood as 320 input and output ends, each input and output end only receives or sends a digital signal, 0 or 1, 0 bit and 0 volt low level are predefined, 1 is 5.5 volt high level and 50mA current, and a time sequence is added to complete signal input, wherein the predefined frequency of the time sequence can be more than 10 Mhz; the FPGA can directly read the signal record of the digital channel according to a predefined time sequence;

the functions are as follows: static programmable digital execution module

An output voltage range of √ 0V to 5.5V and providing a current of 50 mA;

v can provide output frequencies in excess of 10 MHz;

each channel provides storage space for a sequence of 2 million execution vectors;

providing a channel with an output or receiving mode;

providing DSIO for each station under parallel test, wherein the DSIO comprises 1 thousand execution vector output storage spaces and 1 thousand execution vector input storage spaces;

configuration for 48 parallel test stations:

v. provides the connection of 5 digital channels;

v. provides a connection for the test and output of 1 PPMU;

v. provides the output of PPMU and the output of 5 digital channels;

configuration for 32 parallel test stations:

the connection of V10 digital channels;

the output of the 2 PPMUs is connected with the measurement;

the output of each PPMU is directly connected to the output of 5 digital channels;

the output of the PPMU1 can be connected with digital channels 1-5;

the output of the bearing capacity PPMU2 can be connected with a digital channel 6-10;

the test head is connected with the structure of the product to be tested

As shown in fig. 16, a large number of probes 1051 are mounted on a carriage 1052, and contact a chip 113 to be tested and the product 900 to be tested on the test head 100 with the circuit board 101, so as to complete a test circuit, and the group of chips 113 to be tested is automatically replaced by the operating machine 111, thereby completing a test of a large number of products.Said carriage 1052 also being called a strip Chip tray 112

Testing the principle of how the contact circuit board of a product is connected to the product

As shown in fig. 17, the contact circuit Board 101 or Family Board is designed with copper foil printed circuit contacts that are simultaneously connected to 96 products.

The copper foil printed circuit contact points are not directly connected with a product to be tested, but are connected with a chip to be tested through a probe array and a probe array seat.

Each chip to be tested is combined by the probes 1051, and the electrode with large current provides a certain amount of the probes 1051 to contact the chip pins.

Description of parallel and group testing and group ping-pong testing

As shown in FIG. 18, when 96 chips were simultaneously placed in the test in 96 test stations, the 96 test stations were divided into two groups, group A and group B, each of which was 48 test stations, and parallel tests were performed between the groups

The odd test stations are in group A, such as in FIG. 18 labeled yellow or the second and fourth rows, and the even test stations are in group B, such as in FIG. 18 labeled blue or the first and third rows

Performing ping-pong test on the group A and the group B, and controlling the group B to be tested through a relay after the group A is finished

VTH and IDSS were divided into two groups of tests.

Under the limitation of the maximum current 100A of the tester, the test of VDSON is divided into 8 groups between two groups, each group consists of 6 test stations, and the total number is 16.

Group a test station: group B test stations:

panel a 1: 1357911 subgroup B1: 24681012

Panel a 2: 131517192123 subgroup B2: 141618202224

Panel a 3: 252729313335 subgroup B3: 262830323436

Panel a 4: 373941434547 subgroup B4: 384042444648

Panel a 5: 495153555759 subgroup B5: 505254565860

Panel a 6: 616365676971 subgroup B6: 626466687072

Panel a 7: 737577798183 subgroup B7: 747678808284

Panel A8: 858789919395 subgroup B8: 868890929496

Hardware grouping connection mode of external high-power voltage current source Beats

How 1 external said high power voltage current sources Beasts are allocated to 96 test stations:

as shown in fig. 19, the output of the external high-power voltage current source, tables, is distributed by a multi-channel load programming module connected to the main control board through a cable to 48 current output channels, wherein channel 1 is distributed to test stations No. 1 and No. 2, 2 stations are distributed under the control of the ping- pong switch bits 97, 145, similarly, stations No. 95 and No. 96 are distributed by channel 35 under the control of the ping-pong switch bit, and then 48 outputs are distributed to 96 stations to be completed in the test, specifically, the distribution refers to fig. 47.

The control of the ping-pong switch bit can be controlled by 48/2-24, 48/4-12 groups for sequential and parallel operation to complete the number of groups inside and outside.

Since the control of the ping-pong switch bits can be divided into 2 or 4 subgroups within each group, e.g., 48/2-24, or 48/4-12, parallel testing is performed within the subgroups and sequential testing is performed between the subgroups.

The multi-path Load programming module is also called a Multiplexer Load PROG, and the Current output channel is also called a Current out channel.

Hardware grouping connection mode of digital channel

How 320 digital channels are allocated to 96 test stations:

as shown in fig. 20, for example, a tester has 320 digital channels in total, and 240 digital channels are grouped: the digital channel groups #1 to #5 are firstly allocated to the test station No. 1 to test one chip and then switched to the test station No. 2 to test another chip under the control of the switch control bits 97 and 145; according to the mode, 240 digital channels are divided into 240/5, 48 groups of digital channels meet the chip test of 96 test stations by ping-pong mode switching, and if the ping-pong mode switching is not carried out, 96 multiplied by 5 near 480 digital channels are needed, so that for the current design of 96 test stations, 240 digital channels can meet the requirement, and the hardware resources of 240 digital channels are saved; the specific allocation refers to fig. 47.

The test principles and methods are described in detail below with an example of parallel testing of power MOS devices, i.e., PowerMOS chips.

As shown in fig. 24 and 25, 96 power MOS devices are mounted on a lead frame, all electrodes are connected before parallel testing, and S and G electrodes are cut and separated before parallel testing, and as can be seen from the following drawings, in a bar chip array, D electrodes of all chips are connected together, and G electrodes and S electrodes are separated independently:

semiconductor power devices, also known as power semiconductor devices, have been previously referred to as power electronic devices, and simply, are semiconductor devices that perform power processing and have the capability of handling high voltages and large currents.

With the rapid development of new power semiconductor devices represented by power MOSFET devices, the power semiconductor devices are now very wide and are widely used in 4C industries represented by computers, traffic, consumer electronics, and automotive electronics.

Measuring the value of IDSS

The test conditions are that Vgs is 0[ V ], Vds is Nom.BVdss [ V ];

as shown in fig. 21, the working principle of the test is that the leakage current between the D pole and the S pole is measured, if the Vgs is 0V, and the D pole and the S pole are not conducted, the reverse leakage current of the diode, the DCS meter is connected in series between the S pole and the ground, and the leakage current is measured when the source forward voltage connected from the D pole is 15V and 30V, and the value is less than 2.5 μ a, 0.8 μ a is a normal value, otherwise, the leakage current is a defective product.

FIG. 21 shows a schematic diagram 211 of a single event test IDSS; fig. 21 shows a schematic diagram 212 of a multi-grain parallel test IDSS.

Measuring the value of VGS (th)

As shown in fig. 22, the working principle was tested: when the D pole and the G pole are closed by a switch SW14 and are shorted to the ground, and the test condition Vgd is 0V, a DCS current source is connected in series with the S pole, the voltage value of the S pole to the ground is measured on a voltmeter of the DCS current source when the source current is respectively Id is 250 mu A/Id is 20 mu A, and the voltage value is between 1.05V and 2.4V when the voltage range is 250 mu A, and is a normal chip value when the voltage range is 0.88V and 1.89V when the voltage range is 20 mu A. Otherwise, it is a defective product. Because there are only 48 DCS, only 48 DCS can be tested in parallel at a time, and 96 DCS need to be tested in a ping-pong test mode for all 96 DCS.

FIG. 22 shows a schematic diagram 221 of a single event test VGS (th); FIG. 22 shows a schematic diagram 222 of a multiple parallel test VGS (th).

Measuring VDSON-related parameters

Under the test conditions that Vgs is 10V and G pole opening voltage of 5.0V, D pole and S pole conduction current is measured at 8.5A and 2.0A, and D pole and S pole voltage drop is measured.

As shown in fig. 23, a PPMU source is connected between a G pole and an S pole to provide 10V and 5V voltages, a D pole is connected to a cast current source, a load programmable module 1091 is connected between the S pole and a ground line in series to simulate in a load connection state, a differential table of the load programmable module 1091 is used to measure a voltage drop when the D pole and the S pole are conducted and a passing current, when the current is 8.5A, the voltage drop measured by the differential table when the PPMU is loaded with 5V is lower than 415mV, and the current is between 8 and 9A, and is higher than 213mV and lower than 400mV at 10V; when the current is 2A, the PPMU is loaded with 10V, the voltage drop measured by the difference table is lower than 100mV, and the current between 1.4A and 2.6A is a normal chip, otherwise, the chip is a defective product.

FIG. 23 shows a schematic diagram 231 of a single event test VDSON; fig. 23 shows a schematic 232 of a multi-grain parallel test VDSON.

FIG. 45 shows a sample list of parallel test results for the above three electrical parameters for 96 test stations. Fig. 46 is a test result determination list of the three electrical parameters.

Based on the above inventive concept, referring to fig. 1 to 5, according to a first embodiment of a parallel test method of semiconductor power devices of the present invention, the parallel test method is used for performing a parallel test of semiconductor power devices on an entire lead frame by a chip package test apparatus in a package test process. Differs from the prior art at least in that: in the invention, in the packaging test procedure, the semiconductor power device is not completely cut and separated from the lead frame, and the chip packaging test device can simultaneously measure a plurality of semiconductor power devices; in the prior art, the semiconductor power devices are completely cut and separated from the lead frame in the final packaging test station of the chip packaging process, and the chip packaging test device can only measure the semiconductor power devices one by one.

As shown in fig. 2, 3 and 5, the semiconductor power device is a molded or electroplated or baked packaging unit distributed on the lead frame. As described above, the semiconductor power device is, for example, a PowerMOS chip or device.

Referring to fig. 16, the chip package testing apparatus or the parallel testing device of the semiconductor power device includes the test head 100, the test support 110, and the operating machine 111, wherein the test head 100 includes the contact circuit board 101, the main control circuit board 102, the TIB test resource interface board 103, the programmable load loading board 104, and the probe contact apparatus 105, the main control circuit board 102 further includes the DCS integration module circuit board 106 and the switch control module 108, the test support 110 is configured to support and fix the test head 100 and ensure the relative positioning between the operating machine 111 and the test head 100, and the operating machine 111 includes a strip chip tray 112. Fig. 6-16 schematically illustrate the function, structure, and operation of the components of the apparatus for parallel testing of semiconductor power devices, and are described in the relevant text in the above section of the inventive concept.

As shown in fig. 16, the probe contacting device 105 includes a plurality of the probes 1051 and the carriage 1052, wherein the probes 1051 are mounted on the carriage 1052. Preferably, the probe 1051 or the contact probe 1051 includes a conductive needle and a conductive needle, wherein a compression spring is disposed in a hollow cavity of the conductive needle, the conductive needle is disposed at two ends of the conductive needle, and the length of the probe 1051 can be changed by the compression spring so as to adapt to the test of different types of semiconductor power devices.

As shown in fig. 17, the contact circuit board 101 has copper foil printed circuit contacts that are electrically connected to all chip pins of all package units on the lead frame simultaneously. It will be appreciated that for different types of chips, different ones of the contact circuit boards 101 are required in order to design copper foil printed circuit contacts corresponding to the pins of the chip.

Referring to fig. 1 to 6, the parallel test method includes the steps of:

pre-rib-cutting step S1: and cutting and separating part of the chip pins of each packaging unit from the lead frame, and keeping the other part of the chip pins of each packaging unit connected with the lead frame. Fig. 24 is a schematic diagram showing a leadframe after a PowerMOS chip is molded, in which all pins of the PowerMOS chip are connected to the leadframe without being cut. Fig. 25 is a schematic diagram showing a lead frame after the PowerMOS chip is molded, wherein the G-pole pin and the S-pole pin of the PowerMOS chip are cut and separated and are not connected with the lead frame. It is understood that, since the electrodes or pins of different types of chips may be different, which pins need to be cut and separated in the pre-rib cutting step S1 needs to be determined in advance according to the general concept of test circuit design.

Chip fixing step S2: the lead frame is fixedly mounted on a bar type chip tray 112 of the operating machine 111. As shown in fig. 16, the strip chip tray 112 can be precisely moved in two dimensions within the operation plane of the operation table 111 so as to be aligned with the probe array of the probe contacting device 105.

The probe 1051 alignment step S3: a plurality of the probes 1051 of the probe contact device 105 are combined into a probe array, the spacing dimension between the probes 1051 is matched with the spacing dimension between the chip pins of the package unit on the lead frame in the transverse and longitudinal directions, and the second end of each of the probes 1051 is electrically connected with a corresponding copper foil printed circuit contact point of the contact circuit board 101. It is understood that each individual pin of the semiconductor power device is electrically connected to at least one of the probes 1051, and the pins of the semiconductor power device connected to the lead frame may share one or more of the probes 1051, or each pin is electrically connected to at least one of the probes 1051.

Loop establishment step S3: the probe 1051 is in a platform contact manner and is electrically connected to the chip pins of the package units, so that all the chip pins of all the package units on the lead frame are electrically connected to the first end of the corresponding probe 1051, and a test loop is established for each semiconductor power device on the lead frame, and in the test head 100, the test loop of each semiconductor power device corresponds to one test station. It will be appreciated that, as shown in fig. 16, the alignment of the electrical connections between the probe contact devices 105 and the contact circuit board 101 remains fixed throughout the test, and the contact circuit board 101 does not need to be replaced as long as the type of the strip chips 113 to be tested is not replaced. The probe contact device 105 is moved by controlling the operating platform 111 such that the first ends of the probes 1051 are electrically connected to the corresponding chip pins, thereby electrically connecting all the chips on the lead frame to the test circuit. Preferably, the frame image positioning system described above is used for automatically positioning and aligning the probe array with all chip pins of all package units on the lead frame. Preferably, the platform contact is achieved by the carriage 1052, which can assemble the probe array into a platform form, and then by moving the lead frame, all chip pins are integrally electrically contacted with the corresponding probes 1051 on the carriage 1052 in the platform form.

Device grouping step S4: dividing the test stations with the established test loops into two groups: the test system comprises a group A test station and a group B test station, wherein the serial number of the group A test station is an odd number and is equal to (2 xI-1), the serial number of the group B test station is an even number and is equal to (2 xI), and I is larger than or equal to 1. As shown in fig. 18, 24, and 25, for a lead frame having 96 package units or PowerMOS chips, four rows of the PowerMOS chips in fig. 24 are numbered as indicated by the reference numerals in fig. 18, wherein the 2 nd and 4 th rows are a group a PowerMOS chips corresponding to a group a test station, and the 1 st and 3 rd rows are B group PowerMOS chips corresponding to a group B test station.

Parallel test step S5: the switch control bit of the switch control module 108 controls the group a test stations to be in a to-be-tested state according to a ping-pong test mode, and the test head 100 performs parallel test on the semiconductor power devices on the group a test stations; after the group a test is completed, the switch control bit of the switch control module 108 controls the group B test station to be in a state to be tested according to a ping-pong test mode, and the test head 100 performs a parallel test on the semiconductor power devices on the group B test station. It will be appreciated with reference to figures 18, 19 that the resources required by the various test stations are equally well allocated and utilised in favour of the ping-pong switch bit. For example, as shown in fig. 21 and 22, the measurement of the electrical parameter IDSS of the PowerMOS device and the measurement of the electrical parameter VTH of the PowerMOS device described herein are to divide 96 PowerMOS chips into two groups, each group includes 48 PowerMOS chips, and after the 48 PowerMOS chips of the group a are tested in parallel, the dynamic combination of the 48 PowerMOS chips of the group a is performed through the program control circuit, and the ping-pong test conversion is realized by controlling the ping-pong switch bit, so that the 48 PowerMOS chips of the group B are tested in parallel at the same time.

The parallel testing method of the semiconductor power device achieves the technical effect of testing the semiconductor power device on the whole lead frame at one time, and greatly improves the production testing efficiency.

Preferably, the device grouping step S4 further includes the sub-steps of:

group division substep S21: according to the magnitude of the test current or test voltage required by the semiconductor power device and the maximum current or voltage which can be borne by the test head 100, the group A test stations and the group B test stations are respectively divided into M groups, each group comprises N test stations, wherein the serial number of the group A test stations is an odd number and is equal to 2(I + j × N) -1, the serial number of the group B test stations is an even number and is equal to 2(I + j × N), I is the serial number of the test stations, j is the serial number of the group, I is not less than 1 and not more than N, j is not less than 0 and not more than M, M is not less than 0, and N is not less than 1. As described above with reference to fig. 18, 23, 24, 25, the testing of VDSON is divided into two groups of 8 subgroups each, each consisting of 6 test stations, for a total of 16 subgroups, subject to the maximum current 100A of the tester. That is, M is 8, N is 6, 1 ≦ i ≦ 6, 0 ≦ j ≦ 8, the test stations of the group A are odd numbered and equal to 2(i + j × 6) -1, and the test stations of the group B are even numbered and equal to 2(i + j × 6).

Instead of the parallel test step S5, the parallel test is performed as follows:

panel parallel test step S22: the switch control bit of the switch control module 108 controls the test head 100 to test the semiconductor power devices of each group according to a sequential test mode, and in each group, the switch control bit of the switch control module 108 respectively tests the semiconductor power devices belonging to the group a and the semiconductor power devices belonging to the group B in parallel according to a ping-pong test mode. As shown above, the 1 subgroup to the 8 subgroups were tested in sequence, and within each subgroup, all the PowerMOS chips of the j subgroup within the a group were simultaneously tested, and then switched to the B group in the ping-pong test mode, while all the PowerMOS chips of the j subgroup within the B group were simultaneously tested. That is, the a1 panel was tested concurrently, then switched in ping-pong test mode, the B1 panel was tested concurrently, the a2 panel was tested concurrently, then switched in ping-pong test mode, the B2 panel was tested concurrently, the A3 panel was tested concurrently, then switched in ping-pong test mode, the B3 panel was tested concurrently, … ….

The ping-pong test mode of the subgroups achieves the technical effect of conveniently and quickly testing the large-current parameters, such as VDSON, of 96 PowerMOS chips on the whole lead frame after one-time test installation is in place.

Preferably, referring to fig. 17, in case of testing the semiconductor power device using a large current, the probe contacting device 105 provides a certain number of the probes 1051 for each large current pin of the semiconductor power device, forms the combined probes 1051, and contacts the large current pins through the combined probes 1051. For example, fig. 17 shows that 6 probes 1051 are connected to the G-pole, 7 probes 1051 are connected to the D-pole, and 6 probes 1051 are connected to the S-pole of the PowerMOS chip, such a configuration ensures that the probes 1051 do not generate heat excessively when a large input current test is performed, and the current borne by each probe 1051 is within a normal range.

Preferably, referring to fig. 15, the main control circuit board 102 further includes a TIB board interface and a first connecting device, wherein,

the TIB board interface is configured to connect the TIB test resource interface board 103, where the TIB test resource interface board 103 includes a digital channel and a PPMU unit;

the first connecting device is used for connecting the main control circuit board 102, the digital channel and the PPMU unit.

The design of the circuit board in such a modularized manner ensures that the resource circuit board can be replaced according to different test requirements, for example, the TIB test resource interface board 103 shown in fig. 15 has 320 digital channels and 64 PPMU units, and such resource configuration can meet the parallel test requirement of a lead frame of 96 chips. For a lead frame of 240 chips, more resources are needed, and the TIB test resource interface board 103 with larger capacity needs to be replaced. The resources that the tester can provide include, but are not limited to: digital channel, PPMU unit, the floating drive measurement source 1071, the DCS module 1061, the load programmable module 1091, differential measurement table, the time measurement unit 1094, and the like.

Preferably, referring to fig. 13, the switch control module 108 includes a switch control bit capable of driving a micro-test transceiver chip having 16 programming control switches that can be individually programmed and controlled through a single wire protocol framework, and also capable of driving MOS semiconductor switches. It can be understood that the switch control bit has a ping-pong switch control function, and is a key component for implementing the ping-pong test.

Preferably, referring to fig. 11, the main control circuit board 102 includes the load programmable board 109, the load programmable board 109 includes the load programmable module 1091, and the load programmable module 1091 includes, for example, the load programmable unit 1092, the differential meter channel 1093, and the time measuring unit 1094. It will be appreciated that by means of the load programmable module 1091, as shown in fig. 21-23, 33, 37 and 40, through programming, resources can be dynamically allocated, thereby achieving the technical effect of testing the packaged units mounted in place at a time and testing the packaged units on the whole lead frame in parallel.

Preferably, referring to fig. 12, the programmable load board 104 includes a programmable inductive load 1041 and a programmable resistive load 1042;

the programmable load loading board 104 loads the programmable inductive load 1041 and the programmable resistive load 1042, which are required to be used in the test, as loads to be measured through the contact circuit board 101 and the main control circuit board 102, and provides the inductive load 1041 and the resistive load 1042 for each test station.

Such a configuration facilitates dynamic loading of physical components into the test circuit to meet different test requirements, so that the same test equipment can be used for a wider variety of chip tests.

Preferably, referring to fig. 14, the main control circuit board 102 further includes the floating driver board 107, and the floating driver board 107 includes the floating driver measurement source 1071, wherein the floating driver source is isolated by an optical coupler and digitally driven by a programmable floating voltage.

The configuration ensures that different voltage values can be provided for the circuit dynamically, and is beneficial to realizing the automation of the programming control test.

Preferably, referring to fig. 16, the probe contact means 105 further comprises a high temperature test heating means 114;

the parallel test method also comprises the following test steps:

high temperature test step 91: the high temperature test heating device 114 heats the lead frame to a certain temperature, and then performs the high temperature test again according to the parallel test step S5.

Such configuration is favorable for realizing performance test of the chip under a high-temperature working environment.

Preferably, referring to fig. 16, the parallel test method further includes the steps of:

a test strip replacing step 101: after the test of the chip 113 to be tested is completed, the operating machine 111 automatically replaces the next chip 113 to be tested.

The automatic loading mechanism of the lead frame of the operation machine table 111 and the frame image positioning system realize full-automatic parallel test, and are particularly suitable for a full-automatic chip packaging production line.

Preferably, referring to fig. 26, 27, 28, the semiconductor power device is a power MOS chip. The power MOS chip, i.e. the PowerMOS chip, is a preferred example of the present invention, and the method for testing the electrical parameters thereof, especially the testing of the electrical parameters IDSS, VTH, VDSON, is described in detail below.

Advantageously, referring to fig. 24-28, the plurality of semiconductor power devices are connected on a lead frame, wherein the S-pole and G-pole of each semiconductor power device are separated from the lead frame and the D-poles of all semiconductor power devices are connected together. It is understood that the connection of the D-poles of all the semiconductor power devices on the lead frame is considered according to the circuit design requirements of the main control circuit board 102. FIG. 29 is a schematic circuit diagram showing the test head 100 of the parallel test apparatus shown in FIG. 6 connected to a single PowerMOS chip to be tested; FIG. 30 shows a parallel test summary circuit schematic of a PowerMOS chip of a 96 test station; FIG. 31 shows another summary circuit schematic of parallel testing of a PowerMOS chip of a 96 test station; fig. 32 shows an abstraction of a parallel test circuit schematic for a PowerMOS chip of a 96 test station. In fig. 29 and 31, a pair of Force _ G and Sense _ G is used for Kelvin connection to ensure the accuracy of measurement, where Force _ G is used to connect the G pole of the chip to the driving end, and Sense _ G is used to connect the G pole of the chip to the sensing end.

Preferably, referring to fig. 21, the parallel test method of the semiconductor power device includes:

the test loop of the electrical parameter IDSS of the I-th power MOS chip is established as follows:

setting an S pole to be connected to the I-th DCS measuring instrument;

a switch for turning off the connection source of the G pole;

a switch for disconnecting the ground line of the G pole;

setting the D pole to be connected to the high-power voltage current source 300;

the measurement mode of the electrical parameter IDSS of the I-th power MOS chip is as follows:

setting a source output voltage reaching a D pole to be a first voltage value;

collecting data according to a determined time interval through the I-th DCS measuring instrument, and taking an average value, namely a measured first IDSS value;

setting the source output voltage reaching the D pole to be a second voltage value;

and acquiring data according to a determined time interval through the I-th DCS measuring instrument, and averaging to obtain a measured second IDSS value.

For a lead frame with 96 chips, wherein I is more than or equal to 1 and less than or equal to 48, the test head 100 of the invention has the capability of simultaneously providing 48 sets of test resources, so that the parallel test can be carried out by dividing the lead frame into a group A and a group B. For each power MOS chip to be tested, one set of test resources is needed, 48 sets of test resources are needed for testing 48 power MOS chips simultaneously, and 48 test loops are established simultaneously.

Referring to fig. 21, the first voltage value is, for example, 15 volts set for the 5 th marked line, and the second voltage value is, for example, 30 volts set for the 7 th marked line, and thus the first voltage value may also refer to the 351 th marked line of fig. 33, and the second voltage value may also refer to the 361 th marked line next to the 361 th marked line of fig. 33. It is understood that the first voltage value may be 10 volts or 20 volts and the second voltage value may be 20 volts or 40 volts according to the model specification of the semiconductor power device, and the first voltage value and the second voltage value may take any values as needed as long as they are feasible according to a product test scheme.

Referring to fig. 21, the calculation and measurement of the first IDSS value refer to the variable IDSS1_ c of the 6 th marked line, and the calculation and measurement of the second IDSS value refer to the variable IDSS2_ c of the 8 th marked line. Referring to fig. 33, the calculation and measurement of the first IDSS value refer to variable IDSS1_ c of the 361 th marked line, and the calculation and measurement of the second IDSS value refer to variable IDSS2_ c of the 362 th marked line. As described above, in the case where the first voltage value is set to 15V, if the measured first IDSS value is less than 2.5 μ a, and in the case where the second voltage value is set to 30V, if the measured second IDSS value is less than 0.8 μ a, the IDSS parameter of the semiconductor power device is a normal value, the semiconductor power device is good, and otherwise, the semiconductor power device is bad.

As shown in fig. 33-36, the technical effects of dynamically recombining the measurement circuit and controlling the ping-pong switch are achieved by programming, for example, a C + + language program, so that the parallel test effect of the ping-pong mode is achieved. For example, fig. 34 shows circuit changes controlled by program statement 341 databits (DCS _ TO _ GATE1), fig. 35 shows circuit changes controlled by program statement 351micro.

Preferably, referring to fig. 22, the parallel test method of the semiconductor power device includes:

the test loop of the electrical parameter VTH of the I-th power MOS chip is established as follows:

setting an S pole to be connected to the I-th DCS measuring instrument;

the switch of the ground line of the G pole is turned off through the switch control bit of the switch control module 108, so that the G pole is conducted to the ground;

the measurement mode of the electrical parameter VTH of the I-th power MOS chip is as follows:

setting a pin source current of the I-th DCS measuring instrument as a first current value;

acquiring data according to a determined time interval through the I-th DCS measuring instrument, and taking an average value to obtain a measured first VTH value;

setting the pin source current of the I-th DCS measuring instrument as a second current value;

and acquiring data according to a determined time interval through the I-th DCS measuring instrument, and averaging to obtain a measured second VTH value.

For a lead frame with 96 chips, wherein I is more than or equal to 1 and less than or equal to 48, the test head 100 of the invention has the capability of simultaneously providing 48 sets of test resources, so that the parallel test can be carried out by dividing the lead frame into a group A and a group B. For each power MOS chip to be tested, one set of test resources is needed, 48 sets of test resources are needed for testing 48 power MOS chips simultaneously, and 48 test loops are established simultaneously.

Referring to fig. 22, the first current value is, for example, 250 μ a of VTH1 in the table, and the second current value is, for example, 20 μ a of VTH2 in the table, so the first current value can also be understood with reference to the 385 th marked line source code of fig. 37, and the second current value can also be understood with reference to the 383 th marked line of fig. 37. It is understood that the first current value may be 200 μ a or 150 μ a and the second current value may be 10 μ a or 30 μ a according to the model specification of the semiconductor power device, and the first current value and the second current value may take any values as needed as long as they are feasible according to a product test scheme.

Referring to fig. 22, the first VTH value is calculated and measured as a reference variable VTH2, and the second VTH value is calculated and measured as a reference variable VTH 1. Referring to fig. 37, the calculation and measurement of the first VTH value refer to the variable VTH2 of the 386 th marked line, and the calculation and measurement of the second VTH value refer to the variable VTH1 of the 384 th marked line. As described above, in the case where the first current value is set to 250 μ a, if the voltage range of the measured first VTH value is between 1.05V and 2.4V, and in the case where the second current value is set to 20 μ a, if the voltage range of the measured second VTH value is between 0.88V and 1.89V, the VTH parameter of the semiconductor power device is a normal value, the semiconductor power device is good, and otherwise, it is bad.

FIG. 37 is a partial source code graphical table showing the test head 100 of the parallel test apparatus of FIG. 6 programming a dynamically composed test circuit for testing an electrical parameter VTH of a PowerMOS device; fig. 38 shows a circuit schematic of a hardware control response corresponding TO source code statement 381micro. FIG. 39 shows a chart of the results of testing the source codes Mysequence- > test (vth1), Mysequence- > test (vth2), and Mysequence- > test (deltaVth) of FIG. 37.

Preferably, referring to fig. 23, the parallel test method of the semiconductor power device includes:

the parallel test method of claim 2, wherein,

the (i, j) th test loop of the electrical parameter VDSON of the power MOS chip is established as follows:

connecting the D pole to the high power voltage current source 300;

connecting a PPMU source between a G pole and an S pole;

the switch of the grounding line of the G pole is switched off through the switch control bit of the switch control module 108, so that the G pole is disconnected to the ground;

(ii) said (i, j) th said load programmable module 1091 is connected in series between the S pole and ground;

the electrical parameter VDSON of the (i, j) th power MOS chip is measured as follows:

setting the current of the D pole as a third current value;

setting the voltage between the G pole and the S pole as a third voltage value;

simulating a load access state by the (i, j) th load programmable module 1091, and measuring a first voltage value VDSON when the D pole and the S pole are conducted by the (i, j) th load programmable module 1091;

setting the current of the D pole as a fourth current value;

setting the voltage between the G pole and the S pole as a fourth voltage value;

simulating a load access state by the (i, j) th load programmable module 1091, and measuring a second voltage value VDSON when the D pole and the S pole are conducted by the (i, j) th load programmable module 1091.

As described above with reference to fig. 18, 23, 24, 25, the testing of VDSON is divided into two groups of 8 subgroups each, each consisting of 6 test stations, for a total of 16 subgroups, subject to the maximum current 100A of the tester. That is, M is 8, N is 6, 1 ≦ i ≦ 6, 0 ≦ j ≦ 8, the test stations of the group A are odd numbered and equal to 2(i + j × 6) -1, and the test stations of the group B are even numbered and equal to 2(i + j × 6).

Referring to fig. 23, the third current value is, for example, 8.5A, the third voltage value is, for example, 5V, and the fourth current value is, for example, 2A, the fourth voltage value is, for example, 10V. It is understood that the third current value, the third voltage value, the fourth current value, and the fourth voltage may be set to any allowable values as long as the test flow and the product specification model permit. As shown in the data list of fig. 23, in the case where the third current value current is 8.5A and the third voltage value is 5V, the measured first voltage value VDSON of the semiconductor power device is lower than 415mV, and the current IDSON is between 8-9A; in the case where the third current value current is 8.5A and the third voltage value is 10V, the first voltage value VDSON is higher than 213mV and lower than 400 mV; when the fourth current value is 2A, the fourth voltage is 10V, the second voltage value VDSON is lower than 100mV, and the current IDSON is between 1.4A and 2.6A, the semiconductor power device is a normal chip, otherwise, the semiconductor power device is a defective product. Specific measurement embodiments can be seen in the source code shown in fig. 40. The measurement of the parameter current IDSON is not within the scope of the present invention and will not be described in detail.

FIG. 40 shows a graphical representation of a portion of the source code of the test head 100 of the parallel test apparatus shown in FIG. 6 for testing the electrical parameter VDSON of the PowerMOS device by programming the dynamically composed test circuit; FIG. 41 shows a circuit schematic of a hardware control response corresponding to a portion of the SOURCE code of FIG. 40, e.g., statement 401micro.DCS _ MP.Pins ("SOURCE _ dcs"). VRange (VRange10), statement 402micro.LP.Pins ("SOURCE _ lp"). CONNECT (Connection: Connection _), statement 403micro.DCS _ MP.Pins ("SOURCE _ dcs"). CONNECT (DCSConnectSENSE), statement 4404micro.Beast.Pins ("DRAIN _ best"). Voltage (5), statement 405micro.Connectivity.SetDatabit (1,8, Databit on); FIG. 42 is a table showing the maximum load current and other parameters for the test head 100 of the parallel test apparatus of FIG. 6, wherein the test head 100 is capable of withstanding 4 volts max at 40 volts and 200 amps max; FIG. 43 is a chart showing test results for the source code of FIG. 40; FIG. 44: another circuit schematic of the hardware control response of the portion of source code corresponding to fig. 40, which gives a schematic illustration of the program source code and the circuit dynamic control, can be viewed by enlarging the view, or asking the applicant for the original high definition map.

Based on the parallel test method and the parallel test equipment for the semiconductor power device, the invention can complete the measurement of more than 100 electrical parameters of the PowerMOS chip through program control very quickly, efficiently and fully automatically, thereby comprehensively evaluating the yield of the PowerMOS chip.

Therefore, the parallel testing method and the parallel testing equipment for the semiconductor power devices can be used for a fully-automatic chip packaging production line, particularly a fully-automatic semiconductor power device packaging production line, and the production efficiency is improved to the utmost extent.

According to an embodiment of the packaging method of the semiconductor power device of the present invention, referring to fig. 1, the packaging method includes the following steps:

loading step S1601: attaching the wafer to the blue film;

a cutting step S1602: cutting the wafer into chips;

attachment step S1603: bonding the chip on a lead frame;

wire bonding step S1604: connecting the welding points of the chip and the corresponding pins of the lead frame together by using conductive wires in a welding mode;

a molding step S1605: encapsulating the chip by using epoxy resin according to a molding mode to form a molded body;

strip parallel test step S1606: testing semiconductor power devices on the lead frame according to the parallel test method of any one of claims 1 to 10;

a shear molding step S1607: cutting and separating the residual pins of the semiconductor power device from the lead frame at a cutting and forming station, and pressing and forming the pins of the semiconductor power device to form an independent semiconductor power device;

a packing step S1608: the semiconductor power device is packed in a tube or a packing roll for finished product packing.

The technical scheme is also suitable for the full-automatic production line of other chips.

Specifically, as shown in fig. 1, the packaging method of the semiconductor power device includes the steps of:

loading step S1701: attaching the wafer to the blue film;

a cutting step S1702: cutting the wafer into chips;

attachment step S1703: bonding the chip on a lead frame;

wire bonding step S1704: connecting the welding points of the chip and the corresponding pins of the lead frame together by using conductive wires in a welding mode;

molding step S1705: encapsulating the chip by using epoxy resin according to a molding mode to form a molded body;

post-curing step S1706: carrying out thermosetting treatment on the mold sealing body;

electroplating step S1707: electroplating the lead frame to form a packaging unit;

baking step S1708: carrying out baking heat treatment on the packaging unit;

marking step S1709: marking a unique two-dimensional identification code on the lead frame, wherein the two-dimensional identification code and corresponding longitudinal and transverse position coordinates are used as unique information marks of the semiconductor power device corresponding to the packaging unit, and the semiconductor power device has the corresponding longitudinal and transverse position coordinates on the lead frame;

strip parallel test step S1710: testing chips on the lead frame according to the parallel test method of semiconductor power devices according to any one of claims 1 to 10;

result uploading step S1711: the test result of the semiconductor power device with the unique information mark is uploaded to a server and used for a laser printing station, namely a chip good product printing station;

good product printing step S1712: the lead frame is arranged at the laser printing station, and laser printing is carried out on a good product according to the test result of the server;

a shear molding step S1713: cutting and separating the residual pins of the semiconductor power device from the lead frame at a cutting and forming station, and pressing and forming the pins of the semiconductor power device to form an independent semiconductor power device;

a leakage test step S1714: carrying out a quick test item test on the leakage on-off part of the semiconductor power device on a packaging machine;

appearance testing step S1715: carrying out appearance detection on the semiconductor power device;

a packaging step S1716: the semiconductor power device is packed in a tube or a packing roll for finished product packing.

The packaging method of the semiconductor power device is particularly suitable for full-automatic packaging and testing of the PowerMOS chip, and the production efficiency of the packaging method is greatly improved compared with that of the prior art.

The foregoing detailed description of preferred or specific embodiments of the invention has been presented. It should be understood that numerous modifications and variations can be devised by those skilled in the art in light of the present teachings without departing from the spirit and scope of the invention. Therefore, the technical solutions available to those skilled in the art through logic analysis, reasoning and limited experiments based on the design concept of the present invention should be within the scope of the present invention and/or the protection scope defined by the claims.

Claims (17)

1. A parallel test method of semiconductor power devices for performing parallel test of semiconductor power devices on an entire lead frame by a chip package test apparatus in a package test process,

the semiconductor power devices are molded packaging units distributed on the lead frame;

the chip packaging test device comprises a test head (100), a test support (110) and an operating machine table (111), wherein the test head (100) comprises a contact circuit board (101), a main control circuit board (102), a TIB test resource interface board (103), a programmable load loading board (104) and a probe contact device (105), the main control circuit board (102) further comprises a DCS integrated module circuit board (106) and a switch control module (108), the test support (110) is used for supporting and fixing the test head (100) and ensuring the relative positioning between the operating machine table (111) and the test head (100), and the operating machine table (111) comprises a strip type chip tray (112);

the probe contacting device (105) comprises a plurality of probes (1051) and a carriage (1052), wherein the probes (1051) are mounted on the carriage (1052);

the contact circuit board (101) is provided with copper foil printed circuit contact points which are electrically connected with all chip pins of all packaging units on the lead frame at the same time;

the method is characterized in that: the parallel test method comprises the following steps:

pre-rib-cutting step S1: cutting and separating a part of chip pins of each packaging unit from the lead frame, and keeping the other part of chip pins of each packaging unit connected with the lead frame;

chip fixing step S2: fixedly mounting the lead frame on a strip type chip tray (112) of the operating machine table (111);

the probe (1051) alignment step S3: forming a plurality of the probes (1051) of the probe contact device (105) into a probe array, wherein the spacing dimension between the probes (1051) is matched with the spacing dimension between chip pins of a packaging unit on the lead frame in the transverse direction and the longitudinal direction, and electrically connecting the second end of each probe (1051) with a corresponding copper foil printed circuit contact point of the contact circuit board (101);

loop establishment step S3: the probe (1051) adopts a platform contact mode and is electrically connected with the chip pins of the packaging units, so that all the chip pins of all the packaging units on the lead frame are electrically connected with the first end parts of the corresponding probe (1051), a test loop is established for each semiconductor power device on the lead frame, and the test loop of each semiconductor power device corresponds to one test station in the test head (100);

device grouping step S4: dividing the test stations with established test loops into two groups: the test system comprises a group A test station and a group B test station, wherein the serial number of the group A test station is an odd number and is equal to (2 xI-1), the serial number of the group B test station is an even number and is equal to (2 xI), and I is more than or equal to 1;

parallel test step S5: the switch control bit of the switch control module (108) controls the group A test stations to be in a state to be tested according to a ping-pong test mode, and the test head (100) performs parallel test on the semiconductor power devices on the group A test stations; after the group A test is finished, the switch control bit of the switch control module (108) controls the group B test stations to be in a state to be tested according to a ping-pong test mode, and the test head (100) performs parallel test on the semiconductor power devices on the group B test stations.

2. The parallel test method of semiconductor power devices according to claim 1, characterized in that: the device grouping step S4 further includes the sub-steps of:

group division substep S21: according to the magnitude of test current or test voltage required by the semiconductor power device and the maximum current or voltage capable of being borne by the test head (100), the group A test stations and the group B test stations are respectively divided into M groups, each group is provided with N test stations, wherein the serial number of the group A test stations is an odd number and is equal to 2(I + j × N) -1, the serial number of the group B test stations is an even number and is equal to 2(I + j × N), wherein I = (I + j × N), I is the serial number of the test stations, j is the serial number of the group, I is more than or equal to 1 and less than or equal to N, j is more than or equal to 0 and less than or equal to M, M is more than or equal to 0, and N is more than or equal to 1;

instead of the parallel test step S5, the parallel test is performed as follows:

panel parallel test step S22: and the switch control bit of the switch control module (108) controls the test head (100) to test the semiconductor power devices of each subgroup according to a sequential test mode, and in each subgroup, the switch control bit of the switch control module (108) respectively tests the semiconductor power devices belonging to the group A and the semiconductor power devices belonging to the group B in parallel according to a ping-pong test mode.

3. The parallel test method of semiconductor power devices according to claim 2, characterized in that: in the case of testing the semiconductor power device using a large current, the probe contacting device (105) provides a certain number of the probes (1051) for each large current pin of the semiconductor power device, forms a combination of the probes (1051), and contacts the large current pin through the combination of the probes (1051).

4. The parallel test method of semiconductor power devices according to claim 1, characterized in that: the main control circuit board (102) further comprises a TIB board card interface and a first connecting device, wherein,

the TIB board card interface is used for connecting the TIB test resource interface board (103), and the TIB test resource interface board (103) comprises a digital channel and a PPMU unit;

the first connecting device is used for connecting the main control circuit board (102), the digital channel and the PPMU unit.

5. The parallel test method of semiconductor power devices according to claim 1, characterized in that: the switch control module (108) comprises a switch control bit, wherein the switch control bit can drive a micro-test transceiver and can also drive an MOS semiconductor switch, a micro-test transceiver chip is provided with 16 programming control switches, and the programming control switches can be individually programmed and controlled through a single-wire protocol framework.

6. The parallel test method of semiconductor power devices according to claim 1, characterized in that: the main control circuit board (102) comprises a load programmable board card (109), the load programmable board card (109) comprises a load programmable module (1091), and the load programmable module (1091) comprises a load programmable unit (1092), a differential instrument channel (1093) and a time measuring unit (1094).

7. The parallel test method of semiconductor power devices according to claim 1, characterized in that: the programmable load board (104) comprises a programmable inductive load (1041) and a programmable resistive load (1042);

the programmable load loading board (104) loads the programmable inductive load (1041) and the programmable resistive load (1042) required by the test as loads into the measurement through the contact circuit board (101) and the main control circuit board (102), and provides the inductive load (1041) and the resistive load (1042) for each test station.

8. The parallel test method of semiconductor power devices according to claim 1, characterized in that: the main control circuit board (102) further comprises a floating drive board card (107), the floating drive board card (107) comprises a floating drive measurement source (1071), wherein the floating drive measurement source is isolated by an optical coupler and is digitally driven by programmable floating voltage.

9. The parallel test method of semiconductor power devices according to claim 1, characterized in that: the probe contact device (105) further comprises a high temperature test heating device (114);

the parallel test method also comprises the following test steps:

high temperature test step 91: the high-temperature test heating device (114) heats the lead frame to a determined temperature, and then the high-temperature test is carried out again according to the parallel test step S5.

10. The parallel test method of semiconductor power devices according to claim 1, characterized in that: the parallel test method also comprises the following steps:

a test strip replacing step 101: after the test of the strip type chip (113) to be tested is finished, the operating machine table (111) automatically replaces the next strip type chip (113) to be tested.

11. The parallel test method of semiconductor power devices according to any of claims 1 to 10, characterized in that: the semiconductor power device is a power MOS chip.

12. The parallel test method of semiconductor power devices according to claim 11, characterized in that: the semiconductor power devices are connected to a lead frame, wherein the S pole and the G pole of each semiconductor power device are separated from the lead frame, and the D poles of all the semiconductor power devices are connected together.

13. The parallel test method of semiconductor power devices according to claim 12, characterized in that: the test loop of the electrical parameter IDSS of the I-th power MOS chip is established as follows:

setting an S pole to be connected to the I-th DCS measuring instrument;

a switch for turning off the connection source of the G pole;

a switch for disconnecting the ground line of the G pole;

setting the D pole to be connected to a high-power voltage current source (300);

the measurement mode of the electrical parameter IDSS of the I-th power MOS chip is as follows:

setting a source output voltage reaching a D pole to be a first voltage value;

collecting data according to a determined time interval through the I-th DCS measuring instrument, and taking an average value, namely a measured first IDSS value;

setting the source output voltage reaching the D pole to be a second voltage value;

and acquiring data according to a determined time interval through the I-th DCS measuring instrument, and averaging to obtain a measured second IDSS value.

14. The parallel test method of semiconductor power devices according to claim 12, characterized in that:

the test loop of the electrical parameter VTH of the I-th power MOS chip is established as follows:

setting an S pole to be connected to the I-th DCS measuring instrument;

turning off the switch of the grounding wire of the G pole through a switch control bit of the switch control module (108) so that the G pole is conducted to the ground;

the measurement mode of the electrical parameter VTH of the I-th power MOS chip is as follows:

setting a pin source current of the I-th DCS measuring instrument as a first current value;

acquiring data according to a determined time interval through the I-th DCS measuring instrument, and taking an average value to obtain a measured first VTH value;

setting the pin source current of the I-th DCS measuring instrument as a second current value;

and acquiring data according to a determined time interval through the I-th DCS measuring instrument, and averaging to obtain a measured second VTH value.

15. The parallel test method of semiconductor power devices according to claim 12, characterized in that:

the parallel test method of claim 2, wherein,

the (i, j) th test loop of the electrical parameter VDSON of the power MOS chip is established as follows:

connecting the D pole to a high power voltage current source (300);

connecting a PPMU source between a G pole and an S pole;

disconnecting the switch of the grounding wire of the G pole through a switch control bit of a switch control module (108) so that the G pole is disconnected to the ground;

(ii) connecting the (i, j) th load programmable module (1091) in series between the S pole and the ground;

the electrical parameter VDSON of the (i, j) th power MOS chip is measured as follows:

setting the current of the D pole as a third current value;

setting the voltage between the G pole and the S pole as a third voltage value;

simulating a load access state through the (i, j) th load programmable module (1091), and measuring a first voltage value VDSON when a D pole and an S pole are conducted by using the (i, j) th load programmable module (1091);

setting the current of the D pole as a fourth current value;

setting the voltage between the G pole and the S pole as a fourth voltage value;

and simulating a load access state through the (i, j) th load programmable module (1091), and measuring a second voltage value VDSON when the D pole and the S pole are conducted by using the (i, j) th load programmable module (1091).

16. The packaging method of the semiconductor power device is characterized in that: the packaging method comprises the following steps:

loading step S1601: attaching the wafer to the blue film;

a cutting step S1602: cutting the wafer into chips;

attachment step S1603: bonding the chip on a lead frame;

wire bonding step S1604: connecting the welding points of the chip and the corresponding pins of the lead frame together by using conductive wires in a welding mode;

a molding step S1605: encapsulating the chip by using epoxy resin according to a molding mode to form a molded body;

strip parallel test step S1606: testing semiconductor power devices on the lead frame according to the parallel test method of any one of claims 1 to 10;

a shear molding step S1607: cutting and separating the residual pins of the semiconductor power device from the lead frame at a cutting and forming station, and pressing and forming the pins of the semiconductor power device to form an independent semiconductor power device;

a packing step S1608: the semiconductor power device is packed in a tube or a packing roll for finished product packing.

17. The packaging method of the semiconductor power device is characterized in that: the packaging method comprises the following steps:

loading step S1701: attaching the wafer to the blue film;

a cutting step S1702: cutting the wafer into chips;

attachment step S1703: bonding the chip on a lead frame;

wire bonding step S1704: connecting the welding points of the chip and the corresponding pins of the lead frame together by using conductive wires in a welding mode;

molding step S1705: encapsulating the chip by using epoxy resin according to a molding mode to form a molded body;

post-curing step S1706: carrying out thermosetting treatment on the mold sealing body;

electroplating step S1707: electroplating the lead frame to form a packaging unit;

baking step S1708: carrying out baking heat treatment on the packaging unit;

marking step S1709: marking a unique two-dimensional identification code on the lead frame, wherein the two-dimensional identification code and corresponding longitudinal and transverse position coordinates are used as unique information marks of the semiconductor power device corresponding to the packaging unit, and the semiconductor power device has the corresponding longitudinal and transverse position coordinates on the lead frame;

strip parallel test step S1710: testing chips on the lead frame according to the parallel test method of semiconductor power devices according to any one of claims 1 to 10;

result uploading step S1711: uploading the test result of the semiconductor power device with the unique information mark to a server for a laser printing station, namely a chip good product printing station;

good product printing step S1712: the lead frame is arranged at the laser printing station, and laser printing is carried out on a good product according to the test result of the server;

a shear molding step S1713: cutting and separating the residual pins of the semiconductor power device from the lead frame at a cutting and forming station, and pressing and forming the pins of the semiconductor power device to form an independent semiconductor power device;

a leakage test step S1714: carrying out a quick test item test on the leakage on-off part of the semiconductor power device on a packaging machine;

appearance testing step S1715: carrying out appearance detection on the semiconductor power device;

a packaging step S1716: the semiconductor power device is packed in a tube or a packing roll for finished product packing.

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