CN109473361A - The parallel test method of semiconductor power device - Google Patents

Abstract

The present invention discloses the parallel test method of semiconductor power device, it is used in packaging and testing process, concurrent testing is carried out to the semiconductor power device on whole lead frame by chip package test device, the chip package test device includes measuring head (100), test bracket (110) and operation board (111).The parallel test method is the following steps are included: pre- rib cutting step S1, chip fixing step S2, probe alignment step S3, circuit establishment step S3, device is grouped step S4, concurrent testing step S5: the switch control position of the switch control module (108) carries out concurrent testing to the semiconductor power device on A group testing station by table tennis test pattern control；After completing the test of A group, the switch control position of the switch control module (108) carries out concurrent testing to the semiconductor power device on B group testing station by table tennis test pattern control.Invention achieves the technical effects for improving testing efficiency.

Description

The parallel test method of semiconductor power device

Technical field

The present invention relates to the test for being specially adapted for manufacturing or handle during semiconductor or solid state device or its component or The technical field (H01L 21/66) of measurement method or equipment, the invention particularly relates to the concurrent testing sides of semiconductor power device Method.

Background technique

The production procedure of existing traditional semiconductor power device is as shown in Figure 1:

Wafer load station by bonding wafer on blue film, full wafer wafer is cut into one by wafer cutting work station A independent chip, chip paste station again die bonding on frame, and the spacer-type solder joint on the chip on frame is used again The wire of high-purity is welded to connect on specified terminal pin on frame in chip bonding wire station, next entirety thermmohardening and Injection molding solidification, the chip after pin Trim Molding is electroplated are placed into after pipe the inside is gone gradation test non-defective unit printing packaging again.

Limitation description for test station simple grain chip testing traditional at present has following aspects:

(1) test speed of one single chip is slow, and cumulative production period chip delivery time is long.

(2) one single chip individual factors cause artificial interference factor quality risk to improve.

(3) the general golden finger of simple grain chip, which each requires individually to position, tests yields caused by easily leading to poor contact Decline, so that unnecessary cost be caused to waste.

A kind of method that patent document CN102253324B discloses application Parallel Test Architecture test hot carrier's effect, The following steps are included: S1, carrying out the test in individual devices stage, S2, the test for carrying out the stress loading stage, S3, alternately and repeatedly The test of step S1 and step S2, the electric parameters more repeatedly measured.MOS device hot carrier can be improved in the present invention Testing efficiency.

Patent document CN101702005B discloses a kind of parallel testing circuit with time correlation dielectric breakdown (TDDB). The detection time that the TDDB of transistor device can be greatly shortened using TDDB parallel testing circuit provided by the invention, is mentioned significantly The detection efficiency of high transistor device, effectively reduces production cost.

Patent document CN106788441A disclose it is a kind of drive MOS film resistor battle array DAC Array Control Circuit, including according to The secondary image data FIFO being connected, sequential control circuit and DAC array；DAC array is m × n structure, i.e., m DAC is one Group shares n group；M and n is the natural number not comprising 0；The data input pin of m DAC in each group is connected in parallel, n group DAC is respectively independent to be connected with sequential control circuit；The output end of DAC array with MOS film resistor battle array for being connected, DAC Number of channels it is consistent with the input end of analog signal quantity of MOS film resistor battle array, and correspond；Sequential control circuit is double Cushioning control mode；This it is a kind of drive MOS film resistor battle array DAC Array Control Circuit ensure that multichannel DAC data load Correctness improves the efficiency of image data refreshing, ensure that the reliability and real-time of image data DAC conversion.

Patent document CN101728293B discloses a kind of side of MOS transistor device gate oxide integrity (GOI) test Method, comprising the following steps: a test power supply is provided；Multiple MOS transistor devices to be measured are connected to the test power supply； Detect the MOS transistor device leakage current at this time；When the leakage current suddenly change, arrangement for detecting is opened, described in detection Failpoint in MOS transistor device.Using this method, reliability of the gate oxide can also carried out to MOS transistor device Test when, especially with parallel time relevant dielectric breakdown (TDDB) test when, can not only assess device under test Service life, and can synchronize and reflect in time and accurately the specific feelings of failpoint on MOS transistor device grid oxic horizon to be measured Condition, to carry out further failure analysis to device.

Patent document CN205670168U discloses a kind of voltage test device based on voltmeter head, including voltage access list Member, PLC unit and voltmeter head detect display unit, and voltage access unit includes the first direct current amplitude voltage input interface, the Two direct current amplitude voltage input interfaces and alternating voltage input interface；PLC unit includes toggle switch array, ship type switch arrays With air switch array；The voltmeter head detection display unit includes three line D.C. voltmeter head units, two line DC voltages Gauge outfit unit and two line A.C. voltmeter head units.The utility model tests voltage value to be measured, energy by voltmeter head unit Save development time and development cost；Entire test process is simple and clear, and image that the result is intuitive, testing time are short, accurately Rate is high, and this test device is compact-sized, easy to operate, and can meet the personalized testing requirement of user.

Patent document CN203084151U discloses a kind of table tennis test machine based on power remove technology, including multiple tests Head, and the energy supply control module being electrically connected with the measuring head；Utility model has the advantages that the test machine overcomes now Some needs to cut off a large amount of signals in alternately testing handoff procedure and influences testing efficiency based on the test machine of table tennis test philosophy With the defect of accuracy, testing efficiency is quickly and accuracy is high.

Patent document CN202903908U discloses a kind of PCB circuit board test equipment, more particularly, to a kind of Novel table tennis Mode vacuum double-station PCB circuit board test equipment.A kind of Novel table tennis mode vacuum double-station PCB circuit board test equipment, It is characterised in that it includes test equipment ontology (1), the upper cover jig (2) being arranged on test equipment ontology (1) and lower cover are controlled Have (3), described upper cover jig (2) one end and lower cover jig (3) one end are hinged；Handle is provided on the upper cover jig (2) (4)；Upper cover jig (2) rear is provided with laborsaving component；The laborsaving component and handle (4) are connected.Therefore, the utility model has Have the following advantages: rationally, structure is simple and completely practical for 1. designs；2. high degree of automation, while can be reduced operating personnel again Physical demands and fatigue, to improve 20% or more the accuracy that 30% or more working efficiency and product differentiate.

Patent document CN201637797U discloses a kind of test machine, including multiple measuring heads, further includes passing through data-interface The control module connecting with multiple measuring heads, control module receive test signal, indicate that multiple measuring heads are suitable by data-interface It is secondary to start to test, test result is sent to control module by data-interface after the completion of each measuring head test, to all surveys After examination head completes primary test, all test results are concentrated by control module and are exported.Above-mentioned test machine equipped with Multiple measuring heads, the every movement of wafer simultaneously contact once with probe card, can test the chip equal with measuring head quantity, relative to Every movement simultaneously contacts the test machine that can only once test the traditional single core built-in testing an of chip with probe card, substantially increases survey Try speed and efficiency.And only need to be tested with a probe station cooperation, it is carried out relative to needing to cooperate with two probe stations The test machine of table tennis test, can save cost.

The lead frame that patent document CN103311143B discloses a kind of chip package test device and its uses, the device It is fixedly arranged on contact mount including test processes unit, contact mount and multiple contact units, lead frame, contactor Unit is equipped with the probe array being made of multiple contact probes, encapsulates core in the size of space and lead frame between contact probe The size of space between piece pin matches on horizontal and vertical, and contact probe is set to contactor branch using contact with platform mode It is electrical connected on frame and with encapsulation chip pin, the quantity for encapsulating chip is contained contact probe quantity in contact probe array Integral multiple；Mould-injection road on lead frame includes multiple capsule shape slits, and the connection of two capsule shape slits is located at interval at core The position of piece pin, capsule shape slit are located at the position of chip end and at one-to-one relationships, and mould-injection road is located at lead frame The upper surface of frame.The present invention not only increases concurrent testing efficiency, and improves the utilization rate of lead frame and molding material.

Patent document CN101702005B disclose including multiple MOS transistor devices with time correlation dielectric breakdown Parallel testing circuit is not used to the parallel testing device of test MOS transistor device.

Patent document CN102253324B discloses the Parallel Test Architecture of MOS device hot carrier's effect, but without open The ping pong scheme of control circuit.

The method that patent document CN101728293B discloses MOS transistor device gate oxide integrity (GOI) test, but The ping pong scheme of control circuit is not disclosed.

Patent document CN106788441A discloses the DAC Array Control Circuit of driving MOS film resistor battle array, is not used to Test the parallel testing device of MOS transistor device.

Patent document CN201637797U, CN202903908U, CN203084151U, CN205670168U disclose control The ping pong scheme of circuit processed, but there is no the open tests to semiconductor power device.

The lead frame that patent document CN103311143B discloses a kind of chip package test device and its uses, but do not have The concrete structure design of open parallel testing device.

Summary of the invention

For overcome the deficiencies in the prior art, it is an object of the present invention to propose the parallel survey of semiconductor power device Method for testing can carry out concurrent testing to the device on whole frame, be applied to final encapsulation test step, easily carry out High and low, room temperature test, improves production capacity, reduces testing cost.

The second object of the present invention is to propose the parallel test method of semiconductor power device, by logic circuit and Program code controllably carries out the test mode of ping pong scheme, while the multiple work power devices of parallel testing, has made full use of The resource of limit, intelligently improves utilization efficiency.

For this purpose, the present invention proposes the parallel test method of semiconductor power device, it is used in packaging and testing process, leads to It crosses chip package test device and concurrent testing is carried out to the semiconductor power device on whole lead frame, wherein

The semiconductor power device is distributed across the molding encapsulation unit of molding on the lead frame；

The chip package test device includes measuring head, test bracket and operation board, wherein the measuring head packet Include contact circuit board, main control board, TIB test resource interface board, programmable load load plate and probe contact device, institute Stating main control board further includes DCS integration module circuit board and switch control module, and the test bracket is for supporting and fixing The measuring head, and guarantee the relative positioning between the operation board and the measuring head, the operation board includes a formula Chip tray；

The probe contact device includes multiple probes and bracket, wherein the probe is assemblied on the bracket；

The contact circuit board has electric simultaneously with all chip pins of all encapsulation units on the lead frame Property connection copper foil printed circuit contact point；

It is characterized by: the parallel test method the following steps are included:

Pre- rib cutting step S1: the segment chip pin of each encapsulation unit is separated with lead frame cutting, And another part chip pin of each encapsulation unit is remained connected to the lead frame；

Chip fixing step S2: the lead frame is fixedly mounted on the formula chip tray of the operation board；

Probe alignment step S3: multiple probes of probe contact device are formed into probe array, between the probe The size of space and the chip pin of the encapsulation unit on the lead frame between the size of space in horizontal and vertical upper phase Matching, and make the corresponding copper foil printed circuit contact point electricity of the second end of each probe with the contact circuit board Property connection；

Circuit establishment step S3: the probe uses contact with platform mode, and electric with the chip pin of the encapsulation unit Property be connected, thus, all chip pins of all encapsulation units on the lead frame and the first end of corresponding probe It is electrically connected, and then establishes test loop for the semiconductor power device each of on the lead frame, in the test In head, the corresponding testing station of the test loop of each semiconductor power device；

Device is grouped step S4: the testing station that test loop has been established being divided into the group testing station two groups: A and B group is surveyed Examination station, wherein the serial number odd number of A group testing station is equal to, and the serial number even number of B group testing station is equal to, And I >=1；

Concurrent testing step S5: the switch control position of the switch control module controls the A group by table tennis test pattern Testing station is in state to be tested, and the measuring head surveys the semiconductor power device on A group testing station parallel Examination；After completing the test of A group, the switch control position of the switch control module controls the B group test by table tennis test pattern It stands in state to be tested, the measuring head carries out concurrent testing to the semiconductor power device on B group testing station.

Other technical solutions according to the present invention can also include following one or more technical characteristics.So long as Technical characteristic combination be it is enforceable, the new technical solution thus formed belongs to a part of the invention.

Compared with prior art, the beneficial effects of the present invention are:

A formula test for semiconductor power device of the invention is by test macro and corresponding to multiple semiconductor function The connection design of rate device meets the products application for carrying out concurrent testing to the device on whole frame and tests work in final encapsulation Sequence easily carries out high and low, room temperature test, improves production capacity, reduce testing cost.

Detailed description of the invention

Referring to attached drawing, feature, advantage of the invention and characteristic are able to more preferably by the description of following description Understanding, in attached drawing:

Fig. 1: improved chip package process flow chart is shown, wherein a formula concurrent testing step is added into technique stream Cheng Zhong；

Fig. 2: the schematic diagram of lead frame is shown, wherein the foot 1 and foot 2 of chip are cut, and from the lead frame It separates；

Fig. 3: the pictorial diagram of lead frame is shown, wherein the connection of each chip inside the lead frame, institute are shown It states lead frame and unique two dimensional code identification is set, array co-ordinates are arranged in chip unit in frame；

Fig. 4: the structural schematic diagram of an embodiment of chip package test device is shown；

Fig. 5: encapsulation unit is shown and is separated from the lead frame by cutting and is formed by presser feet；

Fig. 6: the schematic diagram of a preferred embodiment of the concurrent testing equipment of semiconductor power device is shown；

Fig. 7: the structural schematic diagram of the measuring head of the concurrent testing equipment of semiconductor power device shown in fig. 6；

Fig. 8: the system architecture schematic diagram of the concurrent testing equipment of semiconductor power device shown in fig. 6；

Fig. 9: the master control control panel of the measuring head of concurrent testing equipment shown in fig. 6 and the company of internal resource and chip to be measured Connect schematic illustration；

Figure 10: the structure and schematic illustration of the DCS integration module circuit board of master control control panel shown in Fig. 9；

Figure 11: the structure and schematic illustration of the programmable board of the load of master control control panel shown in Fig. 9；

Figure 12: structure and the principle signal of the programmable load load plate of the measuring head of concurrent testing equipment shown in fig. 6 Figure；

Figure 13: the grouping schematic diagram of the switch control module of master control control panel shown in Fig. 9；

Figure 14: the structure and schematic illustration of the floating Driver Card 1071 of master control control panel shown in Fig. 9；

Figure 15: the structure and principle of the TIB test resource interface board 103 of the measuring head of concurrent testing equipment shown in fig. 6 Schematic diagram；

Figure 16: the schematic diagram that the measuring head of concurrent testing equipment shown in fig. 6 is connect with product to be measured；

Figure 17: the signal that the contact circuit board 101 of the measuring head of concurrent testing equipment shown in fig. 6 is connect with product to be measured Figure；

Figure 18: the measuring head of concurrent testing equipment shown in fig. 6 carries out concurrent testing, grouping test, grouping table tennis test Schematic illustration；

Figure 19: the hardware grouping catenation principle in the high-power voltage and current source in the outside of concurrent testing equipment shown in fig. 6 shows It is intended to；

Figure 20: the hardware of the digital channel of the TIB test resource interface board of the measuring head of concurrent testing equipment shown in fig. 6 It is grouped catenation principle schematic diagram；

Figure 21: the test circuit that the measuring head of concurrent testing equipment shown in fig. 6 is dynamically composed by programming Control is used for Test the operation principle schematic diagram of the electrical parameter IDSS of PowerMOS device；

Figure 22: the test circuit that the measuring head of concurrent testing equipment shown in fig. 6 is dynamically composed by programming Control is used for Test the operation principle schematic diagram of the electrical parameter VTH of PowerMOS device；

Figure 23: the test circuit that the measuring head of concurrent testing equipment shown in fig. 6 is dynamically composed by programming Control is used for Test the operation principle schematic diagram of the electrical parameter VDSON of PowerMOS device；

The schematic diagram of Figure 24: PowerMOS chip molding lead frame after molding, wherein PowerMOS chip owns Pin is not cut, and is all connected with lead frame；

The schematic diagram of Figure 25: PowerMOS chip molding lead frame after molding, wherein the pole G of PowerMOS chip Pin and S pole pipe foot are separated by cutting, are not connected with lead frame；

Figure 26: the schematic diagram of the PowerMOS chip on the lead frame, wherein G pole pipe foot and S pole pipe foot quilt Cutting separation；

Figure 27: PowerMOS device finished product schematic；

Another schematic diagram of Figure 28: Figure 25: PowerMOS chip molding lead frame after molding；

Figure 29: the electricity that the measuring head of concurrent testing equipment shown in fig. 6 is connect with single PowerMOS chip to be tested Road schematic diagram；

The concurrent testing "Σ" logic circuit schematic diagram of the PowerMOS chip of Figure 30: 96 testing stations；

Another "Σ" logic circuit schematic diagram of the concurrent testing of the PowerMOS chip of Figure 31: 96 testing stations；

The parallel testing circuit schematic diagram of the PowerMOS chip of Figure 32: 96 testing stations plucks choosing；

Figure 33: the test circuit that the measuring head of concurrent testing equipment shown in fig. 6 is dynamically composed by programming Control is used for The part of original code for testing the electrical parameter IDSS of PowerMOS device illustrates table；

The circuit of Figure 34: the source code databiton (DCS_TO_GATE1) corresponding to Figure 33 hardware controls response shows It is intended to；

Figure 35: Figure 33 source code Micro.Beast.Pins (" DRAIN_beast ") .Voltage's (Vdrain) is hard The circuit diagram of part control response；

The test of Figure 36: Figure 33 source code Mysequenc- > test (idss1) and Mysequenc- > test (idss2) As a result chart；

Figure 37: the test circuit that the measuring head of concurrent testing equipment shown in fig. 6 is dynamically composed by programming Control is used for The part of original code for testing the electrical parameter VTH of PowerMOS device illustrates table；

Figure 38: the source code Micro.Connectivity.SetDatabit (1,14, DatabitOn) corresponding to Figure 37 The circuit diagram responded with the hardware controls of databitoff (DCS_TO_GATE1)；

Figure 39: Figure 37 source code Mysequenc- > test (vth1), Mysequenc- > test (vth2) and The test result chart of Mysequenc- > test (deltaVth)；

Figure 40: the test circuit that the measuring head of concurrent testing equipment shown in fig. 6 is dynamically composed by programming Control is used for The part of original code for testing the electrical parameter VDSON of PowerMOS device illustrates table；

Figure 41: the circuit diagram of the hardware controls response of the part of original code corresponding to Figure 40；

Figure 42: the loading current maxima of the measuring head of concurrent testing equipment shown in fig. 6 and other parameter lists；

The test result chart of Figure 43: Figure 40 source code；

Figure 44: another circuit diagram of the hardware controls response of the part of original code corresponding to Figure 40.

Concurrent testing the results list of the PowerMOS chip of Figure 45: 96 testing stations；

The test result of Figure 46: PowerMOS chip judges table；

Figure 47: 96 test position resource allocation table partial schematic diagrams；

Same or similar element uses same numeral mark in the figure, and different elements uses different number marks Note, in which: 100, measuring head；101, circuit board is contacted；102, main control board；103, TIB test resource interface board；104, may be used Programmed load load plate；1041, inductive load；1042, ohmic load；105, probe contacts device；1051, probe；1052, it holds in the palm Frame；106, DCS integration module circuit board；1061, DCS module；107, floating Driver Card；1071, it floats and drives measurement source； 108, switch control module；109, programmable board is loaded；1091, programmable module is loaded；1092, programmable unit is loaded； 1093, difference instrument channel；1094, time measuring unit；110, test bracket；111, board is operated；112, formula chip support Disk；113, to be measured formula chip；114, high temperature test heating device；200, connecting cable；300, high-power voltage and current source； 400, computer is tested；500, board working power；900, product to be measured.

Specific embodiment

Hereinafter, in conjunction with attached drawing and specific embodiment, the present invention is described further.

Design concept of the invention is as follows:

The present invention makes full use of the superchip on lead frame intensively to be handled, as shown in Figure 1, in lead frame After frame molding, plating, baking, pre- rib cutting is carried out, as shown in Fig. 2, the cutting of specific pin guarantees the realization of electrical testing, often The segment chip pin of a encapsulation unit cuts with lead frame and separates, and cooperates on frame unique 2 D identifying code and corresponding Coordinate in length and breadth carries out whole concurrent testing to encapsulation unit.

Concurrent testing will be connected to implement by means of chip end with lead frame.

The chip package test device includes test processes unit, contact mount and multiple contact units.At test Reason unit is also referred to as concurrent testing equipment or test machine, and contact mount is also referred to as test bracket 110, multiple contact units Referred to as probe contacts device 105.

Lead frame is fixedly arranged on contact mount, and contact unit is equipped with the spy being made of multiple contact probes 1051 Needle array encapsulates the size of space between chip pin in the size of space and lead frame between contact probe 1051 in transverse direction Match on longitudinal direction, contact probe 1051 uses contact with platform mode, is set on contact mount and draws with encapsulation chip Foot is electrical connected, and the quantity for encapsulating chip is consistent with 1051 quantity of contact probe contained in contact probe array, the encapsulation core The quantity of piece is, for example, 96.Contact probe 1051 is also referred to as probe 1051, and encapsulation chip is also referred to as encapsulation unit.

Corresponding test result upload server, prints for next station chip non-defective unit；Entirely draw after the test of formula Wire frame, according to the test result of server, can carry out laser printing, entire lead to non-defective unit in next laser printing station The product of frame cuts pin in excision forming station, independent after cutting after compression moulding, as shown in figure 5, then, packing After machine carries out the quick test item test in electric leakage on-off part, after the appearance detection of product, it is reloaded into pipe or packaging Volume the inside packaging.

The design of chip package test device and its lead frame used

The design of lead frame includes:

Each chip pins are to the Power MOS connection tested Ji Qie Zhu is designed, as shown in figure 3, to draw inside lead frame The molding figure of wire frame, the connection of each chip of lower portion, lead frame unique two dimensional code identification, chip unit array in frame Coordinate；

The design of chip unit array co-ordinates identifying system in the unique two dimensional code identification of lead frame and frame, as shown in Figure 3；

The design of lead frame location fit test contactor, as shown in figure 4, being chip package test device, also referred to as The concurrent testing equipment of semiconductor power device comprising measuring head 100, the test bracket 110 and operation board 111, In, the measuring head 100 includes 1051 integration module of probe described in osculating element --- and the also referred to as described probe contacts device 105, the chip package test device further includes frame Image Location System, the automatic positioning for probe array.

Fig. 5 shows encapsulation unit such as semiconductor power device and cuts separation and presser feet molding from the lead frame.

The design of chip package test device includes:

1051 integration module of probe described in osculating element；

The design of 1051 integration module of probe and lead frame mating part described in osculating element；

The design of probe 1051 integration module and lead frame Image Location System described in osculating element；

Chip package test device and test platform are as follows for the design presentation of test key parameter resource allocation:

System structure and functional profile

As shown in fig. 6, the test macro or concurrent testing equipment are by the measuring head 100, connecting cable 200, voltage Current source 300 and test computer 400 form, wherein the measuring head 100 has been integrated with the used potential circuit of test The resources such as source and clock digital instrument, the connecting cable 200 include with it is described test computer 400 connect communication cable, and The cable of external big voltage and current source connection and the control cable of the measuring head 100.Semiconductor power device shown in fig. 6 Concurrent testing equipment be only limited to the electric performance test of chip and output test result, need to cooperate another equipment, in lead Connecting test and test completion output are carried out after frame loading and transmission and image automatic positioning, complete a large amount of product test.

The measuring head 100 can be combined by the dynamic circuit of Programming chip interface plate to be measured, for various types of The chip testing of type；Chip can concurrently be tested；Chip interface plate to be measured can be configured and connect various resources.The core to be measured Piece interface board also referred to as contacts circuit board 101.

The test computer 400 can run test program；Control test machine and external equipment, such as external power supply etc.； Storing data；It is mutually communicated with operation board 111 described in product.The test machine is also referred to as concurrent testing equipment.The production Operation board 111 described in product is, for example, the formula chip test platform of high-power MOS tube.

The expanded configuration of the test macro is as follows:

● 13 kilovolts of high-voltage power supply；

● more than the LCR measuring instrumentss in 48 channels；

● more than 48 high-acruracy survey instrument；

● probe 1051 described in the high speed current measurement more than 48；

The test header structure

As shown in fig. 7, the measuring head 100 includes the contact circuit board 101, main control board 102, TIB test money Source interface plate 103 and programmable load load plate 104, wherein the contact circuit board 101 is used for the various productions of engaged test Product are connect with the main control board 102 and TIB test resource interface board 103.The contact circuit board 101 is also referred to as Test product contact plate, product test connection circuit board or Family Board, the main control board 102 are also referred to as Master control control panel, master control borad or Main Board, the TIB test resource interface board 103 be also referred to as test resource interface board, TIB circuit board or TIB Board.

As shown in figure 8, the measuring head 100 further includes the probe contact device 105, wherein the probe contact dress 105 are set for being electrically connected with product 900 to be measured realization, convenient for carrying out parameter measurement to the product 900 to be measured.

The main control board 102 includes time-ordered measurement unit, difference measurement instrument and can loader module.It is optional Ground, the main control board 102 can loading procedure moulds including 48 time-ordered measurement units, 48 difference measurement instrument and 48 Block, it is described can loader module be also referred to as loading procedure unit.

The main control board 102 further includes Current Voltage source and test volume instrument, floating drives measurement source 1071 and open Close control module 108, wherein the quantity of the Current Voltage source and test volume instrument is, for example, 48, and the floating driving is surveyed The quantity in amount source 1071 is, for example, 192, and the quantity of the switch control position of the switch control module 108 is, for example, 240.

The test macro further includes external power supply or board working power 500, provides the energy for board work.

The composition and catenation principle of the main control board 102 and internal resource and chip to be measured

As shown in figure 9, the main control board 102 is also referred to as master control control panel or master control borad, the main control board 102 Function it is as follows:

1. the mster-control centre of all components；

2. the communication center of all components, communication modes are, for example, USB/PCI Express；

3. all component connecting interfaces in addition to external extended source；

The main control board 102 includes:

4.TIB board interface；

5.TIB circuit board, the also referred to as described TIB test resource interface board 103, quantity is, for example, 1；

The TIB test resource interface board 103 includes digital channel and PPMU unit, for example including 64 PPMUs units With 320 digital channels, wherein the PPMU unit includes 8 channels, in the system of 48 concurrent testing stations configuration, each PPMU can be individually connected to 48 testing stations；Each digital channel can be directly controlled by FPGAs；Each testing station can be used To 5 digital channels.PPMU is referred to as each pin parameter measurement unit module.

It is described in the way of 900 feed zone of product to be measured to progress product test, the testing station includes:

● the contactor being connected with the pin of each chip；

● the encapsulation of each chip is limited convenient for the device of contactor contact accurate positioning；

● contactor is connected to the corresponding test position on the Family board of test machine.

6.192 independent floating driving sources, are grouped in the way of 4 × 48；

7. the attachment device of digital channel and PPMU, also referred to as the first attachment device；

8.48 direct current output sources and measuring instrumentss, wherein the set or circuit board of direct current output source and measuring instrumentss Referred to as DC-Sources Board or DCS NG；

9.48 PLC technology load blocks, each PLC technology load blocks include the negative of 1 programmable load Carry --- also referred to as LoadProg NG, 1 difference measurement instrument pack or difference measurement instrument channel --- also referred to as DiffMeter and 1 clock meter unit --- also referred to as time-ordered measurement unit or TMU；

10. the switch control module 108 provides 240 switch control positions；It is divided into 5 groups, every group of 48 switch controls Position；

The switch control position can both drive micrometering examination transceiver or Microtest transceiver, can also be with Drive MOS semiconductor switch, wherein each micrometering examination transponder chip have 16 by single-wire-protocol frame or The switch that Single wire ptotocol frame is individually programmed, the MOS semiconductor switch is for example for relaying purposes；

240 switch control positions can fully control each testing station by circuit setting, however, it has been proposed that it is divided into 5 groups, The first 4 groups connections as resource, the 5th group is used as public connection；

Routinely, up to four different micrometering examination transceivers are used for the relevant connection in testing station.Each micrometering examination transmitting-receiving Device is controlled by a data bit, and interrelational form is as follows:

First group (1-48): being controlled by No. 1 transceiver

Second group (49-96): being controlled by No. 2 transceivers

Third group (97-144): it is controlled by No. 3 transceivers

4th group (145-192): being controlled by No. 4 transceivers

5th group (193-240): being controlled by public transceiver

48 voltage and current sources and test volume instrument DCS NG working principle

As shown in Figure 10, it shares 4 pieces of DCS integration module circuit boards 106 to be mounted on the main control board 102, every piece The DCS integration module circuit board 106 can be interchanged, and have 12 DCS moulds inside every piece of DCS integration module circuit board 106 Block 1061 is screwed installation, and 12 × 4, which share 48 DCS, supports 48 test positions to work at the same time.The DCS module 1061 has There is the function in Current Voltage source and test volume instrument.The DCS integration module circuit board 106 is also referred to as DCS Boards, described DCS module 1061 is also referred to as DCS MP NG.

The specifications parameter of the DCS module 1061:

√ function has 4 quadrants to export VI

√ function has FV, FI, FHiZ, MV, MI

√ output current scope 20uA, 200uA, 2mA, 20mA, 200mA, 4A

√ output voltage range 1V, 3V, 5V, 10V, 30V, 80V

√ abnormal alarm function

The √ time measures function

Programmable offered load and connection measuring instrument principle

As shown in figure 11, the main control board 102 includes loading programmable board 109, wherein the load is programmable The quantity of board 109 is, for example, 4.It is described to load programmable board 109 including loading programmable module 1091, wherein each It is described to load programmable board 109 for example including 12 load programmable modules 1091.It is described to load programmable board 109 Also referred to as Load Prog Board, the load programmable module 1091 are referred to as Load Programmable NG.

The load programmable module 1091 includes load programmable unit 1092, difference instrument channel 1093 and timing Measuring unit.The load programmable unit 1092 also referred to as can add programming channel, can loader module, the difference instrument Channel 1093 is also referred to as difference measurement instrument, and time-ordered measurement unit is also referred to as time measuring unit 1094, time-ordered measurement unit.

Therefore, the main control board 102 has the load programmable module 1091 described more than 48, each load Programmable module 1091 is for example including 1 load programmable unit, 1092,1 difference instrument channels 1093 and 1 The time measuring unit 1094.

The load programmable unit 1092 is shown in a manner of principle of work and power block diagram in Figure 11.

Difference instrument channel 1093 is shown in a manner of principle of work and power block diagram in Figure 11.

The time measuring unit 1094 is shown in a manner of principle of work and power block diagram in Figure 11.

Programmable load load plate

The programmable load load plate 104 includes programmable inductive load 1041 and programmable ohmic load 1042.As shown in figure 12, the programmable load load plate 104 is for example including 48 × 2 programmable 1041 Hes of inductive load 48 × 4 programmable ohmic loads 1042.The load of mainly various parameters value is electric in the programmable load load plate 104 Sensing resistor, these loads directly all cannot be once connected on the circuit of chip to be measured, be needed programmable by the load Board 109 accesses as required under program control, participates in measurement.

The programmable load load plate 104 is to connect circuit board with product test by master control borad, and test is needed to use To programmable inductance and resistance as load be loaded into measurement in, at present provide 48 concurrent testing stations, provide simultaneously The inductive load 1041 and ohmic load 1042 of each testing station.Product test connection circuit board is also referred to as the contact circuit Plate 101.

As shown in figure 12, each testing station is configured with reconfigurable interconnection load, has 4 measuring resistances in load load plate With 2 inductance, it may be connected to 4 different locations.

240 bit switch control bit principles

As shown in figure 13, system provides 64 data bit or control bit or databits.64 control bits are by FPGA Digital signal directly drives, and 64 control bits output is the signal of 0v or 3.3v, therefore it is straight that MOSFET can be driven to come The coil or possible configuration for connecing driving relay drive transceiver MSW05 described below.

The switch control module 108MSW05 is applied to the control of the transceiver of 16 control channels of high-pressure and high-precision, By 16 separate solid relay packages inside LQFP44 package module.The switch control module 108MSW05 can pass through The mode of serial or parallel opens/closes each channel with the various modes of make an immediate response at a high speed type or low speed delaying type.

240 independent control positions can be provided, and be segmented into 5 groups, controlled by 48 independent control positions.

240 switch control positions, which refer to the test machine at present, has 240 switch control positions to go control 240 to switch, and 240 A control bit is made of several MSW05 chips, has 16 MOS semiconductor switch inside each MSW05.

The floating drives measurement source principle

The main control board 102 includes floating Driver Card 107.As shown in figure 14, the main control board 102 is for example Including 4 pieces of floating Driver Cards 107.

It are furnished with 4 different floating driving sources in each testing station.

Each floating driving source is by light-coupled isolation and programmable floating voltage digital drive.

Floating driving source connects first 4 bit digital channels.

Circuit diagram in 4 referring to Fig.1, wherein

The rank DRV+/DRV-difference of programmable high potential are as follows: 4-18V；

The rank DRV+/DRV-difference of programmable low potential are as follows: -5--2V and 0V；

May be programmed output current precision when exporting 300mV is 50mA.

The digital channel of TIB circuit board and the connection of PPMU

TIB circuit board, the also referred to as described TIB test resource interface board 103, including PPMUs and digital channel.Such as Figure 15 Shown, the TIB test resource interface board 103 is for example including 64 PPMUs and 320 digital channels.The TIB test resource Interface board 103 is mounted on master control borad, and the TIB circuit board for each testing station provide 2 PPMU simulation output sources and 10 digital channel accesses.

The function and its composition of PPMU describes

The each PPMU of √ can provide the voltage and current output channel source of 4 quadrants output；

√ has output voltage, exports electric current；Export certain frequency waveform；Voltage is measured, the function of electric current is measured；

The range of √ output voltage and measurement voltage is ± 11.25V；

√ output electric current and the range for measuring electric current are that ± 5uA ± 20uA ± 200uA ± 2mA ± 60mA is reported extremely It is alert；

√ provides the connection of Kelvin measurement device；

DGS connection outside √；

The each PPMU of √ can be directly connected to the output and measurement of 5 digital channels；

Digital channel working principle

320 digital channels are directly controlled by FPGAs, by TIB circuit board insertion master control borad；320 digital channels can To be interpreted as 320 input/output terminals, each input/output terminal only receives or sends digital signal, and 0 or 1, pre-define 0 The 0 volt of low level in position, 1 is 5.5 volts of high level 50mA electric currents, in addition timing completes signal input, wherein the preparatory of the timing is determined Adopted frequency can be greater than 10Mhz；FPGA can be directly read the signal record of digital channel by timing predetermined；

Its function: static programmable number execution module

The output voltage range of √ 0V to 5.5V and provide the electric current of 50mA；

√ can provide the output frequency more than 10MHz；

The each channel √ provides the storage space of the sequence of 2,000,000 execution vectors；

√ provides the channel that output or receptive pattern can be selected；

√ provides DSIO, including 1,000 execution vector output memory spaces and 1,000 execution for each station of concurrent testing Vector inputs memory space；

For the configuration at 48 concurrent testing stations:

√ provides the connection of 5 digital channels；

√ provides the connection of test and the output of 1 PPMU；

√ provides the output of PPMU and the output of 5 digital channels；

For the configuration at 32 concurrent testing stations:

The connection of 10 digital channels of √；

The output and measurement connection of 2 PPMUs of √；

The output of each PPMU of √ is directly connected to the output end of 5 digital channels；

√ PPMU1 output can connect digital channel 1-5；

√ PPMU2 output can connect digital channel 6-10；

The measuring head connects the structure of the product to be measured

As shown in figure 16, it is assemblied on bracket 1052 by a large amount of probe 1051,113 He of contact measured formula chip Circuit board 101 is contacted described in the product 900 to be measured on the measuring head 100, test loop is completed, by the operation board 111 replace described 113 groups of to be measured formula chip automatically, complete the test of typical products in mass production.The bracket 1052 is also referred to as a formula Chip tray 112

Described in test product contact circuit board and product how catenation principle

As shown in figure 17, design has and connect simultaneously with 96 granule products on the contact circuit board 101 or Family Board Copper foil printed circuit contact point.

Copper foil printed circuit contact point is not directly connected to product to be tested instead of, passes through probe array and probe array Seat connects chip to be measured.

Every chip to be measured is combined by these described probes 1051, and the big electrode of electric current provides a certain number of spies 1051 contact chip pin of needle.

The description of concurrent testing and grouping test and grouping table tennis test

As shown in figure 18, when 96 chips are put into the test of 96 testing stations simultaneously, 96 testing stations are divided into two groups, A group and B group, every group of 48 testing stations, carry out the concurrent testing between group and group

Odd number testing station is A group, and such as Figure 18 mark yellow or second, four rows, even number testing station is B group, such as Figure 18 mark blue Or first and third row

A group and B group carry out ping-pong type test, after the completion of A group, pass through relay control test b group

VTH and IDSS is divided to for two groups of tests.

The limitation of tested test-run a machine maximum current 100A, the test of VDSON are respectively divided into 8 groups again between two groups, each Group is made of 6 testing stations, in total 16 groups.

A group testing station: B group testing station:

3579 11 group B1:2 468 10 12 of group A1:1

15 17 19 21 23 group B2:14 16 18 20 22 24 of group A2:13

27 29 31 33 35 group B3:26 28 30 32 34 36 of group A3:25

39 41 43 45 47 group B4:38 40 42 44 46 48 of group A4:37

51 53 55 57 59 group B5:50 52 54 56 58 60 of group A5:49

63 65 67 69 71 group B6:62 64 66 68 70 72 of group A6:61

75 77 79 81 83 group B7:74 76 78 80 82 84 of group A7:73

87 89 91 93 95 group B8:86 88 90 92 94 96 of group A8:85

The hardware of external high-power voltage and current source Beats is grouped connection type

1 outside high-power voltage and current source Beasts is how to distribute to 96 testing stations:

As shown in figure 19, the output of the external high-power voltage and current source Beats is by cable connection to the more of master control borad Road load programming module distributes 48 current output channels, and wherein No. 1 and No. 2 testing stations are distributed in channel 1, in toggle switch It carries out distributing between 2 stations under the control of position 97,145, similarly the 95th and No. 96 station is led under the control of toggle switch position by the 35th Road is allocated, and then 48 outputs of completion are distributed to 96 stations and completed in testing, and specific distribution is referring to Figure 47.

Since the control of toggle switch position can be with 48/2=24,48/4=12 is organized interior progress sequence and concurrent working completion The outer quantity of group is controlled in group.

Since the control of toggle switch position is segmented into 2 groups or 4 groups, such as 48/2=24 or 48/ in every group 4=12 carries out concurrent testing in group, and sequential testing is carried out between group.

Multichannel loading programming module is also referred to as Multiplexer Load PROG, and current output channels are also referred to as Current The channel out.

The hardware of digital channel is grouped connection type

320 digital channels are how to be assigned to 96 testing stations:

As shown in figure 20, such as a total of 320 digital channels of test machine, 240 digital channels therein are divided Group: digital channel group #1 to #5 first distributes to No. 1 testing station and tests a core by the control of switch control position 97 and 145 Piece then switches to No. 2 testing stations and tests another chip；240 digital channels are divided into 240/5,48 groups according to this method Digital channel is met the chip testing of 96 testing stations by ping pong scheme switching, if needing 96 without ping pong scheme switching × 5 nearly 480 digital channels are saved so 240 digital channels can satisfy for current 96 testing stations of design The hardware resource of 240 digital channels；Specific distribution is referring to Figure 47.

Hereafter using power MOS (Metal Oxide Semiconductor) device --- namely test original is described in detail as example in the concurrent testing of PowerMOS chip Reason and method.

As shown in Figure 24, Figure 25, there are 96 power MOS (Metal Oxide Semiconductor) devices on a lead frame, the institute before carrying out concurrent testing Electrode in succession, before concurrent testing can the pole S and G cut separate, such as the following figure it can be seen that in a formula chip Inside array, the pole D of all chips is connected together, and the pole G and the pole S are that independent separate comes out:

Semiconductor power device, also referred to as power semiconductor, also referred to as power electronic devices in the past, it is simple come It says, carries out Power Processing, there is processing high voltage, the semiconductor devices of high current ability.

As using power MOSFET device as the rapid development of the novel power semiconductor of representative, present power is partly led Body device is very extensive, computer, passage, consumer electronics, automotive electronics be representative 4C industry more have application.

Measure the value of IDSS

Test condition: Vgs=0 [V], Vds=Nom.BVdss [V]；

As shown in figure 21, test job principle: the leakage current between the pole D and the pole S is surveyed, condition is the pole D in Vgs=0V When being not turned on the pole S, the reverse leakage current of diode, DCS instrument is connected in series to the source that measurement is accessed by the pole D between the pole S and ground Leakage current is measured when forward voltage 15V and 30V, for value less than 2.5 μ A, otherwise it is defective products that 0.8 μ A, which is normal value,.

Figure 21 shows the schematic diagram 211 of simple grain test IDSS；Figure 21 shows the schematic diagram 212 of more concurrent testing IDSS.

Measure the value of VGS (th)

As shown in figure 22, test job principle: the pole D and the pole G are closed to be shorted over the ground by switch SW14 and meet test condition Vgd When=0V, when the pole S seals in DCS current source, and sourcing current is respectively Id=250 μ A/Id=20 μ A in the voltmeter in DCS current source The end S voltage-to-ground value is measured, value is in 250 μ A between voltage range 1.05V and 2.4V, the voltage range 0.88V in 20 μ A It is normal chip value between 1.89V.It otherwise is defective products.Due to there was only 48 DCS, so once can only concurrent testing 48 Grain, 96 need to complete all 96 tests under test pattern of rattling.

Figure 22 shows the schematic diagram 221 of simple grain test VGS (th)；Figure 22 shows the principle of more concurrent testing VGS (th) Figure 22 2.

Measure VDSON relevant parameter

Test condition: under the conditions of the pole the G cut-in voltage of Vgs=10V, 5.0V, the pole D and the pole S conducting electric current are in 8.5A, 2.0A Measure conducting electric current and the pole D S extreme pressure drop.

Test job principle: as shown in figure 23, offer 10V and the 5V voltage between the pole G and the pole S is accessed with the source PPMU, in D Beast current source is accessed in pole, and the simulation of load programmable module 1091 is sealed between the pole S and ground wire in load access state Under, pressure drop when being connected with the difference table measurement pole D and the pole S of the load programmable module 1091 and the electric current that passes through work as electricity When stream is 8.5A, the pressure drop that difference table is surveyed when PPMU loads 5V will be lower than 415mV, and electric current is higher than between 8-9A in 10V 213mV is lower than 400mV；When electric current is 2A, PPMU loads 10V, and the pressure drop that difference table is surveyed will be lower than 100mV and electric current exists It is normal chip between 1.4A and 2.6A, is otherwise defective products.

Figure 23 shows the schematic diagram 231 of simple grain test VDSON；Figure 23 shows the schematic diagram of more concurrent testing VDSON 232。

Figure 45 shows the concurrent testing result sample list of the above three electrical parameter of 96 testing stations.Figure 46 is described The test result of three electrical parameters judges list.

Conceived based on foregoing invention, referring to Fig.1-5, the parallel test method of semiconductor power device according to the present invention First embodiment, the parallel test method is used in packaging and testing process, by chip package test device to whole Semiconductor power device on lead frame carries out concurrent testing.With the difference of the prior art at least that: in the present invention In, in packaging and testing process, the semiconductor power device not from the lead frame, separate completely by cutting, institute Multiple semiconductor power devices can be measured simultaneously by stating chip package test device；And in the prior art, in chip package work In the final encapsulation test station of skill, the semiconductor power device completely from the lead frame isolate completely by cutting Come, and chip package test device is merely able to singly measure semiconductor power device.

As shown in Fig. 2,3,5, the semiconductor power device be distributed across the molding on the lead frame molding or Person molding plating, baking molding encapsulation unit.As described above, the semiconductor power device is, for example, PowerMOS core Piece or device.

Referring to Fig.1 6, the concurrent testing equipment of the chip package test device or semiconductor power device includes described Measuring head 100, the test bracket 110 and the operation board 111, wherein the measuring head 100 includes the contact electricity Road plate 101, the main control board 102, the TIB test resource interface board 103,104 and of programmable load load plate The probe contacts device 105, and the main control board 102 further includes the DCS integration module circuit board 106 and the switch Control module 108, the test bracket 110 guarantee the operation board 111 for supporting and fixing the measuring head 100 With the relative positioning between the measuring head 100, the operation board 111 includes a formula chip tray 112.Fig. 6-16 briefly shows Function, structure and the working principle of each component part of the concurrent testing equipment of semiconductor power device out, and hair above Bright design part has carried out related text description.

As shown in figure 16, the probe contact device 105 includes multiple probes 1051 and the bracket 1052, In, the probe 1051 is assemblied on the bracket 1052.Preferably, the probe 1051 or contact probe 1051 include conduction Syringe needle and conductive needle body, wherein compressed spring is provided in the hollow cavity of the conduction needle body, the conduction syringe needle is placed in The both ends of the conduction needle body, also, by means of the compressed spring, the length of the probe 1051 can change, to fit Answer the test of the semiconductor power device of different model.

As shown in figure 17, the contact circuit board 101 has all with all encapsulation units on the lead frame The copper foil printed circuit contact point that chip pin is electrically connected simultaneously.It is understood that being needed for different types of chip The different contact circuit board 101, to design copper foil printed circuit contact point corresponding with the pin of the chip.

Referring to Fig.1-6, the parallel test method the following steps are included:

Pre- rib cutting step S1: the segment chip pin of each encapsulation unit is separated with lead frame cutting, And another part chip pin of each encapsulation unit is remained connected to the lead frame.Figure 24 shows PowerMOS chip dies Seal the schematic diagram of lead frame after molding, wherein all pins of PowerMOS chip are not cut, all with lead frame phase Even.Figure 25 shows the schematic diagram of PowerMOS chip molding lead frame after molding, wherein the G pole pipe of PowerMOS chip Foot and S pole pipe foot are separated by cutting, are not connected with lead frame.It is understood that due to the electrode of different types of chip Or pin may be different, therefore, cutting needed to separate which pin just needs in advance according to test circuit in pre- rib cutting step S1 The total design of design is to determine.

Chip fixing step S2: the lead frame is fixedly mounted on to the formula chip tray of the operation board 111 On 112.As shown in figure 16, formula chip tray 112 can accurately two dimension be moved in the operation planar of the operation board 111 It is dynamic, to be aligned with the probe array of probe contact device 105.

The 1051 alignment step S3 of probe: multiple compositions of probe 1051 of probe contact device 105 are visited Needle array, the size of space between the probe 1051 and between the chip pin of the encapsulation unit on the lead frame between Match on horizontal and vertical every size, and makes the second end and the contact circuit board of each probe 1051 101 corresponding copper foil printed circuit contact point is electrically connected.It is understood that each of semiconductor power device is independent Pin is accordingly electrically connected with probe 1051 described at least one, the pipe of semiconductor power device connecting with the lead frame Foot can be used in conjunction with one or more probe 1051, can also each pin accordingly with probe described at least one 1051 electrical connections.

Circuit establishment step S3: the probe 1051 uses contact with platform mode, and draws with the chip of the encapsulation unit Foot is electrical connected, thus, all chip pins of all encapsulation units on the lead frame and the corresponding probe 1051 first end is electrically connected, and then is tested back for semiconductor power device foundation described each of on the lead frame Road, in the measuring head 100, the corresponding testing station of the test loop of each semiconductor power device.It is understood that , as shown in figure 16, it is electrically connected between the probe contact device 105 and the contact circuit board 101 after being aligned, whole It is kept fixed together in a test process, as long as the type of the to be measured formula chip 113 is changed without, there is no need to replace State contact circuit board 101.Device 105 is contacted to move the probe by controlling the operation board 111, so that the probe 1051 first end is electrically connected with corresponding chip pin, so that all chips on the lead frame are both electrically connected with Into test circuit.Preferably, using frame Image Location System described above, for probe array and the lead frame On all chip pins of all encapsulation units carry out automatic positioning alignment.Preferably, the contact with platform mode passes through institute Bracket 1052 is stated to realize, the probe array can be assembled into the form of platform by the bracket 1052, then pass through movement The lead frame, realize all chip pins integrally to the corresponding probe on the bracket 1052 of flat form 1051 is in electrical contact.

Device is grouped step S4: the testing station that test loop has been established being divided into the group testing station two groups: A and B group is surveyed Examination station, wherein the serial number odd number of A group testing station is equal to (2 × I-1), the serial number even number of B group testing station, It is equal to (2 × I), and I >=1.As shown in Figure 18,24,25, for the lead with 96 encapsulation units or PowerMOS chip For frame, four row PowerMOS chips in Figure 24 are numbered by serial number shown in Figure 18, wherein the 2nd, 4 behavior A groups PowerMOS chip, corresponds to A group testing station, and the 1st, 3 behavior B group PowerMOS chips correspond to B group testing station.

Concurrent testing step S5: the switch control position of the switch control module 108 controls the A by table tennis test pattern Group testing station is in state to be tested, and the measuring head 100 carries out simultaneously the semiconductor power device on A group testing station Row test；After completing the test of A group, the switch control position of the switch control module 108 controls the B by table tennis test pattern Group testing station is in state to be tested, and the measuring head 100 carries out simultaneously the semiconductor power device on B group testing station Row test.It is understood that referring to 18,19, the same row of resource needed for each testing station beneficial to the toggle switch position and It realizes effective distribution and utilizes.For example, as shown in Figure 21,22, the electrical parameter IDSS of PowerMOS device as described herein Measurement with the electrical parameter VTH of PowerMOS device is exactly that 96 PowerMOS chips are divided into two groups, and every group 48, simultaneously After 48 PowerMOS chips of concurrent testing A group, by sequence circuit dynamic combined, and the toggle switch is controlled Table tennis test conversion, concurrent testing while realizing 48 PowerMOS chips to B group are realized in position.

The parallel test method of above-mentioned semiconductor power device has reached the semiconductor on the primary whole lead frame of test The technical effect of power device greatly improves production test efficiency.

Preferably, the device grouping step S4 further includes following sub-step:

Group divide sub-step S21: according to needed for the semiconductor power device test electric current or test voltage it is big The maximum current or voltage that the small and described measuring head 100 is able to bear, respectively by A group testing station and B group testing station Respectively it is divided into M group, there is N number of testing station in every group, wherein the serial number odd number of A group testing station is equal to 2 (i+j × N)- 1, the serial number even number of B group testing station is equal to 2 (i+j × N), wherein I=(i+j × N), i are testing station serial number, j For group's serial number, and 1≤i≤N, 0≤j≤M, M >=0, N >=1.As described above, referring to Fig.1 8,23,24,25, by the survey The limitation of test-run a machine maximum current 100A, the test of VDSON are respectively divided into 8 groups again between two groups, and each group is tested by 6 It stands composition, in total 16 groups.It is, M=8, N=6,1≤i≤6, the serial number of 0≤j≤8, A group testing station is odd Number, is equal to 2 (i+j × 6) -1, and the serial number even number of B group testing station is equal to 2 (i+j × 6).

The concurrent testing step S5 is substituted, carries out concurrent testing as follows:

Group concurrent testing step S22: test pattern controls in order for the switch control position of the switch control module 108 The measuring head 100 tests the semiconductor power device of each group, also, in each group, the switch control module 108 switch control position is by the semiconductor power device for belonging to A group in group described in table tennis test pattern respectively concurrent testing With the semiconductor power device for belonging to B group.As indicated above, 1 group to 8 groups is tested in order, and in each group, together When test A group in j group all PowerMOS chips, then by table tennis test pattern convert to B group, while test b group All PowerMOS chips of interior j group.It is, concurrent testing A1 group simultaneously, then by table tennis test pattern conversion, Concurrent testing B1 group simultaneously, while concurrent testing A2 group, then by table tennis test pattern conversion, while concurrent testing B2 is small Then group, while concurrent testing A3 group are converted by table tennis test pattern, while concurrent testing B3 group ... ....

By the table tennis test pattern of above-mentioned point of group reached it is primary test be installed in place after, quickly and easily test whole The technical effect of the high current parameter such as VDSON of 96 PowerMOS chips on lead frame.

Preferably, referring to Fig.1 7, in the case of using semiconductor power device described in high-current test, the probe is connect It touches device 105 and provides the probe 1051 of quantification for each high current pin of the semiconductor power device, formed The probe 1051 is combined, and the high current pin is contacted by the combination probe 1051.For example, Figure 17 is shown The pole G of PowerMOS chip is connected with 6 probes 1051, and the pole D is connected with 7 probes 1051, and the pole S is connected with 6 The probe 1051, such configuration guarantee that the probe 1051 will not be extraordinary in the case where carrying out big input current test Fever, the electric current that the every probe 1051 is born is in the normal range.

Preferably, referring to Fig.1 5, the main control board 102 further includes TIB board interface and the first attachment device, In,

The TIB board interface is for connecting the TIB test resource interface board 103, the TIB test resource interface board 103 include digital channel and PPMU unit；

First attachment device is for connecting the main control board 102 and the digital channel, the PPMU unit.

Board design modular in this way guarantees that resource circuit plate can be replaced by different testing requirements, for example, figure There are the TIB test resource interface board 103 shown in 15 320 digital channels and 64 PPMU units, such resource to match Set the concurrent testing needs that can satisfy the lead frame of 96 chips.And for the lead frame of 240 chips, it is necessary to more Resource needs replacing the bigger TIB test resource interface board 103 of capacity.The resource that the test machine is capable of providing includes But be not limited to: digital channel, PPMU unit, floating driving measurement source 1071, the DCS module 1061, the load can Programming module 1091, difference measurement table, described time measuring unit 1094 etc..

Preferably, referring to Fig.1 3, the switch control module 108 includes switch control position, wherein the switch control position Micrometering can be driven to try transceiver, can also drive MOS semiconductor switch, the micrometering examination transponder chip has 16 programmings Control switch, programming Control switch can pass through single-wire-protocol frame individually programming Control.It is understood that described Switch control position has toggle switch control function, is the critical component for realizing table tennis test.

Preferably, referring to Fig.1 1, the main control board 102 include it is described load programmable board 109, the load can Programming board 109 includes the load programmable module 1091, and the load programmable module 1091 is for example including the load Programmable unit 1092, difference instrument channel 1093 and the time measuring unit 1094.It is understood that by In the load programmable module 1091, as shown in Figure 21-23,33,37,40, by programming, resource can be dynamically distributed, Realize that primary test is installed in place, the technical effect of the encapsulation unit on the whole lead frame of concurrent testing.

Preferably, referring to Fig.1 2, the programmable load load plate 104 includes programmable inductive load 1041 and can compile The ohmic load 1042 of journey；

The programmable load load plate 104 be by the contact circuit board 101 and the main control board 102, The programmable inductive load 1041 and the programmable ohmic load 1042 that test needs to use are as load load Into measurement, the inductive load 1041 and the ohmic load 1042 are provided for each testing station.

Such be configured with is conducive to dynamically be loaded into physics component in test circuit, to meet different test need It wants, so that same test equipment can be used for a greater variety of chip testings.

Preferably, referring to Fig.1 4, the main control board 102 further includes the floating Driver Card 107, and the floating is driven Movable plate card 107 includes that the floating drives measurement source 1071, wherein the floating driving source may be programmed floating by light-coupled isolation Dynamic voltage digital driving.

Such configuration guarantees that different voltage values can be provided for circuit dynamic, conducive to programming Control test is realized Automation.

Preferably, referring to Fig.1 6, the probe contact device 105 further includes high temperature test heating device 114；

The parallel test method further includes following testing procedure:

High temperature test step 91: the lead frame is heated to one and determined by the high temperature test heating device 114 Then temperature carries out high temperature test by the concurrent testing step S5 again.

It is such to configure the performance test being advantageously implemented under the high-temperature work environment to chip.

Preferably, referring to Fig.1 6, the parallel test method further includes following steps:

A step 101 is surveyed in replacement: after the test for completing the to be measured formula chip 113, the operation board 111 is automatic Replace the next to be measured formula chip 113.

It is realized entirely certainly by the autoloading structure and frame Image Location System of the lead frame of the operation board 111 The concurrent testing of dynamicization, particularly suitable for full-automatic chip package production line.

Preferably, referring to Figure 26,27,28, the semiconductor power device is power mos chip.Power mos chip is also It is PowerMOS chip, as preferred embodiment of the invention, the test method of its electrical parameter is described in detail below, especially It is the test of electrical parameter IDSS, VTH, VDSON.

Advantageously, referring to Figure 24-28, the multiple semiconductor power device connection is on the lead frames, wherein Mei Geban The semiconductor power device separated, also, all is cut in the pole S and the pole G of conductor power device from the lead frame The pole D of part is connected together.It is understood that the pole D of semiconductor power device all on the lead frame is to connect Be connected together is needed according to the circuit design of the main control board 102 to consider.Figure 29 shows concurrent testing shown in fig. 6 The circuit diagram that the measuring head 100 of equipment is connect with single PowerMOS chip to be tested；Figure 30 shows 96 tests The concurrent testing "Σ" logic circuit schematic diagram for the PowerMOS chip stood；Figure 31 shows the parallel of the PowerMOS chip of 96 testing stations Test another "Σ" logic circuit schematic diagram；Figure 32 shows plucking for the parallel testing circuit schematic diagram of the PowerMOS chip of 96 testing stations Choosing.In Figure 29,31, the purpose of Force_G and Sense_G in pairs is used to guarantee the precision of measurement Kelvin connection, Force_G refer to the pole the G connection driving end of chip, and Sense_G refers to that the pole G of chip is connected to sensing end.

Preferably, referring to Figure 21, the parallel test method of the semiconductor power device is:

The test loop of the electrical parameter IDSS of i-th power mos chip is established as follows:

The setting pole S is connected to i-th DCS measuring instrumentss；

Close the switch in the connection source of the pole G；

Disconnect the switch of the ground line of the pole G；

The setting pole D is connected to the high-power voltage and current source 300；

The measurement method of the electrical parameter IDSS of the i-th power mos chip is as follows:

The source output voltage that the arrival pole D is arranged is the first voltage value；

By the i-th DCS measuring instrumentss, data are acquired by determining time interval, is averaged, as measures First IDSS value；

The source output voltage that the arrival pole D is arranged is second voltage value；

By the i-th DCS measuring instrumentss, data are acquired by determining time interval, is averaged, as measures 2nd IDSS value.

For the lead frame of 96 chips, wherein 1≤I≤48, the measuring head 100 of the invention have while providing The ability of 48 sets of test resources, therefore it is segmented into A group and B group progress concurrent testing.For each power MOS core to be tested Piece requires a set of test resource, while testing 48 power mos chips and just needing 48 sets of test resources, and establishing 48 simultaneously A test loop.

Referring to Figure 21, the first voltage value is, for example, 15 volts of the 5th label row setting, and the second voltage value is for example It is 30 volts of the 7th label row setting, therefore the first voltage value is also referred to the 351st label row of Figure 33, described the Two voltage values are also referred to the next line of the 361st label row of Figure 33.It is understood that according to the semiconductor power device The model specification of part, the first voltage value are also possible to 10 volts or 20 volts, and the second voltage value is also possible to 20 Volt or 40 volts, as long as the first voltage value and the second voltage value can roots according to product test concept feasible According to needing to take any numerical value.

Referring to Figure 21, the calculating of the first IDSS value and measurement are referring to the variable i dss1_c of the 6th label row, and described the The calculating of two IDSS values is with measurement referring to the variable i dss2_c of the 8th label row.Referring to Figure 33, the calculating of the first IDSS value With measurement referring to the variable i dss1_c of the 361st label row, the calculating and measurement of the 2nd IDSS value are gone referring to the 362nd label Variable i dss2_c.As described above, in the case of the first voltage value is set as 15V, if measurement obtain described the One IDSS value is less than 2.5 μ A, and in the case of the second voltage value is set as 30V, if measurement obtain described second IDSS value is less than 0.8 μ A, then the IDSS parameter of the semiconductor power device is normal value, and the semiconductor power device is good Otherwise product are defective products.

As shown in figs. 33-36, by programming such as C Plus Plus program, reach and realize that dynamic reorganization measuring circuit, table tennis are opened The technical effect for closing control, has reached the concurrent testing effect of ping pong scheme.For example, program statement 341databiton (DCS_ TO_GATE1 the circuit variation) controlled is as shown in figure 34, program statement 351Micro.Beast.Pins (" DRAIN_beast ") .Voltage the circuit variation of (Vdrain) control is as shown in figure 35, and the test result of electrical parameter IDSS is as shown in figure 36.

Preferably, referring to Figure 22, the parallel test method of the semiconductor power device is:

The test loop of the electrical parameter VTH of i-th power mos chip is established as follows:

The setting pole S is connected to i-th DCS measuring instrumentss；

The switch that the ground line of the pole G is closed by the switch control position of the switch control module 108, so that the pole G It is connected over the ground；

The measurement method of the electrical parameter VTH of the i-th power mos chip is as follows:

The pin sourcing current that the i-th DCS measuring instrumentss are arranged is the first current value；

By the i-th DCS measuring instrumentss, data are acquired by determining time interval, is averaged, as measures First VTH value；

The pin sourcing current that the i-th DCS measuring instrumentss are arranged is the second current value；

By the i-th DCS measuring instrumentss, data are acquired by determining time interval, is averaged, as measures Second VTH value.

For the lead frame of 96 chips, wherein 1≤I≤48, the measuring head 100 of the invention have while providing The ability of 48 sets of test resources, therefore it is segmented into A group and B group progress concurrent testing.For each power MOS core to be tested Piece requires a set of test resource, while testing 48 power mos chips and just needing 48 sets of test resources, and establishing 48 simultaneously A test loop.

Referring to Figure 22, first current value is, for example, the 250 μ A of VTH1 value in table, and second current value is, for example, 20 μ A of VTH2 value in table, therefore first current value is also referred to the 385th of Figure 37 and row source code is marked to understand, Second current value is also referred to the 383rd label row of Figure 37.It is understood that according to the semiconductor power device Model specification, first current value is also possible to 200 μ A or 150 μ A, second current value be also possible to 10 μ A or 30 μ A of person, as long as first current value and second current value can according to need and take according to product test concept feasible Any numerical value.

Referring to Figure 22, the calculating and measurement of first VTH value referring to variable V TH2, the calculating of second VTH value with Measurement is referring to variable V TH1.Referring to Figure 37, the calculating of first VTH value and the variable vth2 of the 386th label row of measurement reference, The calculating of second VTH value is with measurement referring to the variable vth1 of the 384th label row.As described above, in first electric current Value is set as in the case of 250 μ A, if between the voltage range 1.05V and 2.4V of first VTH value that measurement obtains, and In the case of second current value is set as 20 μ A, if the voltage range 0.88V of second VTH value that measurement obtains and Between 1.89V, then the VTH parameter of the semiconductor power device is normal value, and the semiconductor power device is non-defective unit, otherwise For defective products.

Figure 37 shows the survey that the measuring head 100 of concurrent testing equipment shown in fig. 6 is dynamically composed by programming Control Examination circuit is used to test the part of original code diagram illustrating table of the electrical parameter VTH of PowerMOS device；Figure 38, which is shown, to be corresponded to The source statement 381Micro.Connectivity.SetDatabit (1,14, DatabitOn) and sentence of Figure 37 The circuit diagram of the hardware controls response of 382databitoff (DCS_TO_GATE1)；Figure 39 shows the source code of Figure 37 The test of Mysequenc- > test (vth1), Mysequenc- > test (vth2) and Mysequenc- > test (deltaVth) As a result chart.

Preferably, referring to Figure 23, the parallel test method of the semiconductor power device is:

Parallel test method as described in claim 2 carries out concurrent testing, wherein

The test loop of the electrical parameter VDSON of (i, j) a described power mos chip is established as follows:

The pole D is connected to the high-power voltage and current source 300；

The source PPMU is accessed between the pole G and the pole S；

The switch that the ground line of the pole G is disconnected by the switch control position of the switch control module 108, so that the pole G It disconnects over the ground；

(i, j) a described load programmable module 1091 is concatenated between the pole S and ground wire；

The measurement method of the electrical parameter VDSON of (i, j) a power mos chip is as follows:

The electric current that the pole D is arranged is third current value；

The voltage being arranged between the pole G and the pole S is third voltage value；

By (i, j) a 1091 fictitious load access state of load programmable module, with (i, j) A load programmable module 1091 measures the first voltage value VDSON when pole D and the conducting of the pole S；

The electric current that the pole D is arranged is the 4th current value；

The voltage being arranged between the pole G and the pole S is the 4th voltage value；

By (i, j) a 1091 fictitious load access state of load programmable module, with (i, j) A load programmable module 1091 measures the second voltage value VDSON when pole D and the conducting of the pole S.

As described above, referring to Fig.1 8,23,24,25, it is limited by the test machine maximum current 100A, the survey of VDSON Examination is respectively divided into 8 groups again between two groups, and each group is made of 6 testing stations, in total 16 groups.It is, M=8, N=6,1≤i≤6,0≤j≤8, the serial number odd number of A group testing station are equal to 2 (i+j × 6) -1, the B group test The serial number even number stood is equal to 2 (i+j × 6).

Referring to Figure 23, the third current value is, for example, 8.5A, and the third voltage value is, for example, 5V, and the described 4th Current value is, for example, 2A, and the 4th voltage value is, for example, 10V.As long as it is understood that testing process and product specification type Number license, third current value, third voltage value, the 4th current value, the 4th voltage can be set to the numerical value of any permission.Such as figure Shown in 23 data list, in the case of the third current value electric current is 8.5A, third voltage value is 5V, measure The first voltage value VDSON of the semiconductor power device is lower than 415mV, and electric current IDSON is between 8-9A；Described In the case of third current value electric current is 8.5A, third voltage value is 10V, the first voltage value VDSON is higher than 213mV, low In 400mV；The 4th current value is 2A, the 4th voltage is 10V, the second voltage value VDSON is lower than 100mV and electric current For IDSON between 1.4A and 2.6A, otherwise it is defective products that the semiconductor power device, which is normal chip,.Specific measurement is real The mode of applying can be found in source code shown in Figure 40.Measurement about parameter electric current IDSON not within protection scope of the present invention, Therefore it is no longer described in detail.

Figure 40 shows the survey that the measuring head 100 of concurrent testing equipment shown in fig. 6 is dynamically composed by programming Control Examination circuit is used to test the part of original code diagram illustrating table of the electrical parameter VDSON of PowerMOS device；Figure 41 shows correspondence In part of original code such as sentence 401Micro.DCS_MP.Pins (" SOURCE_dcs ") .VRange of Figure 40 (VRange10), sentence 402Micro.LP.Pins (" SOURCE_lp ") .Connect (Connection::Connect_), language Sentence 403Micro.DCS_MP.Pins (" SOURCE_dcs ") .Connect (DCSConnectSENSE), sentence 4404Micro.Beast.Pins (" DRAIN_beast ") .Voltage (5), sentence 405Micro.Connectivity.Set The circuit diagram of the hardware controls response of Databit (1,8, DatabitOn)；Figure 42 shows concurrent testing shown in fig. 6 and sets The loading current maxima of the standby measuring head 100 and other parameter lists, wherein the measuring head 100 is able to bear 4 most Big voltage is 40 volts, maximum current is 200 amperes；Figure 43 shows the test result chart of the source code of Figure 40；Figure 44: corresponding In another circuit diagram of the hardware controls response of the part of original code of Figure 40, provides program source code and circuit dynamic is controlled The schematically signal of system, can be checked, or require original high definition figure to applicant by amplification diagram.

Parallel test method and equipment based on above-mentioned semiconductor power device, the present invention can very quickly, efficiently The measurement of rate, full-automatic the 100 multinomial electrical parameters that PowerMOS chip is completed by process control, to comprehensively comment Estimate the yields of the PowerMOS chip.

Therefore, the parallel test method of above-mentioned semiconductor power device and equipment can be used for full-automatic chip package Production line, the packing producing line of especially full automatic semiconductor power device, production efficiency is increased to ultimate attainment.

One embodiment of the packaging method of semiconductor power device according to the present invention, referring to Fig.1, the packaging method The following steps are included:

It loads step S1601: wafer is attached on blue film；

Cutting step S1602: the wafer is cut into chip；

Amplexiform step S1603: on the lead frames by the die bonding；

Bonding wire step S1604: the respective pin conductor wire of the solder joint of the chip and the lead frame is passed through into weldering The mode of connecing links together；

Molding step S1605: the chip is encapsulated with epoxy resin by molded mode, forms molding body；

Formula concurrent testing step S1606: parallel test method test according to any one of claim 1 to 10 Semiconductor power device on the lead frame；

Shear forming step S1607: in shear forming station by the remaining pin of the semiconductor power device from described Cutting is separated on lead frame, and by the pin compression moulding of the semiconductor power device, forms independent semiconductor Power device；

Packaging step S1608: the semiconductor power device, which is loaded into pipe or package roll, carries out finished product packing.

Above-mentioned technical proposal is also applied for the full-automatic production line of other chips.

Specifically, as shown in Figure 1, the packaging method of semiconductor power device the following steps are included:

It loads step S1701: wafer is attached on blue film；

Cutting step S1702: the wafer is cut into chip；

Amplexiform step S1703: on the lead frames by the die bonding；

Bonding wire step S1704: the respective pin conductor wire of the solder joint of the chip and the lead frame is passed through into weldering The mode of connecing links together；

Molding step S1705: the chip is encapsulated with epoxy resin by molded mode, forms molding body；

Post cure step S1706: heat cure processing is carried out to the molding body；

Plating step S1707: being electroplated the lead frame, forms encapsulation unit；

Baking procedure S1708: baking heat treatment is carried out to the encapsulation unit；

Markers step S1709: unique 2 D identifying code is marked on the lead frame, wherein use the two dimension The unique information of identification code and corresponding position coordinates in length and breadth as the corresponding semiconductor power device of the encapsulation unit Label, the semiconductor power device have the corresponding position coordinates in length and breadth on the lead frame；

Formula concurrent testing step S1710: semiconductor power device according to any one of claim 1 to 10 Parallel test method tests the chip on the lead frame；

As a result uploading step S1711: the test result of the semiconductor power device with unique information label uploads To server, it to be used for laser printing station, that is, chip non-defective unit print stations；

Non-defective unit printing step S1712: the lead frame is in the laser printing station, according to the test knot of server Fruit carries out laser printing to non-defective unit；

Shear forming step S1713: in shear forming station by the remaining pin of the semiconductor power device from described Cutting is separated on lead frame, and by the pin compression moulding of the semiconductor power device, forms independent semiconductor Power device；

Leakage tests step S1714: on packing machine to the semiconductor power device carry out electric leakage on-off part it is quick Test item test；

Appearance testing procedure S1715: appearance detection is carried out to the semiconductor power device；

Packaging step S1716: the semiconductor power device, which is loaded into pipe or package roll, carries out finished product packing.

Full-automatic encapsulation and survey of the packaging method of above-mentioned semiconductor power device particularly suitable for PowerMOS chip Examination, production efficiency are greatly improved than the prior art.

The preferred or specific embodiment of the invention is described in detail above.It should be appreciated that the technology of this field Personnel make many modifications and variations without the design concept that creative work can be created according to the present invention.Therefore, all In technical field technical staff according to the design concept of the invention pass through on the basis of existing technology logic analysis, reasoning or The limited available technical solution of experiment of person, all should be within the scope of the invention and/or by claims institute In determining protection scope.

Claims (17)

1. the parallel test method of semiconductor power device is used in packaging and testing process, is tested and filled by chip package It sets and concurrent testing is carried out to the semiconductor power device on whole lead frame, wherein

The semiconductor power device is distributed across the molding encapsulation unit of molding on the lead frame；

The chip package test device includes measuring head (100), test bracket (110) and operation board (111), wherein institute Measuring head (100) are stated to include contact circuit board (101), main control board (102), TIB test resource interface board (103), can compile Journey loads load plate (104) and probe contact device (105), and the main control board (102) further includes DCS integration module electricity Road plate (106) and switch control module (108), the test bracket (110) are used to supporting and fixing the measuring head (100), And guaranteeing the relative positioning between operation board (111) and the measuring head (100), the operation board (111) includes Formula chip tray (112)；

Probe contact device (105) includes multiple probes (1051) and bracket (1052), wherein probe (1051) dress It fits on the bracket (1052)；

Contact circuit board (101) has electric simultaneously with all chip pins of all encapsulation units on the lead frame Property connection copper foil printed circuit contact point；

It is characterized by: the parallel test method the following steps are included:

Pre- rib cutting step S1: the segment chip pin of each encapsulation unit is separated with lead frame cutting, and every Another part chip pin of a encapsulation unit is remained connected to the lead frame；

Chip fixing step S2: the lead frame is fixedly mounted on to the formula chip tray of operation board (111) (112) on；

Probe (1051) the alignment step S3: multiple probes (1051) of probe contact device (105) are formed Probe array, the size of space between the probe (1051) and between the chip pin of the encapsulation unit on the lead frame The size of space match on horizontal and vertical, and the second end of each probe (1051) is made to contact electricity with described The corresponding copper foil printed circuit contact point of road plate (101) is electrically connected；

Circuit establishment step S3: the probe (1051) uses contact with platform mode, and the chip pin with the encapsulation unit It is electrical connected, thus, all chip pins of all encapsulation units on the lead frame and the corresponding probe (1051) first end is electrically connected, and then establishes test for semiconductor power device described each of on the lead frame Circuit, in the measuring head (100), the corresponding testing station of the test loop of each semiconductor power device；

Device is grouped step S4: the testing station that test loop has been established is divided into the group testing station two groups: A and B group testing station, Wherein, the serial number odd number of A group testing station is equal to (2 × I-1), the serial number even number of B group testing station, etc. In (2 × I), and I >=1；

Concurrent testing step S5: the switch control position of the switch control module (108) controls the A group by table tennis test pattern Testing station is in state to be tested, and the measuring head (100) carries out simultaneously the semiconductor power device on A group testing station Row test；After completing the test of A group, the switch control position of the switch control module (108) controls institute by table tennis test pattern It states B group testing station and is in state to be tested, the measuring head (100) is to the semiconductor power device on B group testing station Carry out concurrent testing.

2. the parallel test method of semiconductor power device according to claim 1, it is characterised in that: the device grouping Step S4 further includes following sub-step:

Group divide sub-step S21: according to needed for the semiconductor power device test electric current or test voltage size and The maximum current or voltage that the measuring head (100) is able to bear, it is respectively that A group testing station and B group testing station is each It is divided into M group, there is N number of testing station in every group, wherein the serial number odd number of A group testing station is equal to 2 (i+j × N) -1, The serial number even number of B group testing station is equal to 2 (i+j × N), wherein I=(i+j × N), i are testing station serial number, and j is Group's serial number, and 1≤i≤N, 0≤j≤M, M >=0, N >=1；

The concurrent testing step S5 is substituted, carries out concurrent testing as follows:

Group concurrent testing step S22: test pattern controls institute in order for the switch control position of the switch control module (108) The semiconductor power device that measuring head (100) test each group is stated, also, in each group, the switch control module (108) switch control position is by the semiconductor power device for belonging to A group in table tennis test pattern respectively concurrent testing group Part and the semiconductor power device for belonging to B group.

3. the parallel test method of semiconductor power device according to claim 2, it is characterised in that: using high current It tests in the case of the semiconductor power device, probe contact device (105) is the every of the semiconductor power device A high current pin provides the probe (1051) of quantification, is formed and combines the probe (1051), and passes through described group It closes the probe (1051) and contacts the high current pin.

4. the parallel test method of semiconductor power device according to claim 1, it is characterised in that: the governor circuit Plate (102) further includes TIB board interface and the first attachment device, wherein

The TIB board interface is for connecting the TIB test resource interface board (103), the TIB test resource interface board It (103) include digital channel and PPMU unit；

First attachment device is for connecting the main control board (102) and the digital channel, the PPMU unit.

5. the parallel test method of semiconductor power device according to claim 1, it is characterised in that: the switch control Module (108) includes switch control position, wherein the switch control position can drive micrometering to try transceiver, can also drive MOS Semiconductor switch, the micrometering examination transponder chip have 16 programming Control switches, and the programming Control switch can pass through Single-wire-protocol frame individually programming Control.

6. the parallel test method of semiconductor power device according to claim 1, it is characterised in that: the governor circuit Plate (102) includes loading programmable board (109), and the load programmable board (109) includes the load programmable module (1091), the load programmable module (1091) include load programmable unit (1092), difference instrument channel (1093) and Time measuring unit (1094).

7. the parallel test method of semiconductor power device according to claim 1, it is characterised in that: described programmable negative Carrying load plate (104) includes programmable inductive load (1041) and programmable ohmic load (1042)；

The programmable load load plate (104) be by the contact circuit board (101) and the main control board (102), The programmable inductive load (1041) that test is needed to use and the programmable ohmic load (1042) are as negative Load is loaded into measurement, provides inductive load (1041) and ohmic load (1042) for each testing station.

8. the parallel test method of semiconductor power device according to claim 1, it is characterised in that: the governor circuit Plate (102) further includes floating Driver Card (107), and the floating Driver Card (107) includes driving measurement source (1071) of floating, Wherein, the floating driving source is by light-coupled isolation, and programmable floating voltage digital drive.

9. the parallel test method of semiconductor power device according to claim 1, it is characterised in that: the probe contact Device (105) further includes high temperature test heating device (114)；

The parallel test method further includes following testing procedure:

High temperature test step 91: the lead frame is heated to one and determines temperature by the high temperature test heating device (114) Then degree carries out high temperature test by the concurrent testing step S5 again.

10. the parallel test method of semiconductor power device according to claim 1, it is characterised in that: the parallel survey Method for testing further includes following steps:

A step 101 is surveyed in replacement: after the test for completing to be measured formula chip (113), the operation board (111) is replaced automatically The next to be measured formula chip (113).

11. the parallel test method of semiconductor power device according to any one of claim 1 to 10, feature exist In: the semiconductor power device is power mos chip.

12. the parallel test method of semiconductor power device according to claim 11, it is characterised in that: multiple described half Conductor power device connects on the lead frames, wherein the pole S and the pole G of each semiconductor power device are by from the lead frame It cuts and separates on frame, also, the pole D of all semiconductor power devices is connected together.

13. the parallel test method of semiconductor power device according to claim 12, it is characterised in that: i-th power The test loop of the electrical parameter IDSS of MOS chip is established as follows:

The setting pole S is connected to i-th DCS measuring instrumentss；

Close the switch in the connection source of the pole G；

Disconnect the switch of the ground line of the pole G；

The setting pole D is connected to high-power voltage and current source (300)；

The measurement method of the electrical parameter IDSS of the i-th power mos chip is as follows:

The source output voltage that the arrival pole D is arranged is the first voltage value；

By the i-th DCS measuring instrumentss, data are acquired by determining time interval, are averaged, first as measured IDSS value；

The source output voltage that the arrival pole D is arranged is second voltage value；

By the i-th DCS measuring instrumentss, data are acquired by determining time interval, are averaged, second as measured IDSS value.

14. the parallel test method of semiconductor power device according to claim 12, it is characterised in that:

The test loop of the electrical parameter VTH of i-th power mos chip is established as follows:

The setting pole S is connected to i-th DCS measuring instrumentss；

The switch that the ground line of the pole G is closed by the switch control position of the switch control module (108), so that the G is extremely right Ground conducting；

The measurement method of the electrical parameter VTH of the i-th power mos chip is as follows:

The pin sourcing current that the i-th DCS measuring instrumentss are arranged is the first current value；

By the i-th DCS measuring instrumentss, data are acquired by determining time interval, are averaged, first as measured VTH value；

The pin sourcing current that the i-th DCS measuring instrumentss are arranged is the second current value；

By the i-th DCS measuring instrumentss, data are acquired by determining time interval, are averaged, second as measured VTH value.

15. the parallel test method of semiconductor power device according to claim 12, it is characterised in that:

Parallel test method as described in claim 2 carries out concurrent testing, wherein

The test loop of the electrical parameter VDSON of (i, j) a described power mos chip is established as follows:

The pole D is connected to high-power voltage and current source (300)；

The source PPMU is accessed between the pole G and the pole S；

The switch that the ground line of the pole G is disconnected by the switch control position of switch control module (108), so that the pole G is broken over the ground It opens；

(i, j) a described load programmable module (1091) is concatenated between the pole S and ground wire；

The measurement method of the electrical parameter VDSON of (i, j) a power mos chip is as follows:

The electric current that the pole D is arranged is third current value；

The voltage being arranged between the pole G and the pole S is third voltage value；

It is a with (i, j) by (i, j) a load programmable module (1091) fictitious load access state The first voltage value VDSON when load programmable module (1091) the measurement pole D and the pole S are connected；

The electric current that the pole D is arranged is the 4th current value；

The voltage being arranged between the pole G and the pole S is the 4th voltage value；

It is a with (i, j) by (i, j) a load programmable module (1091) fictitious load access state Second voltage value VDSON when load programmable module (1091) the measurement pole D and the pole S are connected.

16. the packaging method of semiconductor power device, it is characterised in that: the packaging method the following steps are included:

It loads step S1601: wafer is attached on blue film；

Cutting step S1602: the wafer is cut into chip；

Amplexiform step S1603: on the lead frames by the die bonding；

Bonding wire step S1604: the respective pin of the solder joint of the chip and lead frame conductor wire is passed through into welding side Formula links together；

Molding step S1605: the chip is encapsulated with epoxy resin by molded mode, forms molding body；

Formula concurrent testing step S1606: described in parallel test method test according to any one of claim 1 to 10 Semiconductor power device on lead frame；

Shear forming step S1607: in shear forming station by the remaining pin of the semiconductor power device from the lead Cutting is separated on frame, and by the pin compression moulding of the semiconductor power device, forms independent semiconductor power Device；

Packaging step S1608: the semiconductor power device, which is loaded into pipe or package roll, carries out finished product packing.

17. the packaging method of semiconductor power device, it is characterised in that: the packaging method the following steps are included:

It loads step S1701: wafer is attached on blue film；

Cutting step S1702: the wafer is cut into chip；

Amplexiform step S1703: on the lead frames by the die bonding；

Bonding wire step S1704: the respective pin of the solder joint of the chip and lead frame conductor wire is passed through into welding side Formula links together；

Molding step S1705: the chip is encapsulated with epoxy resin by molded mode, forms molding body；

Post cure step S1706: heat cure processing is carried out to the molding body；

Plating step S1707: being electroplated the lead frame, forms encapsulation unit；

Baking procedure S1708: baking heat treatment is carried out to the encapsulation unit；

Markers step S1709: unique 2 D identifying code is marked on the lead frame, wherein use the two dimension mark Code and corresponding position coordinates in length and breadth are marked as the unique information of the corresponding semiconductor power device of the encapsulation unit, The semiconductor power device has the corresponding position coordinates in length and breadth on the lead frame；

Formula concurrent testing step S1710: semiconductor power device according to any one of claim 1 to 10 it is parallel Test method tests the chip on the lead frame；

As a result uploading step S1711: the test result of the semiconductor power device with unique information label is uploaded to clothes Business device, is used for laser printing station, that is, chip non-defective unit print stations；

Non-defective unit printing step S1712: the lead frame is given in the laser printing station according to the test result of server Non-defective unit carries out laser printing；

Shear forming step S1713: in shear forming station by the remaining pin of the semiconductor power device from the lead Cutting is separated on frame, and by the pin compression moulding of the semiconductor power device, forms independent semiconductor power Device；

Leakage tests step S1714: electric leakage on-off part is carried out to the semiconductor power device on packing machine and is quickly tested Project testing；

Appearance testing procedure S1715: appearance detection is carried out to the semiconductor power device；

Packaging step S1716: the semiconductor power device, which is loaded into pipe or package roll, carries out finished product packing.