CN217112602U - Semiconductor device module test system - Google Patents
Semiconductor device module test system Download PDFInfo
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- CN217112602U CN217112602U CN202123109631.1U CN202123109631U CN217112602U CN 217112602 U CN217112602 U CN 217112602U CN 202123109631 U CN202123109631 U CN 202123109631U CN 217112602 U CN217112602 U CN 217112602U
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Abstract
The application discloses semiconductor device module test system, its characterized in that, semiconductor device module test system includes: an upper computer; the data processing device is coupled with the upper computer; the power supply is coupled with the upper computer; the test terminal is respectively coupled with the data processing device and the power supply; the upper computer sends a test instruction to the data processing device and the power supply, the data processing device sends the test instruction to the test terminal, the power supply provides current and voltage for the test terminal according to the test instruction, the test terminal is used for connecting a plurality of elements to be tested and feeding detection information back to the upper computer, and the test instruction is formulated by the upper computer according to the test requirements of the elements to be tested. The technical scheme can test a plurality of elements to be tested simultaneously, and has high test speed and high test efficiency; simultaneously, the technical scheme directly obtains the current and voltage test value of the power supply through the upper computer, so that the test precision is higher.
Description
Technical Field
The application relates to the field of semiconductor testing, in particular to a semiconductor device module testing system.
Background
At present, the development of the semiconductor industry in China is relatively lagged behind, a large number of chips and equipment are purchased from foreign countries, and after the chips and the equipment are limited by the United states recently, the domestic industry chain cannot meet the production requirement, so that huge loss is caused, and the development of the domestic semiconductor industry chain is promoted. The semiconductor is used as a mass production object, and a large-scale automatic test is needed, so that an automatic semiconductor test system is produced.
However, the conventional automatic semiconductor test system has low test efficiency, low automation level and low test precision.
Disclosure of Invention
The application provides a semiconductor device module testing system, which solves the problems of low testing efficiency, low automation level and low testing precision of an automatic semiconductor testing system during the existing large-scale automatic testing.
In order to solve the technical problem, the application adopts a technical scheme that: provided is a semiconductor device module test system, characterized in that the semiconductor device module test system includes: an upper computer; the data processing device is coupled with the upper computer; the power supply is coupled with the upper computer; the test terminal is respectively coupled with the data processing device and the power supply; the upper computer sends a test instruction to the data processing device and the power supply, the data processing device sends the test instruction to the test terminal, the power supply provides current and voltage for the test terminal according to the test instruction, the test terminal is used for connecting a plurality of elements to be tested and feeding detection information back to the upper computer, and the test instruction is formulated by the upper computer according to the test requirements of the elements to be tested.
The testing system of the semiconductor device module further comprises a concentrator, the upper computer is connected with the power supply and the data processing device through the concentrator, and the concentrator carries out protocol conversion processing on the testing instruction, so that the testing instruction is matched and communicated with the power supply and the data processing device.
The upper computer comprises a test instruction processing device and a display screen, the test instruction processing device is used for editing and sending test instructions, and the display screen is used for displaying test results of the to-be-tested elements.
Wherein, the data processing device includes: programmable logic array data processing device, singlechip or wireless data acquisition device.
The power supply comprises a voltage source and a current source, the current testing precision provided by the power supply reaches 10pA, and the voltage testing precision provided by the power supply reaches 10 uV.
The power supply provides current and voltage for one or more test terminals, and obtains a current and voltage test value of the element to be tested and feeds the current and voltage test value back to the upper computer.
The testing terminal comprises a plurality of triggers, a plurality of drivers and a plurality of testing channels, wherein the triggers control the drivers to work, the drivers are used for driving the testing channels to be switched, and the testing channels are connected with the elements to be tested.
The trigger is connected with the data processing device and used for driving the driver to work according to the test instruction.
The drivers drive the test channels to convert the connection relation, and serial connection conversion can be carried out.
The testing channel is internally provided with a plurality of relay switches, and the relay switches are connected with the element to be tested.
The beneficial effect of this application is: being different from the situation of the prior art, the present application provides a semiconductor device module test system, which is characterized in that the semiconductor device module test system includes: an upper computer; the data processing device is coupled with the upper computer; the power supply is coupled with the upper computer; the test terminal is respectively coupled with the data processing device and the power supply; the upper computer sends a test instruction to the data processing device and the power supply, the data processing device sends the test instruction to the test terminal, the power supply provides current and voltage for the test terminal according to the test instruction, the test terminal is used for connecting a plurality of elements to be tested and feeding detection information back to the upper computer, and the test instruction is formulated by the upper computer according to the test requirements of the elements to be tested. The technical scheme can test a plurality of elements to be tested simultaneously, and has high test speed and high test efficiency; simultaneously, the technical scheme directly obtains the current and voltage test value of the power supply through the upper computer, so that the test precision is higher.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, it is obvious that the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without inventive efforts, wherein:
fig. 1 is a schematic structural diagram of an embodiment of a semiconductor device module testing system provided in the present application.
Fig. 2 is a schematic structural diagram of another embodiment of a semiconductor device module testing system provided in the present application.
Fig. 3 is a schematic structural diagram of an embodiment of a test terminal in the semiconductor device module test system provided in the present application.
Detailed Description
In order to make the technical problems solved, the technical solutions adopted, and the technical effects achieved by the present application clearer, the technical solutions of the embodiments of the present application will be further described in detail below with reference to the accompanying drawings.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a semiconductor device module testing system according to a first embodiment of the present disclosure. The semiconductor device module test system 10 of the present embodiment includes an upper computer 101, a data processing apparatus 102, a power supply 103, and a test terminal 104.
In this embodiment, the upper computer 101 is connected to the data processing device 102 and the power supply 103, respectively, the data processing device 102 is connected to the test terminal 104, and the power supply 103 is connected to the test terminal 104. Wherein, the upper computer 101 sets a test instruction according to the test requirement of the device to be tested and then sends the test instruction to the data processing device 102 and the power supply 103, the data processing device 102 sends the test instruction to the test terminal 104, the power supply 103 provides current and voltage for the test terminal 104 according to the test instruction, the test terminal 104 is connected with the device to be tested and then tests the device to be tested according to the test instruction, the power supply 103 provides current and voltage for the test device and simultaneously obtains the current and voltage information of the test of the device to be tested, and feeds the obtained current and voltage information back to the upper computer 101, the upper computer 101 displays the test result after processing the current and voltage information, that is, the upper computer 101 sets the test instruction according to the test requirement of the device to be tested in this embodiment, the data processing device 102 controls the test terminal 104 to test according to the test instruction, the power supply 103 provides current and voltage for the test terminal 104, when the element to be tested is connected with the test terminal 104, the power supply 103 simultaneously obtains current and voltage values of the element to be tested during testing, the current and voltage values are fed back to the upper computer 101, and the upper computer 101 analyzes and displays a test result of the element to be tested according to the current and voltage values.
By the mode, the test data information of the element to be tested can be acquired in real time, and the upper computer 101 is high in data analysis efficiency, so that the time required for testing the element to be tested is short, and the test efficiency is high. Because the current and voltage provided by the power supply 103 have high precision, the current testing precision can reach 10pA, and the voltage testing precision reaches 10uV, when the testing terminal 104 tests the element to be tested, the current and voltage value with higher precision can be obtained, and can be fed back to the upper computer 101, so that the testing precision of the semiconductor device module testing system 10 is high.
Further, in order to improve the utilization rate of the upper computer 101 and the number of the elements to be tested in the semiconductor device module testing system 10 at the same time, a concentrator is added in the second embodiment of the present application, and by using the concentrator, the simultaneous testing capability of the semiconductor device module testing system 10 is greatly improved. As shown in fig. 2, fig. 2 is a schematic structural diagram of a semiconductor device module testing system according to a second embodiment of the present disclosure. The semiconductor device module test system 20 of the present embodiment includes an upper computer 201, a hub 202, a data processing apparatus 203, a power supply 204, and a test terminal 205.
In this embodiment, the host computer 201 is connected to the hub 202, the hub 202 is connected to the data processing device 203 and the power supply 204, the data processing device 203 is connected to the test terminal 205, and the power supply 204 is connected to the test terminal 205. Wherein, the upper computer 201 comprises an industrial computer and matched upper computer 201 software. In other embodiments, the upper computer 201 may further be connected to a plurality of hubs 202, the hubs 202 may further be connected to a plurality of data processing devices 203, the hubs 202 may further be connected to a plurality of power supplies 204, the data processing devices 203 may further be connected to a plurality of test terminals 205, the power supplies 204 may further be connected to a plurality of test terminals 205, one power supply 204205 may further be used in cooperation with a plurality of data processing devices 203, and the test terminals 205 are coupled to the device under test during testing. Also, the HUB 202 is preferably a USB HUB HUB.
In this embodiment, the upper computer 201 sets a test instruction according to a test requirement of the device to be tested and sends the test instruction to the hub 202, the hub 202 performs protocol conversion processing on the received test instruction, so that the test instruction is matched and communicated with the data processing device 203 and the power supply 204, then sends the test instruction to the data processing device 203 and the power supply 204, the data processing device 203 sends the test instruction to the test terminal 205, the test terminal 205 tests the device to be tested according to the test instruction, the power supply 204 provides current and voltage for the test terminal 205 according to the test instruction, obtains a current and voltage test value of the device to be tested in real time, and sends the current and voltage test value to the upper computer 201, and the upper computer 201 performs data analysis and display on the current and voltage test value.
Through the mode, the hubs 202 are added in the semiconductor device module testing system 20, so that the upper computer 201 can control the data processing devices 203 and the power supply 204 simultaneously, and the testing result can be displayed in real time due to the fact that the upper computer 201 is high in data analysis capacity, and therefore the working efficiency and the working quality of the upper computer 201 are not affected by the fact that the hubs 202 are added. That is to say, the upper computer 201 can obtain the current and voltage test values of the device under test tested by the plurality of test terminals 205 through the connection hub 202, and obtain the test result of the device under test according to the current and voltage test values.
In the semiconductor device module testing system 20, the testing terminal 205 is directly connected to the device to be tested, and the testing terminal 205 automatically tests the device to be tested according to the testing instruction.
As shown in fig. 3, fig. 3 is a schematic structural diagram of an embodiment of a test terminal in the semiconductor device module test system provided in the present application. The test terminal 30 is provided with a plurality of triggers 301, a plurality of drivers 302, and a plurality of test channels 303, wherein a plurality of relay switches 304 are provided in the test channels 303, and the relay switches 304 are coupled with the device under test during testing.
In a specific test process, the relay switch 304 in the test channel 303 is connected with an element to be tested, the upper computer sets a test instruction according to the test requirement of the element to be tested and sends the test instruction to the data processing device and the power supply, the data processing device sends the test instruction to the trigger 301, the trigger 301 controls the driver 302 to drive the test channel 303 to switch according to the test instruction, the test channel 303 can be subjected to series-parallel conversion, and the relay switch 304 in the test channel 303 is connected with the element to be tested; the power supply provides high-precision voltage and current for the element to be tested according to the test instruction, wherein the current precision reaches 10pA, the voltage precision reaches 10uV, because the power supply precision is higher, the current voltage value provided during the test is equal to the current voltage test value of the element to be tested during the test, so the power supply can obtain the current voltage test value of the element to be tested during the test in real time and feed back the current voltage test value to the upper computer, and the upper computer analyzes and displays the test result according to the test value.
Through the above manner, the test terminal 30 can automatically test a plurality of devices to be tested, and can automatically change the test instruction according to the devices to be tested, thereby realizing a higher degree of automatic test.
In a specific implementation mode, the element to be tested can be a storage chip or a logic chip, a plurality of storage chips or logic chips are connected with the trigger, a tester sets a corresponding test instruction on the upper computer and sends the test instruction to the data processing device, the data processing device sends the test instruction to the test terminal, the driver, the trigger and the power supply perform corresponding operation on the element to be tested according to the test instruction, the plurality of storage chips or logic chips are tested according to the set test parameters until the time required to be tested is over, and the power supply sends a power supply voltage test value to the upper computer in real time for analysis and display.
In another specific implementation mode, the component to be tested can be a storage chip aging board, a plurality of storage chip aging boards are connected with the trigger, a tester sets a corresponding test instruction on the upper computer and sends the test instruction to the data processing device, the data processing device sends the test instruction to the test terminal, the driver and the trigger are the power supply and correspondingly operate the component to be tested according to the test instruction, the storage chip aging boards are tested according to the set test parameters until the time required for testing is finished, and the power supply sends the power supply voltage test value to the upper computer in real time for analysis and display.
In the above embodiments, for convenience of explaining the structure and the work flow of the semiconductor device module testing system, only a small number of upper computers, hubs, data processing devices, power supplies, and test terminals are included. In actual production activities, a plurality of hubs can be connected to an upper computer according to test requirements, the hubs can also be simultaneously connected with a plurality of data processing devices and a power supply, and the power supply can be simultaneously matched with the plurality of data processing devices for use; the data processing device can be connected with a plurality of test terminals, and the power supply can provide power for the plurality of test terminals and feed back the test result to the upper computer. The technical scheme can realize the simultaneous measurement of a plurality of elements to be tested, has high test speed and high test efficiency, and can ensure high precision of the current and voltage test value of the elements to be tested because of high precision of the current and voltage of the power supply.
Claims (10)
1. A semiconductor device module test system, comprising:
an upper computer;
a data processing device coupled with the upper computer;
a power source coupled with the upper computer;
a test terminal coupled to the data processing device and the power supply, respectively;
the upper computer sends a test instruction to the data processing device and the power supply, the data processing device sends the test instruction to the test terminal, the power supply provides current and voltage for the test terminal according to the test instruction, the test terminal is used for connecting a plurality of elements to be tested and feeding back detection information to the upper computer, and the test instruction is formulated by the upper computer according to the test requirements of the elements to be tested.
2. The semiconductor device module test system according to claim 1, further comprising a hub, wherein the upper computer is connected to the power supply and the data processing device through the hub, and the hub performs protocol conversion processing on the test command, so that the test command is adapted and communicated with the power supply and the data processing device.
3. The semiconductor device module test system according to claim 1, wherein the upper computer comprises a test instruction processing device and a display screen, wherein the test instruction processing device is used for editing and sending the test instruction, and the display screen is used for displaying the test result of the element to be tested.
4. The semiconductor device module test system of claim 1, wherein the data processing apparatus comprises: programmable logic array data processing device, singlechip or wireless data acquisition device.
5. The semiconductor device module test system of claim 1, wherein the power supply comprises a voltage source and a current source, and the power supply provides a current with a test accuracy of 10pA and a voltage with a test accuracy of 10 uV.
6. The semiconductor device module test system of claim 1, wherein the power supply provides current and voltage to one or more of the test terminals, and obtains a current and voltage test value of the device under test and feeds the current and voltage test value back to the host computer.
7. The semiconductor device module test system of claim 1, wherein the test terminal comprises a plurality of flip-flops, a plurality of drivers, and a plurality of test channels, wherein the flip-flops control the drivers to operate, the drivers are used for driving the switching of the test channels, and the test channels are connected to the device under test.
8. The semiconductor device module test system of claim 7, wherein the flip-flop is connected to the data processing device for driving the driver to operate according to the test command.
9. The semiconductor device module test system of claim 7, wherein a plurality of the test channels are connected, and the driver drives the test channels to switch the connection relationship so as to perform serial-to-parallel conversion.
10. The semiconductor device module test system according to claim 7, wherein a plurality of relay switches are provided in the test channel, the relay switches being connected to the element under test.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202123109631.1U CN217112602U (en) | 2021-12-10 | 2021-12-10 | Semiconductor device module test system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202123109631.1U CN217112602U (en) | 2021-12-10 | 2021-12-10 | Semiconductor device module test system |
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| Publication Number | Publication Date |
|---|---|
| CN217112602U true CN217112602U (en) | 2022-08-02 |
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| CN202123109631.1U Active CN217112602U (en) | 2021-12-10 | 2021-12-10 | Semiconductor device module test system |
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| CN (1) | CN217112602U (en) |
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- 2021-12-10 CN CN202123109631.1U patent/CN217112602U/en active Active
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