CN115603669A - Differential amplifier circuit - Google Patents
Differential amplifier circuit Download PDFInfo
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- CN115603669A CN115603669A CN202211185328.6A CN202211185328A CN115603669A CN 115603669 A CN115603669 A CN 115603669A CN 202211185328 A CN202211185328 A CN 202211185328A CN 115603669 A CN115603669 A CN 115603669A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/26—Modifications of amplifiers to reduce influence of noise generated by amplifying elements
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/56—Modifications of input or output impedances, not otherwise provided for
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
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Abstract
The application provides a differential amplification circuit, it includes: the first input stage comprises an input pair tube and a constant current source, wherein the input pair tube is an N-channel JFET, a grid electrode receives an input signal, a drain electrode is used as an output end of the first input stage, and the drain electrode is connected to a source electrode through the constant current source in a feedback mode. According to the differential amplification circuit, the first input stage adopts an N-channel JFET as a topological structure of an input geminate transistor, the input impedance is extremely high, and the input noise is extremely low.
Description
Technical Field
The application relates to the technical field of circuit design, in particular to a differential amplification circuit.
Background
The preceding stage differential amplifier circuit is a core key circuit of a general preposed voltage amplifier and directly determines various performances of the amplifier, such as input noise, bandwidth, gain, input impedance, common mode rejection ratio, input range and the like. If an integrated operational amplifier is used in the front-stage differential amplifier circuit, the requirements of high input impedance and low input noise cannot be met at the same time, because the operational amplifier with high input impedance generally has high noise, and the operational amplifier with low input noise has insufficient input impedance.
Disclosure of Invention
In view of the foregoing background, it is an object of the present application to provide a differential amplifier circuit having a high input impedance and low input noise.
In order to achieve the above object, the present application provides a differential amplification circuit comprising: the first input stage comprises an input pair tube and a constant current source, wherein the input pair tube is an N-channel JFET, a grid electrode receives an input signal, a drain electrode is used as an output end of the first input stage, and the drain electrode is connected to a source electrode through the constant current source in a feedback mode.
In an embodiment, the constant current source includes a first amplifier and a schottky diode, a non-inverting input terminal of the first amplifier is grounded via a fifth capacitor and is connected to a cathode of the schottky diode via a ninth resistor, the cathode of the schottky diode is further connected to a positive power supply via an eighth resistor, an anode of the schottky diode is grounded, inverting input terminals of the first amplifier are connected to drains of the pair of input transistors via a fourth resistor and a fifth resistor, respectively, and an output terminal of the first amplifier is connected to sources of the pair of input transistors via a seventh resistor.
In an embodiment, the gates of the input pair transistors are further grounded via an input resistor, the drains of the input pair transistors are further connected to a positive power supply via a drain resistor, the sources of the input pair transistors are further connected to the seventh resistor via a source resistor, and the seventh resistor is further connected to a negative power supply via a tenth resistor.
In an embodiment, the differential amplifier circuit further includes a second amplifier stage, the second amplifier stage includes a second amplifier and a feedback resistor, a positive input end and a negative input end of the second amplifier are connected to two drains of the pair of input transistors, the pair of input transistors includes a first input transistor and a second input transistor, an output end of the second amplifier is connected to a source of the second input transistor through the feedback resistor, and an output end of the second amplifier is an output end of the differential amplifier circuit.
In an embodiment, the differential amplifier circuit further includes a gain selection unit, the gain selection unit includes a relay, the source resistors include a first source resistor, a second source resistor, a third source resistor, a fourth source resistor, a fifth source resistor, and a sixth source resistor, the first source resistor, the third source resistor, and the fifth source resistor are sequentially connected in series, the second source resistor, the fourth source resistor, and the sixth source resistor are sequentially connected in series, a free end of the second source resistor is connected to the source of the second input tube, a free end of the first source resistor is connected to the source of the first input tube, free ends of the fifth source resistor and the sixth source resistor are both connected to the seventh resistor, a common terminal of the relay is connected to a connection point of the second source resistor and the fourth source resistor, a set terminal is grounded via the sixth resistor, a reset terminal is connected to a connection point of the first source resistor and the third source resistor, and the differential amplifier has a low gain mode and a high gain mode.
In an embodiment, the differential amplification circuit further includes a low-gain bias adjustment unit, the low-gain bias adjustment unit includes a first adjustable potentiometer, two ends of the first adjustable potentiometer are respectively connected to a positive power supply and a negative power supply, and a middle adjustment end of the first adjustable potentiometer is connected to the setting end of the relay through the sixth resistor.
In an embodiment, the differential amplification circuit further includes a high-gain bias adjustment unit, the high-gain bias adjustment unit includes a second adjustable potentiometer, two ends of the second adjustable potentiometer are respectively connected to the positive and negative power supplies, and a middle adjustment end of the second adjustable potentiometer is connected to the drain of the first input tube via a first resistor.
In an embodiment, the differential amplifier circuit further includes a high-gain common-mode rejection ratio adjusting unit, the high-gain common-mode rejection ratio adjusting unit includes a third adjustable potentiometer, one end of the third adjustable potentiometer is connected to the source of the first input tube via a second resistor, and the other end and the middle adjusting end of the third adjustable potentiometer are both grounded.
In an embodiment, the differential amplifier circuit further includes a low-gain common-mode rejection ratio adjusting unit, the low-gain common-mode rejection ratio adjusting unit includes a fourth adjustable potentiometer, two ends of the fourth adjustable potentiometer are respectively connected to a connection point of the third source resistor and the fifth source resistor and a connection point of the fourth source resistor and the sixth source resistor, and a middle adjusting end of the fourth adjustable potentiometer is connected to the seventh resistor.
In one embodiment, two working voltage terminals of the first amplifier are respectively connected to a positive power supply and a negative power supply, and are respectively grounded through a first capacitor and a second capacitor; two working voltage ends of the second amplifier are respectively connected with a positive power supply and a negative power supply and are respectively grounded through a third capacitor and a fourth capacitor; the drain resistor comprises a zeroth drain resistor, a first drain resistor and a second drain resistor, and the first drain resistor and the second drain resistor are respectively connected with the drains of the first input tube and the second input tube and are connected with the positive power supply through the zeroth drain resistor.
According to the differential amplification circuit, the first input stage adopts an N-channel JFET as a topological structure of an input geminate transistor, the input impedance is extremely high, and the input noise is extremely low.
Drawings
The drawings described herein are for illustration purposes only and are not intended to limit the scope of the present disclosure in any way. In addition, the shapes, the proportional sizes, and the like of the respective members in the drawings are merely schematic for assisting the understanding of the present application, and are not particularly limited to the shapes, the proportional sizes, and the like of the respective members in the present application. The application can be carried out by a person skilled in the art, in the light of the teaching of the application, selecting from a variety of possible shapes and proportional dimensions according to the specific case. In the drawings:
fig. 1 is a schematic circuit diagram of a differential amplifier circuit according to an embodiment of the present disclosure;
fig. 2 is a schematic circuit diagram of a differential amplifier circuit in a low gain mode according to an embodiment of the present disclosure;
fig. 3 is a schematic circuit diagram of a differential amplifier circuit in a high gain mode according to an embodiment of the present disclosure;
fig. 4 is a schematic circuit diagram of a differential amplifier circuit according to another embodiment of the present application.
Detailed Description
In order to make those skilled in the art better understand the technical solutions in the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Referring to fig. 1, an embodiment of the present invention provides a differential amplifier circuit, which includes: the first input stage comprises an input pair tube and a constant current source, wherein the input pair tube is an N-channel JFET, a grid electrode receives an input signal, a drain electrode serves as an output end of the first input stage, and the drain electrode is connected to a source electrode through the constant current source in a feedback mode. In the first amplification stage of the differential amplification circuit, an N-channel JFET (junction field effect transistor) is used as a topological structure of an input geminate transistor, the N-channel JFET has extremely high input impedance and extremely low input noise, for example, in a specific embodiment, the N-channel JFET input geminate transistor has a matched symmetrical structure, the input impedance is more than or equal to 100G omega, and the input noise is less than or equal to 1.5nV/Hz 0.5 @1kHz. Therefore, the differential amplifier circuit described herein has high input impedance and low input noise. In a specific embodiment, the gates of the input pair transistors are also grounded via an input resistor, for example, the input pair transistors include a first input transistor J 1 A second input pipe J 2 The input resistor comprises a first input resistor R in1 A second input resistor R in2 Said first inlet pipe J 1 A second input pipe J 2 Gate G of 1 、G 2 Respectively via the first input resistance R in1 A second input resistor R in2 Ground, wherein R is set in1 ＝R in2 ＝R in Because the input impedance of the JFET tube is very high (more than or equal to 100G omega), the complete difference is obtained according to a resistance parallel formulaThe input impedance of the partial amplifying circuit is approximately equal to R in 。
In one embodiment, the constant current source includes a first amplifier OPA1 and a schottky diode ZD1, and a non-inverting input terminal of the first amplifier OPA1 is connected to a fifth capacitor C 5 Grounded and through a ninth resistor R 9 The cathode of the Schottky diode ZD1 is connected, and the cathode of the Schottky diode ZD1 is also connected through an eighth resistor R 8 A positive power supply VCC is connected, the anode of the Schottky diode ZD1 is grounded, and the inverting input end of the first amplifier OPA1 is respectively connected with the fourth resistor R 4 A fifth resistor R 5 Drain electrode D connected with the input pair tube 1 、D 2 The output terminal of the first amplifier OPA1 is connected to a seventh resistor R 7 Source S connected to the input pair transistor 1 、S 2 . In one embodiment, the drains D of the input pair transistors 1 、D 2 Further connected to a positive power supply VCC via a drain resistance comprising a zeroth drain resistance R d0 A first drain resistor R d1 A second drain resistor R d2 The first drain resistance R d1 A second drain resistor R d2 Are respectively connected with the first input pipe J 1 A second input pipe J 2 Drain electrode D of 1 、D 2 And via said zeroth drain resistance R d0 The positive power supply VCC is connected. A constant current source composed of a first amplifier OPA1 and a schottky diode ZD1 is connected to the source of the input pair transistor, and flows through a seventh resistor R 7 The current of the Schottky diode ZD1 is constant and constant voltage V is output d To the non-inverting input of the first amplifier OPA1, the inverting input of the first amplifier OPA1 being connected to the drains of the input pair of transistors, V according to the principle of virtual short-break d1 ＝V d2 ＝V d And set R d1 ＝R d2 ＝R d With a drain current of I d ＝(VCC-V d )/(0.5*R d0 +R d ) Changing the resistance value can set the appropriate quiescent operating point for the input pair transistors.
In one embodiment, the differential amplification circuit further comprises a second amplification stage, the second amplification stageComprises a second amplifier OPA2 and a feedback resistor R f The positive and negative input ends of the second amplifier OPA2 are connected with two drains D of the input pair tube 1 、D 2 The output of the second amplifier OPA2 is connected via the feedback resistor R f Connecting the second input pipe J 2 Source electrode S of 2 And, an output terminal of the second amplifier OPA2 is an output terminal of the differential amplifying circuit. In one embodiment, the sources S of the input pair transistors 1 、S 2 Also via the source resistance R S Connecting the seventh resistor R 7 Said seventh resistance R 7 Also via a tenth resistor R 10 A negative supply VEE is connected. According to the principle of negative feedback amplification circuit, the amplification factor A =1+R f /R s . In a specific embodiment, the voltage noise spectral density of the second amplifier OPA2 is less than or equal to 5nV/Hz 0.5 @1kHz, gain-bandwidth product greater than or equal to 50MHz.
In a general purpose pre-voltage amplification instrument, it is usually necessary to set different amplification factors starting from 1. If the amplification factor of the preceding stage differential amplification stage is 1, then the preceding stage differential amplification stage is used for amplifying, and when the amplification factor is set to be high, the input noise performance of the preposed voltage amplification instrument is poor; if the amplification factor of the front stage differential amplification stage is large and then the front stage differential amplification stage is attenuated, the input range performance of the front-end voltage amplification instrument is not good when the amplification factor is set to be low. If the source resistance can be changed, the magnification factor can be changed.
In one embodiment, the differential amplifier circuit further includes a gain selection unit including a relay SW1, and the source resistor R S Includes a first source resistor R S1 A second source resistor R S2 A third source resistance R S3 A fourth source resistor R S4 A fifth source resistor R S5 A sixth source resistor R S6 The first source electrode resistor R S1 A third source resistance R S3 A fifth source resistor R S5 Are sequentially connected in series, and the second source electrode resistor R S2 A fourth source resistor R S4 A sixth source resistor R S6 Are sequentially connected in series, and the second source electrode resistor R S2 Is connected with the second input pipe J 2 Source electrode S of 2 The first source electrode resistor R S1 Is connected with the first input pipe J 1 Source electrode S of 1 The fifth source electrode resistor R S5 A sixth source resistor R S6 Are all connected with the seventh resistor R 7 The common end C of the relay SW1 is connected with the second source electrode resistor R S2 A fourth source resistor R S4 A set terminal S via a sixth resistor R 6 A ground terminal and a reset terminal R connected to the first source resistor R S1 Third source resistance R S3 The differential amplifier having a low gain mode and a high gain mode.
Referring to fig. 2, if the common terminal C of the relay SW1 is connected to the set terminal S, the first source resistor R is connected to the common terminal C of the relay SW1 S1 A third source resistance R S3 A fifth source resistor R S5 Are sequentially connected in series, and the second source electrode resistor R S2 A fourth source resistor R S4 A sixth source resistor R S6 Connected in series in sequence, correspondingly, source resistance R s ＝R s1 +R s3 +R s5 (setting R) s1 ＝R s2 ，R s3 ＝R s4 ，R s5 ＝R s6 ) Adjusting the source resistance to make R s ＝R f At this time, the gain is 2. Referring to fig. 3, if the common terminal C of the relay SW1 is connected to the reset terminal R, the first source resistor R is connected to the common terminal C of the relay SW1 s1 And a second source resistance R s2 Is short-circuited at one end, and correspondingly, the source resistance R s ＝R s1 (setting R as described above) s1 ＝R s2 ) At this time, the gain is 1+R f /R s1 Greater than 2 (as previously described, R f ＝R s ＝R s1 +R s3 +R s5 Time equals 2). Therefore, the differential amplifier has a low gain mode and a high gain mode, and is selected by the gain selection unit, and if the common terminal and the set terminal of the relay in the gain selection unit are connected, the differential amplifier is in the low gain modeThen, it is in high gain mode. So that the low input noise and high input range performance can be satisfied at the same time.
Referring to fig. 4, in an embodiment, the differential amplifier circuit further includes a low-gain bias adjusting unit, and the low-gain bias adjusting unit includes a first adjustable potentiometer RP 1 Said first adjustable potentiometer RP 1 The two tail ends of the first adjustable potentiometer RP are respectively connected with a positive power supply VCC and a negative power supply VEE, and the first adjustable potentiometer RP 1 Via said sixth resistor R 6 And the set end S of the relay SW1 is connected. By means of said first adjustable potentiometer RP 1 Bias zeroing may be performed in a low gain mode.
Referring to fig. 1 and 4 in combination, in one embodiment, the differential amplifier circuit further includes a high-gain bias adjusting unit, and the high-gain bias adjusting unit includes a second adjustable potentiometer RP 2 Said second adjustable potentiometer RP 2 Respectively connected with positive and negative power supplies VCC, VEE, the second adjustable potentiometer RP 2 Via a first resistor R 1 Connecting the first input pipe J 1 Drain electrode D of 1 . By means of said second adjustable potentiometer RP 2 Bias zeroing may be performed in a high gain mode.
Referring to fig. 1 and 4 in combination, in one embodiment, the differential amplifier circuit further includes a high-gain common-mode rejection ratio (CMRR) adjusting unit, and the high-gain CMRR adjusting unit includes a third adjustable potentiometer RP 3 Said third adjustable potentiometer RP 3 Via a second resistor R 2 Connecting the first input pipe J 1 Source electrode S of 1 Said third adjustable potentiometer RP 3 The other end and the middle adjusting end of the connecting rod are grounded. The third adjustable potentiometer RP 3 And the feedback resistance R f Close to and slightly smaller than, adjust said third adjustable potentiometer RP 3 Said third adjustable potentiometer RP can be made 3 A second resistor R 2 And the feedback resistance R f Is equal, thereby being adjusted to the maximumGood common mode rejection ratio.
Referring to fig. 1 and 4 in combination, in an embodiment, the differential amplifier circuit further includes a low-gain common-mode rejection ratio adjusting unit, and the low-gain common-mode rejection ratio adjusting unit includes a fourth adjustable potentiometer RP 4 Said fourth adjustable potentiometer RP 4 Are respectively connected with the third source electrode resistor R S3 A fifth source resistor R S5 And the fourth source resistance R S4 A sixth source resistor R S6 Said fourth adjustable potentiometer RP, said fourth adjustable potentiometer RP 4 The middle adjusting end of the resistor is connected with the seventh resistor R 7 . Adjusting the fourth adjustable potentiometer RP 4 The common mode gain generated by the fact that the actual resistance values of the resistors in the circuit are not consistent and asymmetrical can be adjusted.
Finally, it should be noted that two working voltage terminals of the first amplifier OPA1 are respectively connected to the positive and negative power supplies VCC and VEE, and respectively pass through the first capacitor C 1 A second capacitor C 2 Grounding; two working voltage ends of the second amplifier OPA2 are respectively connected with positive and negative power supplies VCC and VEE and are respectively connected with the positive and negative power supplies VCC and VEE through a third capacitor C 3 A fourth capacitor C 4 And (4) grounding.
In one embodiment, the differential amplifier circuit has a high gain amplification factor of 50 times, a 3dB bandwidth of more than 1MHz, and a noise of less than 5nV/Hz at 50 times amplification 0.5 @1kHz, common mode rejection ratio is larger than or equal to 100dB @1kHz, and the requirement of the general preposed voltage amplification instrument is completely met.
According to the differential amplification circuit, the first input stage adopts an N-channel JFET as a topological structure of an input geminate transistor, the input impedance is extremely high, the input noise is extremely low, and the first input stage can be called a high-impedance differential input stage. The second input stage adopts a low-noise broadband operational amplifier to form a negative feedback amplification structure, amplifies input signals and has a large gain-bandwidth product, and the second input stage can be called as a low-noise amplification stage. The gain selection unit is formed by a relay and can be switched to a low gain mode or a high gain mode. The low-gain bias adjustment unit and the high-gain bias adjustment unit can perform zero adjustment in a low-gain mode and a high-gain mode, respectively. The low-gain common-mode rejection ratio adjusting unit and the high-gain common-mode rejection ratio adjusting unit can reduce common-mode gain in a low-gain mode and a high-gain mode respectively and improve the common-mode rejection ratio.
It is to be understood that the above description is intended to be illustrative, and not restrictive. Many embodiments and many applications other than the examples provided would be apparent to those of skill in the art upon reading the above description. The scope of the present teachings should, therefore, be determined not with reference to the above description, but should instead be determined with reference to the pending claims along with the full scope of equivalents to which such claims are entitled. The disclosures of all articles and references, including patent applications and publications, are hereby incorporated by reference for all purposes. The omission in the foregoing claims of any aspect of subject matter that is disclosed herein is not intended to forego the subject matter and should not be construed as an admission that the applicant does not consider such subject matter to be part of the disclosed subject matter.
Claims (10)
1. A differential amplification circuit, comprising: the first input stage comprises an input pair tube and a constant current source, wherein the input pair tube is an N-channel JFET, a grid electrode receives an input signal, a drain electrode is used as an output end of the first input stage, and the drain electrode is connected to a source electrode through the constant current source in a feedback mode.
2. The differential amplifier circuit according to claim 1, wherein the constant current source includes a first amplifier and a schottky diode, a non-inverting input terminal of the first amplifier is grounded via a fifth capacitor and is connected to a cathode of the schottky diode via a ninth resistor, the cathode of the schottky diode is further connected to a positive power supply via an eighth resistor, an anode of the schottky diode is grounded, inverting input terminals of the first amplifier are connected to drains of the pair of input transistors via a fourth resistor and a fifth resistor, respectively, and an output terminal of the first amplifier is connected to sources of the pair of input transistors via a seventh resistor.
3. The differential amplifier circuit as in claim 2, wherein the gates of said pair of input transistors are further connected to ground via an input resistor, the drains of said pair of input transistors are further connected to a positive power supply via a drain resistor, the sources of said pair of input transistors are further connected to said seventh resistor via a source resistor, said seventh resistor is further connected to a negative power supply via a tenth resistor.
4. The differential amplifier circuit as claimed in claim 3, further comprising a second amplifier stage, wherein said second amplifier stage comprises a second amplifier and a feedback resistor, wherein a positive input terminal and a negative input terminal of said second amplifier stage are connected to two drain electrodes of said pair of input transistors, said pair of input transistors comprises a first input transistor and a second input transistor, an output terminal of said second amplifier stage is connected to a source electrode of said second input transistor via said feedback resistor, and an output terminal of said second amplifier stage is an output terminal of said differential amplifier circuit.
5. The differential amplifier circuit according to claim 4, wherein the differential amplifier circuit further comprises a gain selection unit, the gain selection unit comprises a relay, the source resistors comprise a first source resistor, a second source resistor, a third source resistor, a fourth source resistor, a fifth source resistor and a sixth source resistor, the first source resistor, the third source resistor and the fifth source resistor are sequentially connected in series, the second source resistor, the fourth source resistor and the sixth source resistor are sequentially connected in series, a free end of the second source resistor is connected to the source of the second input tube, a free end of the first source resistor is connected to the source of the first input tube, free ends of the fifth source resistor and the sixth source resistor are connected to the seventh resistor, a common terminal of the relay is connected to a connection point of the second source resistor and the fourth source resistor, a set terminal is grounded via the sixth resistor, a reset terminal is connected to a connection point of the first source resistor and the third source resistor, and the differential amplifier has a low gain mode and a high gain mode.
6. The differential amplifier circuit as claimed in claim 5, wherein said differential amplifier circuit further comprises a low gain bias adjustment unit, said low gain bias adjustment unit comprises a first adjustable potentiometer, two ends of said first adjustable potentiometer are respectively connected to positive and negative power supplies, and a middle adjustment end of said first adjustable potentiometer is connected to a setting end of said relay via said sixth resistor.
7. The differential amplifier circuit as claimed in claim 6, wherein said differential amplifier circuit further comprises a high gain bias adjustment unit, said high gain bias adjustment unit comprises a second adjustable potentiometer, two ends of said second adjustable potentiometer are respectively connected to positive and negative power supplies, and a middle adjustment end of said second adjustable potentiometer is connected to the drain of said first input tube via a first resistor.
8. The differential amplifier circuit as claimed in claim 7, wherein said differential amplifier circuit further comprises a high-gain common-mode rejection ratio adjusting unit, said high-gain common-mode rejection ratio adjusting unit comprises a third adjustable potentiometer, one end of said third adjustable potentiometer is connected to the source of said first input tube via a second resistor, and the other end and the middle adjusting end of said third adjustable potentiometer are both grounded.
9. The differential amplifier circuit according to claim 8, further comprising a low-gain common-mode rejection ratio adjusting unit, wherein the low-gain common-mode rejection ratio adjusting unit includes a fourth adjustable potentiometer, two ends of the fourth adjustable potentiometer are respectively connected to a connection point of the third source resistor and the fifth source resistor and a connection point of the fourth source resistor and the sixth source resistor, and a middle adjusting terminal of the fourth adjustable potentiometer is connected to the seventh resistor.
10. The differential amplifier circuit as claimed in claim 9, wherein the two working voltage terminals of the first amplifier are connected to a positive power supply and a negative power supply respectively, and are grounded via a first capacitor and a second capacitor respectively; two working voltage ends of the second amplifier are respectively connected with a positive power supply and a negative power supply and are respectively grounded through a third capacitor and a fourth capacitor; the drain resistors comprise a zeroth drain resistor, a first drain resistor and a second drain resistor, and the first drain resistor and the second drain resistor are respectively connected with the drains of the first input tube and the second input tube and are connected with a positive power supply through the zeroth drain resistor.
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| CN202211185328.6A CN115603669B (en) | 2022-09-27 | 2022-09-27 | Differential amplifying circuit |
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| CN114710123A (en) * | 2022-04-19 | 2022-07-05 | 国仪量子(合肥)技术有限公司 | Amplifying circuit and signal detector |
| CN114866042A (en) * | 2022-07-07 | 2022-08-05 | 国仪量子(合肥)技术有限公司 | Signal amplifying circuit |
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2022
- 2022-09-27 CN CN202211185328.6A patent/CN115603669B/en active Active
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| US6323730B1 (en) * | 1999-04-30 | 2001-11-27 | Pcb Piezotronics, Inc. | High resolution zero input current charge sensitive preamplifier |
| US20050200411A1 (en) * | 2004-03-11 | 2005-09-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Differential amplifier without common mode feedback |
| CN203368404U (en) * | 2013-03-28 | 2013-12-25 | 中国矿业大学 | High-gain low noise amplifier |
| CN103248324A (en) * | 2013-04-23 | 2013-08-14 | 南京邮电大学 | High-linearity low-noise amplifier |
| US10084421B1 (en) * | 2017-07-31 | 2018-09-25 | Harman International Industries, Incorporated | Plural feedback loops instrumentation folded cascode amplifier |
| CN114710123A (en) * | 2022-04-19 | 2022-07-05 | 国仪量子(合肥)技术有限公司 | Amplifying circuit and signal detector |
| CN114866042A (en) * | 2022-07-07 | 2022-08-05 | 国仪量子(合肥)技术有限公司 | Signal amplifying circuit |
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