CN115549703A - Integrated CMOS power amplifier wide voltage transmitter and transceiver - Google Patents
Integrated CMOS power amplifier wide voltage transmitter and transceiver Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/02—Transmitters
- H04B1/04—Circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/30—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters
- H03F1/301—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters in MOSFET amplifiers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
- H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
- H03F3/193—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only with field-effect devices
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
- H03F3/211—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only using a combination of several amplifiers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
- H04B1/40—Circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/451—Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/02—Transmitters
- H04B1/04—Circuits
- H04B2001/0408—Circuits with power amplifiers
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Abstract
The invention provides an integrated CMOS power amplifier wide voltage transmitter, comprising: the transmitting module is used for transmitting signals and comprises a CMOS power amplifier; and the transmitter control module is electrically connected with the transmitting module and used for controlling the transmitting frequency and the transmitting power of the radio-frequency signal transmitted by the transmitting module according to a network protocol and processing a baseband signal. The transmitter can improve the integration level, reduce the module area and the number of module components and parts, and further reduce the cost. The invention also provides an integrated CMOS power amplifier wide voltage transceiver.
Description
Technical Field
The invention relates to the technical field of wireless communication, in particular to an integrated CMOS power amplifier wide voltage transmitter and transceiver.
Background
Power Amplifiers (PA) are mainly used in transmitters and transceivers, and are located at the final stage of the transmitting end for amplifying transmitted signals. The power amplifier mainly has indexes such as saturation power, efficiency, linearity and the like. Depending on the fabrication process, the transmitter and the transceiver are usually CMOS processes, while the power amplifier is usually made of GaAs or other compound processes, and the power amplifier is generally difficult to integrate with the transmitter or the transceiver on the same chip. The application of the integrated CMOS power amplifier in the field of Narrow-Band Internet of Things (NBIoT) is still blank at present. Fig. 1 is a schematic diagram of a narrow-band internet-of-things transmitter in the prior art, and referring to fig. 1, the conventional narrow-band internet-of-things transmitter comprises a power management module 1, a transmitter control module 2 and a transmitting module 3, a GaAs power amplifier 4 chip is separately arranged from the transmitter, and the GaAs power amplifier 4 is connected with the transmitting module 3 through a power amplifier input matching module 5.
Therefore, there is a need to provide a new integrated CMOS power amplifier wide voltage transmitter and an integrated CMOS power amplifier wide voltage transceiver to solve the above-mentioned problems in the prior art.
Disclosure of Invention
The invention aims to provide an integrated CMOS power amplifier wide voltage transmitter and an integrated CMOS power amplifier wide voltage transceiver, which can improve the integration level and reduce the module area and the number of module components, thereby reducing the cost.
To achieve the above object, the integrated CMOS power amplifier wide voltage transmitter of the present invention comprises:
a transmitting module for transmitting a signal, the transmitting module comprising a CMOS power amplifier;
and the transmitter control module is electrically connected with the transmitting module and used for controlling the transmitting frequency and the transmitting power of the radio-frequency signal transmitted by the transmitting module according to a network protocol and processing a baseband signal.
The transmitter of the invention has the beneficial effects that: the CMOS power amplifier is integrated, the integration level can be improved, the module area is reduced, an extra power amplifier chip is not needed, the input matching of the power amplifier is not needed, the number of module components can be reduced, and the cost is reduced.
Optionally, the CMOS power amplifier includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor, where a gate of the first NMOS transistor is communicated with a gate of the second NMOS transistor, a gate of the third NMOS transistor is communicated with a gate of the fourth NMOS transistor, a source of the first NMOS transistor, a source of the second NMOS transistor, and a source of the third NMOS transistor are connected with a source of the fourth NMOS transistor and grounded, a drain of the first NMOS transistor and a drain of the third NMOS transistor are both connected with a source of the fifth NMOS transistor, a drain of the second NMOS transistor and a drain of the fourth NMOS transistor are both communicated with a source of the sixth NMOS transistor, and a gate of the fifth NMOS transistor and a gate of the sixth NMOS transistor are connected with a bias voltage. The beneficial effects are that: the generation of non-linearity in the CMOS power amplifier can be reduced and variations in the phase difference between the output and input signals can be reduced, enabling the transmitter to accommodate a larger voltage range.
Optionally, the CMOS power amplifier further includes a first resistor and a second resistor, the source of the second NMOS transistor is connected to one end of the first resistor, the source of the third NMOS transistor is connected to one end of the second resistor, and the source of the first NMOS transistor, the other end of the first resistor, and the other end of the second resistor are connected to the source of the fourth NMOS transistor and grounded. The beneficial effects are that: current consumption can be reduced without affecting the overall efficiency of the CMOS power amplifier.
Optionally, the transmitting module further includes a digital-to-analog converter, a low-pass filter, and a mixer, where the digital-to-analog converter, the low-pass filter, the mixer, and the CMOS power amplifier are sequentially connected and transmit a radio frequency signal, and the CMOS power amplifier is configured to amplify the radio frequency signal.
Optionally, the CMOS power amplifier is connected to an antenna through a balun, and an impedance turns ratio of a radio frequency input end and a radio frequency output end of the balun is 1. The beneficial effects are that: the load impedance of the CMOS power amplifier can be reduced by using a high turns ratio balun, so that enough power can be transmitted at low voltage.
Optionally, the system further comprises a power management module, wherein the power management module is used for supplying power to the transmitting module and the transmitter control module.
Optionally, the power management module comprises a DC-DC converter or an LDO circuit, and the CMOS power amplifier is connected to a power supply through the DC-DC converter or the LDO circuit. The beneficial effects are that: the transmitter can be adapted to a larger voltage range.
Optionally, the power management module further includes a DC-DC converter and an LDO circuit, and the CMOS power amplifier is connected to a power supply through the LDO circuit and the DC-DC converter in sequence. The beneficial effects are that: the power supply ripple can be suppressed, and output stray can be reduced.
Optionally, the transmitter is applied to the internet of things, a narrowband private network or a satellite internet.
The invention also provides an integrated CMOS power amplifier wide voltage transceiver, which is characterized by comprising a receiver and the transmitter. The transceiver has the beneficial effects that: the transceiver integrates the CMOS power amplifier, can improve the integration level, reduce the module area, does not need an additional power amplifier chip, does not need the input matching of the power amplifier, can reduce the number of module components and parts, and reduces the cost.
Drawings
Fig. 1 is a schematic diagram of a narrowband internet of things transmitter in the prior art;
FIG. 2 is a schematic diagram of a transmitter in some embodiments;
FIG. 3 is a schematic diagram of a transmitter in further embodiments;
FIG. 4 is a schematic illustration of the turns of a balun in some embodiments;
FIG. 5 is a side view of a stacked configuration of a balun in some embodiments of the present invention;
FIG. 6 is a top view of the m3 metal layer;
FIG. 7 is a top view of the m2 metal layer;
FIG. 8 is a top view of the m1 metal layer;
FIG. 9 is a top view of the V1 layer;
fig. 10 is a circuit schematic of a high frequency CMOS power amplifier in some embodiments.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention. Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. As used herein, the word "comprising" and similar words are intended to mean that the element or item preceding the word comprises the element or item listed after the word and its equivalent, but not the exclusion of other elements or items.
Fig. 2 is a schematic diagram of a transmitter in some embodiments. Referring to fig. 2, the transmitter includes:
a transmitting module 3, configured to transmit a signal, where the transmitting module includes a CMOS power amplifier 31;
the transmitter control module 2 is electrically connected with the transmitting module 3, and is configured to control the transmitting frequency and the transmitting power of the radio frequency signal transmitted by the transmitting module 3 according to a protocol of the narrowband internet of things and process a baseband signal.
The transmitter integrates the CMOS power amplifier, can improve the integration level, reduce the area of a module, does not need an additional power amplifier chip, does not need the input matching of the power amplifier, can reduce the number of module components and lowers the cost.
In some embodiments, the transmitter is applied to the internet of things, narrowband private networks, or satellite internet.
Referring to fig. 2, the transmitting module 3 further includes a digital-to-analog converter 34, a low-pass filter 33, and a mixer 32, where the digital-to-analog converter 34, the low-pass filter 33, the mixer 32, and the CMOS power amplifier 31 are sequentially connected to transmit a radio frequency signal, and the CMOS power amplifier 31 is configured to amplify the radio frequency signal.
In some embodiments, the CMOS power amplifier 31 includes a high frequency CMOS power amplifier 311 and a low frequency CMOS power amplifier 312, the mixer 32 includes a first mixer 321 and a second mixer 322, the low pass filter 33 includes a first low pass filter 331 and a second low pass filter 332, the digital-to-analog converter 34 includes a first digital-to-analog converter 341 and a second digital-to-analog converter 342, the first digital-to-analog converter 341, the first low pass filter 331, the first mixer 321, and the high frequency CMOS power amplifier 311 are sequentially connected to transmit a high frequency rf signal, and the second digital-to-analog converter 342, the second low pass filter 332, the second mixer 322, and the low frequency CMOS power amplifier 312 are sequentially connected to transmit a low frequency rf signal.
Fig. 3 is a schematic diagram of a transmitter in further embodiments. Referring to fig. 3, the high-frequency CMOS power amplifier 311 is connected to the antenna 7 through a balun 6, and an impedance turns ratio between a radio-frequency input end and a radio-frequency output end of the balun 6 is 1. For different voltages and output powers, the value of N has a corresponding optimal value, when the voltage is 1.8v, the saturation power is more than or equal to 28dbm, and N is preferably 3. If the voltage is lower or the power is higher, the value of N is larger. The load impedance of the CMOS power amplifier can be reduced by using the balun with a high turn ratio, so that enough power can be transmitted at low voltage.
The theoretical value N' and saturation power P of the balun sat The relationship between (unit: W) and VDD (unit: V) is
The PA linearity and PA efficiency are higher.
N is equivalent to N' without considering parasitic inductance and capacitance of traces or package in practical applications.
In some embodiments, when the saturation power is 28dbm and the voltage value is 1.8V, the linearity and efficiency of the PA are high when N is 2-4; when the saturation power is 28dbm and the voltage value is 2.5V, the linearity and efficiency of the PA are high when N is 1.5-2.5; when the saturation power is 28dbm and the voltage is 3.3V, the linearity and efficiency of the PA are high when N is 1-2.
Fig. 4 is a schematic diagram of the turns of a balun in some embodiments. Referring to fig. 3 and 4, the rf input includes a first input port 61 and a second input port 62, and the rf output includes a first output port 63 and a second output port 64. The radio frequency input end adopts a mode of 3-loop impedance parallel connection, the radio frequency output end is 3-loop impedance, the impedance turn ratio of the radio frequency input end and the radio frequency output end of the balun 6 is 1. Fig. 5 is a side view of a stacked structure of a balun according to some embodiments of the present invention, referring to fig. 5, the balun includes 3 metal layers and 2 VIA holes, the 3 metal layers are an m1 metal layer, an m2 metal layer, and an m3 metal layer, respectively, and the 2 VIA holes are a V1 layer and a V2 layer, respectively, wherein the V2 layer is empty. Fig. 6 is a top view of the m3 metal layer in fig. 5, fig. 7 is a top view of the m2 metal layer in fig. 5, fig. 8 is a top view of the m1 metal layer in fig. 5, and fig. 9 is a top view of the V1 layer in fig. 5.
In some embodiments, the impedance turns ratio between the rf input and the rf output of the balun 6 is 1.
In some embodiments, the balun uses a chip of an Integrated Passive Device (IPD) process, and since the IPD process has a larger substrate impedance and a lower cost per unit area compared to a CMOS process, and is very suitable for integrating Passive devices such as inductors, capacitors, and the like, the operation efficiency of the balun can be improved by using the IPD process.
Referring to fig. 2 and 3, the transmitter further includes a power management module 1, where the power management module 1 is configured to supply power to the transmitting module 3 and the transmitter control module 2.
Referring to fig. 3, the transmitter control module 2 includes a phase-locked loop 21, the phase-locked loop 21 is configured to output a frequency signal to the transmitting module 3 to control a transmitting frequency, the phase-locked loop 21 includes a voltage-controlled oscillator 211, and the voltage-controlled oscillator 211 includes a second inductor (not shown), and a center of the second inductor is disposed in a horizontal direction with a center of the balun 6. In some embodiments, the center of the second inductor is disposed in the same vertical direction as the center of the balun 6. The problem of pulling (pulling) of the phase-locked loop by the CMOS power amplifier can be solved by arranging the center of the second inductor and the center of the balun 6 in the same horizontal direction or the same vertical direction.
In some embodiments, the distance between the center of the second inductance and the center of the balun 6 is greater than or equal to 1mm. The distance between the center of the second inductor and the center of the balun 6 is far, so that the problem of phase-locked loop pulling (pulling) of the CMOS power amplifier can be solved.
In some embodiments, the power management module comprises a DC-DC converter or the LDO circuit, and the CMOS power amplifier is connected to a power supply through the DC-DC converter or the LDO circuit. The transmitter can be adapted to a larger voltage range.
Referring to fig. 3, the power management module 1 includes a DC-DC converter 11, and the high frequency CMOS power amplifier 311 is connected to a VBAT pin 13 and an external power source through the DC-DC converter 11.
In some embodiments, the power management module further includes an LDO circuit, and the CMOS power amplifier is connected to the power supply via the LDO circuit and the DC-DC converter in sequence, so that power supply ripple can be suppressed and output spurious can be reduced.
Referring to fig. 3, the power management module 1 includes a DC-DC converter 11 and an LDO circuit 12, and the high frequency CMOS power amplifier 311 is connected to a power supply through the LDO circuit 12 and the DC-DC converter 11 in turn.
Referring to fig. 3, the power supply path of the transmitter includes: the power is connected through a VBAT pin 13, passes through the DC-DC converter 11, a first inductor 14 and the LDO circuit 12, and then supplies power to the high frequency CMOS power amplifier 311 and the first mixer 321, where one end of the first inductor 14 is connected to the DC-DC converter 11, the other end is connected to the LDO circuit 12 and a capacitor 15, respectively, and the capacitor 15 is grounded. The power supply path of the transmitter further comprises: the power supply is connected through the VBAT pin 13, passes through the DC-DC converter 11, the first inductor 14 and the TP port 65, and then splits the current into two paths through the first input port 61 and the second input port 62 of the balun 6 to be transmitted to the high-frequency CMOS power amplifier 311.
In some embodiments, the CMOS power amplifier includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor, a gate of the first NMOS transistor is communicated with a gate of the second NMOS transistor, a gate of the third NMOS transistor is communicated with a gate of the fourth NMOS transistor, a source of the first NMOS transistor, a source of the second NMOS transistor, and a source of the third NMOS transistor are connected with a source of the fourth NMOS transistor and grounded, a drain of the first NMOS transistor and a drain of the third NMOS transistor are both connected with a source of the fifth NMOS transistor, a drain of the second NMOS transistor and a drain of the fourth NMOS transistor are both communicated with a source of the sixth NMOS transistor, and a gate of the fifth NMOS transistor and a gate of the sixth NMOS transistor are connected with a bias voltage.
The second NMOS tube and the third NMOS tube adopt a cross pair mode, the first NMOS tube and the second NMOS tube, the third NMOS tube and the fourth NMOS tube are complementary pairs, the first NMOS tube, the fourth NMOS tube, the fifth NMOS tube and the sixth NMOS tube form a differential structure, the connection mode is called a cross complementary differential structure, and the cross complementary differential structure enables the first NMOS tube and the second NMOS tube to generate parasitic capacitance in opposite directions and enables the third NMOS tube and the fourth NMOS tube to generate parasitic capacitance in opposite directions. Because the NMOS tube can generate parasitic capacitance, and the parasitic capacitance generated by the first NMOS tube, the second NMOS tube, the third NMOS tube, the fourth NMOS tube, the fifth NMOS tube and the sixth NMOS tube is represented as the equivalent capacitance of the CMOS power amplifier, when the input power changes greatly, the change of the equivalent capacitance of the CMOS power amplifier is larger, and the nonlinearity of the CMOS power amplifier is more obvious. When the transmitter is narrowband thing networking transmitter, because narrowband thing networking transmitter is with power supply, has more low pressure application scene, consequently requires the transmitter in low pressure also normally work, in order to prolong narrowband thing networking module battery life, requires narrowband thing networking in low pressure also normally work, is less than 2V usually. Because the input equivalent capacitance of the CMOS power amplifier is generally larger along with the change of input power under the low-voltage condition than under the high-voltage condition, the cross complementary differential structure can reduce the generation of nonlinearity of the narrow-band internet-of-things transmitter under the low-voltage condition, so that the narrow-band internet-of-things transmitter can adapt to a larger voltage range. In addition, the narrow-band Internet of things protocol requires 23dBm average power, the saturation power corresponding to the power amplifier exceeds 28dBm, and the power required by the narrow-band Internet of things protocol is larger through multi-stage amplification.
In some embodiments, the CMOS power amplifier further includes a first resistor and a second resistor, the source of the second NMOS transistor is connected to one end of the first resistor, the source of the third NMOS transistor is connected to one end of the second resistor, and the source of the first NMOS transistor, the other end of the first resistor, and the other end of the second resistor are connected to the source of the fourth NMOS transistor and grounded. The second NMOS tube and the third NMOS tube which form the cross pair are respectively connected with a resistor, so that the current consumption can be reduced, and the overall efficiency of the CMOS power amplifier is not influenced.
Fig. 10 is a circuit schematic of a high frequency CMOS power amplifier in some embodiments. Referring to fig. 10, the high-frequency CMOS power amplifier 311 includes a first NMOS transistor 3111, a second NMOS transistor 3112, a third NMOS transistor 3113, a fourth NMOS transistor 3114, a fifth NMOS transistor 3115 and a sixth NMOS transistor 3116, a gate of the first NMOS transistor 3111 is communicated with a gate of the second NMOS transistor 3112, a gate of the third NMOS transistor 3113 is communicated with a gate of the fourth NMOS transistor 3114, a source of the first NMOS transistor 3111, a source of the second NMOS transistor 3112 and a source of the third NMOS transistor 3113 are connected to a source of the fourth NMOS transistor 3114 and grounded, a drain of the first NMOS transistor 3111 and a drain of the third NMOS transistor 3113 are both connected to a source of the fifth NMOS transistor 3115, a drain of the second NMOS transistor 3112 and a drain of the fourth NMOS transistor 3114 are both communicated with a source of the sixth NMOS transistor 3116, and a gate of the fifth NMOS transistor 3115 and a drain of the sixth NMOS transistor 3116 are connected to a bias voltage (not shown). First NMOS pipe 3111 is connected with first signal entry 31111, fourth NMOS pipe 3114 is connected with second signal entry 31141, fifth NMOS pipe 3115 is connected with first signal export 31151, sixth NMOS pipe 3116 is connected with second signal export 31161.
Referring to fig. 10, the high frequency CMOS power amplifier 311 further includes a first resistor 3117 and a second resistor 3118, a source of the second NMOS transistor 3112 is connected to one end of the first resistor 3117, a source of the third NMOS transistor 3113 is connected to one end of the second resistor 3118, and a source of the first NMOS transistor 3111, the other end of the first resistor 3117, and the other end of the second resistor 3118 are connected to the source of the fourth NMOS transistor 3114 and grounded.
The following is a detailed description of the principle by which the CMOS power amplifier of the present invention can reduce the generation of non-linearity. In the prior art differential structure, the NMOS transistor connected to the second signal input port has g, s, and d ports, and there is a parasitic capacitance between each port, for example, the parasitic capacitance between g and s is Cgs, and the parasitic capacitance between g and d is Cgd. Meanwhile, the NMOS has a signal gain, denoted as a (generally negative). At this time, the equivalent input capacitance Crfin _ p of the second signal inlet may be approximately Crfin _ p ≈ Cgs-a × Cgd. As the output signal amplitude increases, cgs and Cgd change, the gain a also changes, which results in a change of the PA equivalent input capacitance, and in addition, AMAM and AMPM are strongly correlated with this equivalent input capacitance, AMAM distortion refers to distortion in the output signal and input signal amplitude, such as truncation or clipping of the output voltage signal when the input signal swing goes below a threshold voltage or above a saturation voltage, that is, AMAM distortion. AMPM distortion refers to variations in the amplitude of the nonlinear PA input signal, resulting in variations in the phase difference between the output and input signals. This can cause the AMAM, AMPM curves of the PA to deviate from the ideal PA curves. To improve PA linearity, the actual AMAM, AMPM curve needs to be approximated to the ideal curve, and the variation of the PA equivalent input capacitance with other factors, such as input power, process variation, etc., needs to be reduced.
Referring to fig. 10, in the CMOS power amplifier of the present invention, the d port of the fourth NMOS transistor 3114 is a negative swing, and the d port of the third NMOS transistor 3113 is a positive swing. At this time, the equivalent input capacitance Crfin _ p of the second signal inlet 31141 can be roughly expressed as Crfin _ p ≈ Cgs4-A4 × Cgd4+ Cgs3+ A3 × Cgd3 ≈ 2 × Cgs, and A4 × Cgd4 and A3 × Cgd3 are designed to be cancelled as much as possible. Although Cgs and Cgd vary with the increase of the output signal amplitude, the output capacitance is almost less dependent on the gains a and Cgd compared to the conventional differential structure. Even though a and Cgd may vary with input/output power, the variation of the equivalent input capacitance of the second signal inlet 31141 and the first signal inlet 31111 may be smaller.
The AMPM distortion produced by the CMOS power amplifier fluctuates little with the process, since in the conventional structure, crfin _ p ≈ Cgs-a × Cgd, and these 3 variables Cgs, a, cgd all vary with the process. In the CMOS power amplifier of the invention, crfin _ p is approximately equal to Cgs4-A4 Cgd4+ Cgs3+ A3 Cgd3 is approximately equal to 2 Cgs, and only one variable of Cgs can change along with the process change. Therefore, the AMPM distortion generated by the CMOS power amplifier is small along with the process fluctuation.
The invention also provides a transceiver, which comprises a receiver and the transmitter.
The transceiver integrates the CMOS power amplifier, can improve the integration level, reduce the module area, does not need an additional power amplifier chip, does not need the input matching of the power amplifier, can reduce the number of module components and reduce the cost.
Although the embodiments of the present invention have been described in detail hereinabove, it is apparent to those skilled in the art that various modifications and variations can be made to these embodiments. However, it is to be understood that such modifications and variations fall within the scope and spirit of the present invention as set forth in the following claims. Moreover, the invention as described herein is capable of other embodiments and of being practiced or of being carried out in various ways.
Claims (10)
1. An integrated CMOS power amplifier wide voltage transmitter, comprising:
a transmitting module for transmitting a signal, the transmitting module comprising a CMOS power amplifier;
and the transmitter control module is electrically connected with the transmitting module and used for controlling the transmitting frequency and the transmitting power of the radio-frequency signal transmitted by the transmitting module according to a network protocol and processing a baseband signal.
2. The transmitter of claim 1, wherein the CMOS power amplifier comprises a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor, a gate of the first NMOS transistor is communicated with a gate of the second NMOS transistor, a gate of the third NMOS transistor is communicated with a gate of the fourth NMOS transistor, a source of the first NMOS transistor, a source of the second NMOS transistor, and a source of the third NMOS transistor are connected with a source of the fourth NMOS transistor and grounded, a drain of the first NMOS transistor and a drain of the third NMOS transistor are both connected with a source of the fifth NMOS transistor, a drain of the second NMOS transistor and a drain of the fourth NMOS transistor are both communicated with a source of the sixth NMOS transistor, and a gate of the fifth NMOS transistor and a gate of the sixth NMOS transistor are connected with a bias voltage.
3. The transmitter of claim 2, wherein the CMOS power amplifier further comprises a first resistor and a second resistor, wherein the source of the second NMOS transistor is connected to one end of the first resistor, the source of the third NMOS transistor is connected to one end of the second resistor, and the source of the first NMOS transistor, the other end of the first resistor, and the other end of the second resistor are connected to the source of the fourth NMOS transistor and are grounded.
4. The transmitter of claim 1, wherein the transmitting module further comprises a digital-to-analog converter, a low-pass filter, and a mixer, the digital-to-analog converter, the low-pass filter, the mixer, and the CMOS power amplifier are sequentially connected and transmit a radio frequency signal, and the CMOS power amplifier is configured to amplify the radio frequency signal.
5. The transmitter according to claim 1, wherein the CMOS power amplifier is connected to an antenna through a balun having an impedance turns ratio of 1 n at a radio frequency input and 3 at a radio frequency output.
6. The transmitter of claim 1, further comprising a power management module configured to provide power to the transmit module and the transmitter control module.
7. The transmitter of claim 6, wherein the power management module comprises a DC-DC converter or the LDO circuit, and wherein the CMOS power amplifier is coupled to a power source through the DC-DC converter or the LDO circuit.
8. The transmitter of claim 6, wherein the power management module further comprises a DC-DC converter and an LDO circuit, and wherein the CMOS power amplifier is connected to a power supply via the LDO circuit and the DC-DC converter in sequence.
9. The transmitter of claim 1, wherein the transmitter is applied to the internet of things, narrowband private networks, or satellite internet.
10. An integrated CMOS power amplifier wide voltage transceiver, comprising a receiver and a transmitter according to any of claims 1-9.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211227854.4A CN115549703B (en) | 2022-10-09 | 2022-10-09 | Transmitter and transceiver integrated with CMOS power amplifier |
| PCT/CN2023/097733 WO2024077973A1 (en) | 2022-10-09 | 2023-06-01 | Cmos power amplifier integrated wide-voltage transmitter and transceiver |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN202211227854.4A CN115549703B (en) | 2022-10-09 | 2022-10-09 | Transmitter and transceiver integrated with CMOS power amplifier |
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| CN115549703A true CN115549703A (en) | 2022-12-30 |
| CN115549703B CN115549703B (en) | 2024-06-18 |
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| CN202211227854.4A Active CN115549703B (en) | 2022-10-09 | 2022-10-09 | Transmitter and transceiver integrated with CMOS power amplifier |
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| WO (1) | WO2024077973A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2024077973A1 (en) * | 2022-10-09 | 2024-04-18 | 芯翼信息科技(上海)有限公司 | Cmos power amplifier integrated wide-voltage transmitter and transceiver |
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| CN101944924A (en) * | 2010-09-30 | 2011-01-12 | 东南大学 | Broadband MIMO radio frequency transceiving system for next-generation wireless communication network |
| CN107204785A (en) * | 2017-04-23 | 2017-09-26 | 复旦大学 | A kind of digital emitter of configurable low-power consumption |
| CN111965605A (en) * | 2020-02-28 | 2020-11-20 | 加特兰微电子科技(上海)有限公司 | Frequency modulated continuous wave signal transmitting device, method of transmitting frequency modulated continuous wave signal, signal transmitting/receiving device, electronic device, and apparatus |
| CN112702029A (en) * | 2021-03-25 | 2021-04-23 | 成都知融科技股份有限公司 | CMOS power amplifier chip with on-chip integrated detection function |
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| CN1148873C (en) * | 1998-07-24 | 2004-05-05 | 环球通讯科技半导体公司 | Single chip CMOS transmitter/receiver and VCO-mixer structure |
| US7301396B1 (en) * | 2004-12-16 | 2007-11-27 | Anadigics, Inc. | System and method for distortion cancellation in amplifiers |
| CN103516371B (en) * | 2013-09-18 | 2015-10-21 | 清华大学 | Configurable transmitting set |
| CN103762948B (en) * | 2013-12-24 | 2016-09-28 | 芯原微电子(上海)有限公司 | A kind of CMOS radio-frequency power amplifier being integrated in SOC(system on a chip) |
| CN115549703B (en) * | 2022-10-09 | 2024-06-18 | 芯翼信息科技(上海)有限公司 | Transmitter and transceiver integrated with CMOS power amplifier |
| CN115549608A (en) * | 2022-10-09 | 2022-12-30 | 芯翼信息科技(上海)有限公司 | Integrated high linearity CMOS power amplifier |
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2022
- 2022-10-09 CN CN202211227854.4A patent/CN115549703B/en active Active
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101944924A (en) * | 2010-09-30 | 2011-01-12 | 东南大学 | Broadband MIMO radio frequency transceiving system for next-generation wireless communication network |
| CN107204785A (en) * | 2017-04-23 | 2017-09-26 | 复旦大学 | A kind of digital emitter of configurable low-power consumption |
| CN111965605A (en) * | 2020-02-28 | 2020-11-20 | 加特兰微电子科技(上海)有限公司 | Frequency modulated continuous wave signal transmitting device, method of transmitting frequency modulated continuous wave signal, signal transmitting/receiving device, electronic device, and apparatus |
| CN112702029A (en) * | 2021-03-25 | 2021-04-23 | 成都知融科技股份有限公司 | CMOS power amplifier chip with on-chip integrated detection function |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2024077973A1 (en) * | 2022-10-09 | 2024-04-18 | 芯翼信息科技(上海)有限公司 | Cmos power amplifier integrated wide-voltage transmitter and transceiver |
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| Publication number | Publication date |
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| CN115549703B (en) | 2024-06-18 |
| WO2024077973A1 (en) | 2024-04-18 |
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