CN1148873C - Single chip CMOS transmitter/receiver and VCO-mixer structure - Google Patents

Abstract

A single chip RF communication system and method and a VCO-mixer structure are provided. The RF communication system in accordance with the present invention includes a transmitter, a receiver, an antenna for receiving transmitting RF signals, a PLL for generating multi-phase clock signals having a frequency different from a carrier frequency in response to the multi-phase clock signals and a reference signal having the carrier frequency, a demodulation-mixing unit for mixing the received RF signals with the multi-phase clock signals having the frequency different from the carrier frequency to output the RF signals having a frequency reduced by the carrier frequency and an A/D converting unit for converting the RF signals from the mixing unit into digital signals. The VCO in accordance with the present invention includes a plurality of differential delay cells, and the mixer includes a differential amplifying circuit and a combining circuit. The differential amplifying circuit of the multi-phase mixer includes two load resistors coupled to two differential amplifiers, respectively. The combining circuit includes bias transistors, first and second combining units coupled to the bias transistors, respectively, and a current source coupled to the first and second combining units. The first and second combining units include a first and second plurality of transistor units, respectively. Preferably, each of the plurality of transistor units includes a plurality of serially connected transistors, wherein the serially connected transistors are coupled in parallel with the serially connected transistors of the plurality of transistor units.

Description

The control method of communication system, single-chip RF communication system and RF communication system

Invention field

The invention relates to a communication system, clearer and more definite, be about complementary metal oxide semiconductor radio frequency (RF) communication system.The present invention is also about a voltage controlled oscillator (VCO) and blender, and clearer and more definite, is about a heterogeneous VCO and a blender.

The background of correlation technique

At present, a RF communication system has the multiple communications applications that comprises PCS communication and IMT system.Therefore, pursue integrated cost, size and the power consumption of reducing of the semi-conductive chip of a complementary metal oxide of this system.

Usually, this RF communication system is made up of RF front end square and baseband digital signal processing (DSP) square.At present, this base band DSP square can be realized with low-cost and lower powered complementary metal oxide semiconductor technology.Yet this RF front end square can not realize that because be subject to speed and noise characteristic, these features are to be lower than present employed RF communication system speed and noise requirements by the complementary metal oxide semiconductor technology.

For example, this pcs handset system is with the frequencies operations above 2.0GHz, and still present complementary metal oxide semiconductor technology reliability is reaching about 1.0GHz operation only from the viewpoint of speed and noise.Therefore, this RF front end square can use diode or two complementary metal oxide semiconductor technology to realize that it has than complementary metal oxide semiconductor technology better speed and noise characteristic are arranged, but more expensive and consume more power.

At present, the two dissimilar RF structures that are called " directly conversion " and " doubly conversion (double conversion) " are used for complementary metal oxide semiconductor RF communication system.Two structures have the strengths and weaknesses of implementing with the complementary metal oxide semiconductor.

Fig. 1 is that demonstration one correlation technique is directly changed complementary metal oxide semiconductor RF communication system 100, and it comprises an antenna 105, a RF filter 110, a low noise amplifier (LNA) 120, one first blender 140, one second blender 145, a phase-locked loop (PLL) 130, one first low pass filter (LPF) 150, one the 2nd LPF155, one first analog/digital (A/D) transducer 160, one second analog/digital converter 165, one the 3rd blender 160 and a power amplifier 170.

This antenna 105 receives the RF signal, and the RF signal that this is chosen then can be in 110 filtering of RF filter.The RF signal of this filtering is to amplify in LNA 120 gain, and this RF signal by LNA 120 is to multiply each other and directly be demodulated to baseband signal by 90 degree phase differences on first and second blender 140,145.This PLL 130 is to use a voltage-controlled oscillator (VCO) to produce clock signal, I signal and the Q signal of two types ideally.Except phase difference, this I clock is identical with the Q clock signal.I signal has 90 degree phase differences with Q signal ideally.Promptly be that Q signal and I signal have the phase shift of 90 degree.Two groups of signal I, Q are the ability that is used for increasing the RF system ideally, with identification or keep the data of reception, and no matter noise and interference.Two type signals that transmission has an out of phase can reduce the possibility of data degradation or variation.The frequency, demodulation frequency fo of Fig. 1 equals modulating frequency fo.

The frequency of this demodulated base band signal is that initial frequency deducts frequency f _o, with by this first and second LPF 150,155, and on this first and second analog/digital converter 160,165, become each required signal of analog/digital conversion at last.This digital signal can be transferred to the base band discrete-time signal then and handle (PSP) square (not demonstrating in the drawings).Channel selecting is by changing the frequency f on phase-locked loop (PLL) 130 _oCarry out.

A possible cause of about 1GHz restriction is the structure at VCO and the blender of PLL 130 on complementary metal oxide semiconductor technology confidence level.Fig. 2 is the circuit diagram that shows a background voltage control generator one blender, and wherein this VCO 10 comprises 4 differential delay unit 12,14,16 and 18, and has the structure of loop-like oscillator.These 4 delay cells the 12,14,16, the 18th, series connection, and clocking LO+ and reverse clock signal LO one, each clock signal has a frequency f _oVCO 10 control circuits that produce a frequency control signal comprise a phase-frequency detector 4, frequency control signal are outputed to a charge pump (pump) 6 and a loop filter 8 of this each delay cell 12,14,16,18.This phase-frequency detector 4 receives respectively the reference clock signal f from a reference clock divider circuit 2 _RefWith a VCO clock signal f from a VCO clock divider circuit 3 _VCOThe frequency f of this clock signal LO+ and LO- _oBe with M/K (f _Ref)=f _oExpression.Therefore, this frequency f _oBe based on this reference clock signal f _RefWith divider circuit 2,3.

For example, the blender 20 of a Gilbert-multiplier is with this input signal, and for example RF signal RF+ and RF-multiply by clock signal LO+ and LO-.This blender 20 comprises the two load resistance R1, the R2 that are coupled to source voltage VDD, 8 N type metal-oxide semiconductor transistors (NMOS) 21-28, an and current source I _S1The gate pole of this nmos pass transistor 21,22 is coupled to and receives this clock signal LO+, and gate pole 23,24 couplings of nmos pass transistor receive reverse clock signal LO-.The gate pole of this nmos pass transistor 25,26 receives bias voltage V altogether _BiasThe gate pole of this nmos pass transistor 27,28 receives RF signal RF+, RF-respectively.Therefore, have only when this transistor 25,27 or transistor 26,28 to be transformed into simultaneously in " ON " state, this clock signal LO+, LO-just can multiply by this RF signal RF+, RF-.The amount that this output signal OUT+ of blender 20, OUT-frequency are lower than original frequency is the frequency f of this clock signal LO+, LO- _o

Though a frequency range and a low phase noise need be in various application widely, this VCO- mixer structure 10,20 can only be supported the about 1GHz frequency that nearly has reliability phase noise and frequency range.The performance of this VCO- mixer structure 10,20 can worsen because of phase noise and frequency range, and when in this clock signal LO+, LO-frequency from VCO increase, can't accept.Therefore, when the frequency f of this clock signal LO+, LO- _oSurpass in about 1GHz, this VCO10 and blender 20 can not be realized.

As mentioned above, the direct conversion RF system 100 of correlation technique has the integrated advantage of complementary metal oxide semiconductor RF, because it is simpler.In the directly conversion RF of correlation technique system, only need single PLL, and high-Q filter is unwanted.Yet the direct transformational structure of this correlation technique has the integrated difficulty of the single-chip of making or impossible shortcoming.

As shown in Figure 3A, from clock signal cos ω such as the local oscillator (LO) of VCO _LOT can leak to blender input or antenna, and wherein radioactive ray can take place, because this local oscillator (LO) is the frequency identical with the RF carrier wave.Unwanted transmit clock signal Δ (t) cos ω _LOT can reflect near object, and " is received again " by blender.This low pass filter can be exported a signal M (t)+Δ (t) because leak clock signal.Shown in Fig. 3 B, oneself's mixing meeting of local oscillator causes the problem such as time variation or " pacing up and down " direct current biasing in the output of this blender.

Fig. 3 B changes and direct current biasing the description time." A " is illustrated in the signal before the blender, and the signal after " B " expression blender.Time changes direct current biasing clearly can reduce the receiver part together with intrinsic circuit bias dynamic range.In addition, directly changing the RF system needs a high-frequency of channel selecting, low phase noise PLL, and it is not easy to use an integrated complementary metal oxide semi-conductor electricity voltage-controlled oscillator (VCO) to reach, and discusses in the above for the reason to small part.

Fig. 4 is according to considering that all potential passages and transistorized times of transformational structure of frequency show the calcspar of the RF communication system 300 of a correlation technique.This RF communication system 300 comprises an antenna 305, a RF filter 310, a LNA320, one first blender 340, one second blender 345, reaches one the one LPF350, one the 2nd LPF355, second level blender 370-373, a first adder 374, reaches a second adder 375.This RF communication system 300 further comprises one the 3rd LPF380, one the 4th LPF385, one first analog/digital converter 390, one second analog/digital converter 395, first and second PLL330,335, one the 3rd blender 360 and a power amplifier 370.

This blender 340,345,370-373 all are used for demodulation, and the 3rd blender 360 is used for modulation.This first and second blender 340,345 is used for a RF frequency of selecting, and second level blender 370-373 chooses to be used for an intermediate frequency (IF).The one PLL 330 can be at a high frequency or RF frequency clocking, and the 2nd PLL 335 can produce the clock signal with low frequency or intermediate frequency (IF).

The transmission data multiply each other with the clock signal that has from the RF frequency of PLL 330, so that have from deduct the frequency of RF frequency from an original transmission data frequency.The output signal of the 3rd blender 360 is done the gain amplification at power amplifier 370, then via antenna 305 emissions.

For receiving data, this antenna 305 receives the RF signal, and this RF signal of filter RF 310 filtering.The RF signal of this filtering is amplified by LNA 320, and the single-frequency local oscillator that is generally VCD by 90 degree phase difference blenders 340,345 and converts intermediate-freuqncy signal to.This PLL 330 can produce the clock signal of the I signal and the Q signal of RF signal.This first blender 340 can multiply each other this RF signal and the clock signal with I signal of RF frequency, and this second blender 345 can multiply each other RF signal and the Q signal with RF frequency.This LPF the 350, the 355th uses in intermediater-frequency stage (that is, the first order), so that converting in the intermediate-freuqncy signal, remove any non-switched frequency content, it allows all passages can pass through this third level blender 370-373.All passages in intermediater-frequency stage can be directly changed into baseband frequency signal so that do channel selecting with frequency by adjustable PLL 335 then.

Demodulated base band signal C passes through filter (LPF) 380,385, and converts numerical data to by analog/digital converter 390,395.This numerical data can be transformed into base band discrete-time signal place (DSP) square (not demonstrating in the drawings) then.

As mentioned above, the RF system 300 that doubly changes of correlation technique has various advantage.This correlation technique doubly change RF system 300 and can use lower frequency to carry out channel modulation, that is, intermediate frequency, the 2nd PLL 335, rather than high frequency, that is, RF, a PLL 330.As a result, this high-frequency RF PLL 330 can be can more effective optimized fixed frequency PLL.In addition, since being to use frequency P LL 335, channel modulation, just can reduce so the phase noise of channel selecting produces carrying out than the low frequency operation.

Yet the RF system 300 that doubly changes of correlation technique has various shortcoming.The RF system that doubly changes of this correlation technique has two PLL300 that are not easy to be integrated in single-chip.In addition, the frequency of a PLL is to remain on to realize with the complementary metal oxide semiconductor technology, and is clearer and more definite, is to use a complementary metal oxide semiconductor VCD.The structure of this VCD and blender has about 1GHz restriction on the confidence level of complementary metal oxide semiconductor technology.In addition, a self-mixed problem still can take place, because the 2nd PLL is on the same frequency of the intermediate frequency carrier of needs.Fig. 5 A is that the clock signal that is described in the RF communication system 300 is leaked, and figure B is the direct current biasing of the variation of description time and " pacing up and down ", because leakage clock signal Δ (t) the cos ω in the RF of Fig. 4 communication system 300 _LO2(t) (for example, the oneself mixes).

At Fig. 5 A, this first blender is with this RF signal and has frequency W _LO1The clock signal cos ω of RF _Lo1Multiply each other, and output M (t) cos ω _LO2The RF signal of t, it has the frequency of deducting W _LO1Frequency.This second blender will from the RF signal of first blender with have frequencies omega _LO2The clock signal cos ω of intermediate frequency _LO2Multiply each other.Yet, before LPF, since the output signal frequency of this second blender is identical with the RF carrier frequency of needs.Therefore, the output signal of this second blender can leak to a substrate or leak to second blender again.This time changes direct current biasing can reduce the receiver part significantly together with intrinsic circuit bias dynamic range.

Above-mentioned reference paper is listed for reference at this, it has full and accurate description for extra or selectivity details, feature and technical background.

Summary of the invention

A purpose of the present invention is that essence is avoided the problem and the shortcoming of correlation technique at least.

Of the present invention one further purpose is the method that will make a complementary metal oxide semiconductor RF front end and use this front end, and it allows a chip of a RF communication system integrated.

Other purpose of the present invention is that a RF communication system and a method that reduces cost and power demand will be provided.

Still be the using method that a reliable high speed, low noise complementary metal oxide semiconductor RF communication system and this system will be provided for another object of the present invention.

The further purpose of the present invention is the frequency range that will increase the RF front end of a RF communication system.

The further purpose of the present invention is to make a voltage-controlled oscillator one blender in single substrate.

Another object of the present invention is the frequency range that will increase by a VCO-mixer structure.

Still be to reduce the noise of a voltage-controlled oscillator structure for another object of the present invention.

Another object of the present invention is the performance that will increase this VCO-mixer structure.

If will purpose according to the present invention reach above-mentioned purpose and advantage wherein whole at least or part, as embodying and describing widely, a kind of communication system of the present invention comprises: an acceptor unit, its reception comprise the signal of the selection signal with a carrier frequency; One monolock phase loop, it produces the multi-phase clock signal that is different from a frequency of this carrier frequency more than two have, and wherein, described multi-phase clock signal is combined and has a plurality of local oscillator signals of the second frequency that is higher than this frequency with generation; An and demodulation mixer, it mixes described received selection signal and described multi-phase clock signal more than two, the selection signal that has the frequency that deducts this carrier frequency with output, wherein, a signal in each described local oscillator signals demodulation I CF signal and the Q CF signal.

If will purpose further according to the present invention reach purpose whole or part, a kind of single-chip RF communication system comprises: a transmitter-receiver is used for receiving and sending the RF signal; One monolock phase loop is used for generation and has less than carrier frequency f ₀Basic identical frequency 2*f ₀A plurality of 2N phase clock signals of/N, wherein N is a positive integer, is used as number of phases; One demodulation mixed cell is used for and will mixes with a plurality of 2N phase clock signals from this phase-locked loop from the RF signal of this transmitter-receiver, and with the RF signal that output has the frequency that deducts this carrier frequency, wherein this demodulation mixer comprises a plurality of two input mixers; Wherein, these a plurality of 2N phase clock signals are combined with at least one signal in demodulation I CF signal and the Q CF signal; And an analog/digital conversion unit, be used for the RF conversion of signals from this demodulation mixed cell is become digital signal.

Remain purpose further according to the present invention and reach purpose whole or part, a kind of control method of RF communication system comprises: received signal, this signal comprise the selection signal with a carrier frequency; Generation is more than two multi-phase clock signal, and each multi-phase clock signal has an essentially identical frequency that is different from this carrier frequency, and described multi-phase clock signal is combined and has a plurality of local oscillator signals of the second frequency that is higher than this frequency with generation; Reach and select signal to mix received carrier frequency with described multi-phase clock signal more than two, have with output the frequency that deducts this carrier frequency by the selection signal of demodulation, so that from corresponding local oscillator signal demodulation first CF signal of described multi-phase clock signal combination more than two and a signal second CF signal.

Additional advantage of the present invention, purpose, and characteristic have the description of the technology in technology and become more obvious via describing below with part, or can understand from enforcement of the present invention.Purpose of the present invention and advantage, and can be well understood to from appendix claim book specifically noted.

The simple declaration of accompanying drawing

The present invention will describe in detail with reference to following accompanying drawing, and its similar reference number is the expression components identical, wherein:

Fig. 1 is the circuit diagram that shows a correlation technique RF communication system;

Fig. 2 is the circuit diagram of a correlation technique voltage-controlled oscillator one mixer structure;

Fig. 3 A is that the circuit clock signal that is presented at Fig. 1 leaks;

Fig. 3 B is that " oneself mix " of circuit of displayed map 3A is graphic;

Fig. 4 is the circuit diagram that shows another correlation technique RF communication system;

Fig. 5 A is presented in the circuit of Fig. 4 clock signal to leak;

Fig. 5 B is that " oneself mixes " that be presented in the circuit of Fig. 5 A is graphic;

Fig. 6 shows that according to the present invention first embodiment of heterogeneous low frequency (MPLF) RF communication system is graphic;

Fig. 7 shows PLL circuit exemplary block diagram;

Fig. 8 is the receiving unit calcspar that shows a RF communication system according to another embodiment of the present invention;

Fig. 9 is the RF communication system calcspar that shows the Fig. 8 with 6 phase places;

Figure 10 is the receiving unit calcspar that still shows a RF communication system according to embodiments of the invention;

Figure 11 is the RF communication system calcspar that shows the Figure 10 with 6 phase places;

Figure 12 still shows that according to embodiments of the invention the receiving unit square of a RF communication system is solid;

Figure 13 A is the calcspar that shows one voltage-controlled oscillating-mixer structure example;

Figure 13 B is the VCO-mixer structure circuit diagram of displayed map 13A;

Figure 14 is the circuit diagram that shows another VCO-mixer example; And

Figure 15 A-15H shows that the time sequential routine waveform of Figure 14 is graphic.

The detailed description of preferred embodiment

Use the formed single-chip RF communication system of complementary metal oxide semiconductor technology to have various demand.One complementary metal oxide semi-conductor electricity voltage-controlled oscillator (VCO) has relatively poor noise characteristic.Therefore, one complementary metal oxide semiconductor phaselocked loop road (PLL) integrated needs, yet, the number of PLL should be very little, and the intermediate frequency of a PLL (for example should be different from a RF frequency of transmitting ideally fully, be enough low ideally) so that use this complementary metal oxide semiconductor VCO to control a phase noise result.High-Q filter can be removed ideally, because relevant shortcoming zone and power requirements.And the many elements in complementary metal oxide semiconductor RF system should be very little or reduce, and can not lower efficiency.

First preferred embodiment of the present invention (MPLF) is changed RF communication system 500 at " heterogeneous low frequency " shown in Figure 6, and can form on single complementary metal oxide semiconductor chip ideally.This first preferred embodiment can be to surpass the frequencies operations of about 1GHz." conversion of leggy low frequency " term can be used, and can obtain by multiply by the leggy low-frequency periodic signal ideally because have a single-phase periodic signal of high frequency.First preferred embodiment of this MPLF conversion RF communication system 500 is to comprise a front end MPLF RF square 502 and Digital Signal Processing (DSP) square 504, and it is base band ideally.As mentioned above, correlation technique DSP square can form with the complementary metal oxide semiconductor technology.Therefore, the detailed description that comprises the DSP square of a digital signal processor 550 just can be omitted.

This MPLF conversion RF square 502 comprises an antenna 505, a RF filter 510 (for example, band pass filter), a low noise amplifier (LNA) 520 and first and second blender 530,560.This MPLF conversion RF square 502 further comprises a phase-locked loop (PLL) 540, a low pass filter (LPF) 580, an analog/digital (A/D) transducer 590, reaches a power amplifier 570 of coupling between second blender 560 and antenna 505.This PLL 540 can produce a modulation and demodulation clock, that is, local oscillator (LO), its frequency is by a reference clock (REF f ₀) decision.

Fig. 7 is the embodiment calcspar that shows PLL 540.This PLL 540 comprise respectively with reference to main dispenser 610,620, a phase comparator 630, a loop filter 640, an and voltage-controlled oscillator (VCO) 650.These VCO 650 output LO frequency f ₀, this frequency is compared with reference clock signal by phase comparator 630.The output signal of this phase comparator 630 can be passed through loop filter 640, is used as the control signal (for example, frequency) of VCO 650.According to this communication system, the frequency of this LO is variable idealistically.For example, the LO frequency of PCS Personal Communications System (PCS) can be about 1.8GHz, and the LO frequency of IMT 2000 systems is about 2.0GHz.

In first preferred embodiment of MPLF conversion RF communication system 500 shown in Figure 6, the transmission data are to be received from DSP square 504 by MPLF RF square 502.These transmission data are to modulate second blender 560 in the LO frequency ideally by one to be modulated.This modulating data is to be amplified by power amplifier 570, and by antenna 505 outputs.

The input signal that this low noise amplifier (LNA) 520 can receive from antenna 505, and the amplifying signal level is with output RF signal.This RF BPF 520 is coupling between antenna 505 and LNA 520 ideally.This RF signal comes demodulation by demodulation first blender 530 ideally on the frequency identical with modulating frequency.The output of this demodulation mixer 530 is by becoming the reception data by LPF 580.The data of this reception are to convert a digital signal to by analog/digital converter 590 ideally, and export DSP 550 to.

In order to use the single PLL of the intermediate frequency that enough is lower than transmission RF frequency, first preferred embodiment of this MPLF conversion RF communication system 500 is to use by multiply by the single-phase high frequency periodic signal that a heterogeneous low-frequency periodic signal obtained (that is, RF frequency).Especially, though non-being intended to of the present invention will be limited, a high frequency " sine " need use the system at RF with " cosine " signal.Has ω _RFThe sine of frequency and cosine signal can be by multiply by 2 ω that have shown in following equation 1 and 2 _RFThe N phase place sinusoidal signal of/N frequency obtains:

$\cos {\mathrm{\ω}}_{\mathrm{RF}}=2^{\frac{N}{2}-1}\underset{k=0}{\overset{\frac{N}{2}-1}{\mathrm{II}}}\sin (\frac{{2\·\mathrm{\ω}}_{\mathrm{RF}}}{N}\·t-\frac{2\·\mathrm{k\π}}{N}+\frac{\mathrm{\π}}{N})---\left(1\right)$

$\sin {\mathrm{\ω}}_{\mathrm{RF}}=2^{\frac{N}{2}-1}\underset{k=0}{\overset{\frac{N}{2}-1}{\mathrm{II}}}\sin (\frac{{2\·\mathrm{\ω}}_{\mathrm{RF}}}{N}\·t-\frac{2\·\mathrm{k\π}}{N})---\left(2\right)$

One multiplication factor is not " N " but " N/2 ", because remaining N/2 sinusoidal signal can be the reverse of a N/2 sinusoidal signal.This reverse signal is the differential signal that is used for making a difference input mixer ideally.

Fig. 8 is the receiving unit 700 that shows second preferred embodiment of a RF square according to the present invention, and it can use first preferred embodiment in MPLF conversion RF communication system.This receiving unit 700 comprises an antenna 715, a RF filter 720, a LNA 725 and a demodulation mixer 730.The receiving unit 700 of this RF square further comprises a PLL740, a low pass filter 780 and an analog/digital converter 790.This PLL 740 can produce a demodulation clock, that is, equal 2*f ₀The local oscillator of/N (LO), its frequency are to be determined by a reference clock (not demonstrating in the drawings).Antenna 715, RF filter 720, LNA 725, LPF 780 are similar in operation to first preferred embodiment with analog/digital converter 790, therefore just omit detailed description.

The receiving unit 700 of RF square uses a PLL 740.This PLL 740 uses 2*f ₀/ N frequency, and produce 2N phase clock signal altogether.This PLL 740 can produce N phase place ± LOcos, and (k is t) with N phase place ± LO _Sin(k, t) signal, its be ideally by as determine at following equation 3-4.

$\±L{O}_{\cos }(k,t)=\±\sin (\frac{2{\mathrm{\ω}}_{\mathrm{RF}}}{N}t-\frac{2\mathrm{k\π}}{N}+\frac{\mathrm{\π}}{N})\mathrm{wbeTe},k=\mathrm{0,1},2\·\·\·\frac{N}{2}-1---\left(3\right)$

$\±L{O}_{\sin }(k,t)=\±\sin (\frac{2{\mathrm{\ω}}_{\mathrm{RF}}}{N}t-\frac{2\mathrm{k\π}}{N})\mathrm{wbeTe},k=\mathrm{0,1},2\·\·\·\frac{N}{2}-1---\left(4\right)$

As shown in Figure 8, the receiving unit 700 of this RF square has the demodulation mixer 730 that is divided into top and following blender array 732,734.This comprises a plurality of 2 one traditional input mixers 735 with following blender array 732,734 above each.Should top blender array 732 be that (frequency is (2 ω with N phase place (N/2: non-return, N/2 is reverse) _RFThe sinusoidal signal of)/N) and a RF signal multiplication, it is to equal single-phase ω _RFThe cosine signal of frequency and RF signal multiplication.Non-return and reverse sinusoidal signal needs in order to import single blender, because these 2 traditional input mixers need the difference input.Should following blender array 734 be that (frequency is ω with N phase place (N/2 is non-return, and N/2 is reverse) _RF/ N) sinusoidal signal and RF signal, it is the ω that equals single-phase _RFSinusoidal signal and RF signal multiplication.Therefore, the receiving unit 700 of this RF square is similar to direct transformational structure shown in Figure 1 on function.Yet receiving unit 700 according to the present invention is to use the N phase place, 2 ω _RFThe sinusoidal signal demodulation of the frequency of/N rather than single-phase ω _RFSinusoidal signal.

As mentioned above, this PLL 740 can produce the 2N phase clock signal.The N phase clock signal is N phase place sinusoidal signal and N phase cosine signal.Two N phase signals comprise non-return signal of N/2 and N/2 reverse signal.Blender array 732 above this N phase place sinusoidal signal can be imported together with the RF signal, and this N phase place sinusoidal signal can be together with blender array 734 below the input of RF signal.Should toply have a plurality of blenders 735 and M progression respectively with following blender array 732 and 734.This M progression comprises the first order, (for example, 735), the second level (for example, 735 ') ..., M-1 level, and M level (for example, 735 ").Each grade of each blender array comprises a blender that has two inputs at least.Blender number K1 on the first order is the highest number of stages.Afterbody M level has the minimal number (KM) of blender in whole level.The relative progression of blender among level can be represented K1＞K2＞K3＞K4 with inequation ... KM-1＞KM.

Each blender 735 has two inputs.Each input has a reverse signal and a non-return signal of reverse signal, because each input of this blender 735 is to import two different signals.As mentioned above, be the input signal of on the first order, being used as blender 735 from the RF signal of LNA 725 with n-signal from PLL 746.Output signal at the blender on the first order 73 is that the input signal of being used as blender 735 ' on the second level uses.In an identical manner, the blender output signal on the M-1 level is to be used as blender 735 " two input signals use, it is the single blender on the M level of blender array 732 and following blender array 734 in the above.

Fig. 9 is the 6 phase place examples that show the receiving unit 700 of MPLF conversion RF communication system, and it is to use 2 traditional input mixers.One PLL 840 produces the 12 phase place sinusoidal signals that can send blender 830 to.Adjoining two phase difference between signals are π/6 (that is, 2 π/12).Phase place (0,2,4,6,8,10) is that the input of being used as top blender 832 is used, and multiplies each other with RF input ideally, and it is to equal cos (ω _RFT) with the product of RF input.Blender 834 below phase place (1,3,5,7,9,11) can be imported, and can multiply each other with the RF input ideally, and equal sin (ω _RFT) with the product of RF input.Therefore, in clock signal and RF signal multiplication, the frequency of this clock signal is f ₀

This PLL 840 comprises the clock generator such as a voltage control source (VCO), and so just can produce 12 phase clock signals that multiply each other with RF in modulation.The clock signal of this generation has the frequency f of being lower than ₀ Frequency 2*f ₀/ P (P=number of phases), with the RF signal multiplication.Clock signal from PLL 840 has lower frequency 2*f ₀/ P, because PLL 840 meeting generation multi-phase clock signal phase places 0 ..., phase place 12.The RF signal of filtering is to do gain at LNA725 to amplify, and multiplies each other with multi-phase clock signal, thereby in 12 sinusoidal signals of blender array 830 generations in order to modulation.The amount that the RF signal frequency that multiplies each other with clock signal is lower than initial frequency is the last frequency f of clock signal ₀

Initial frequency 2*f from the clock signal of PLL 840 ₀/ P can change over f ₀, in order at blender (for example, blender array) 830 and RF signal multiplication.Therefore, above this blender array 832 with should below blender array 834 is capable of being combined becomes to have 2*f ₀The clock signal of/P, and will have frequency f ₀Clock signal and RF signal multiplication.As a result, have and reduced frequency f ₀The RF signal of frequency can be by LPF 780 and analog/digital converter 790, and be sent to DSP part (not demonstrating in the drawings).The 12 phase place sinusoidal signals that PLL 840 is produced are as follows:

Phase place 0: $\sin (\frac{{\mathrm{\ω}}_{\mathrm{RF}}}{3}t+\frac{\mathrm{\Π}}{6})$

Phase place 1: $\sin (\frac{{\mathrm{\&omega;}}_{\mathrm{<figure-callout\; id="3"\; label="RF"\; filenames="C9980876400291.png,C9980876400361.png"\; state="\{\{state\}\}">RF</figure-callout>}}}{3}\&CenterDot;t)$

Phase place 2: $\sin (\frac{{\mathrm{\&omega;}}_{\mathrm{RF}}}{3}t-\frac{\mathrm{\&Pi;}}{6})$

Phase place 3: $\sin (\frac{{\mathrm{\&omega;}}_{\mathrm{RF}}}{3}t-\frac{2\mathrm{\&Pi;}}{6})$

Phase place 4: $\sin (\frac{{\mathrm{\&omega;}}_{\mathrm{RF}}}{3}t-\frac{3\mathrm{\&Pi;}}{6})$

Phase place 5: $\sin (\frac{{\mathrm{\&omega;}}_{\mathrm{RF}}}{3}t-\frac{4\mathrm{\&Pi;}}{6})$

Phase place 6: $-\sin (\frac{{\mathrm{\&omega;}}_{\mathrm{RF}}}{3}t+\frac{\mathrm{\&Pi;}}{6})$

Phase place 7: $-\sin \left(\frac{{\mathrm{\&omega;}}_{\mathrm{RF}}}{3}t\right)$

Phase place 8: $-\sin (\frac{{\mathrm{\&omega;}}_{\mathrm{RF}}}{3}t-\frac{\mathrm{\&Pi;}}{6})$

Phase place 9: $-\sin (\frac{{\mathrm{\&omega;}}_{\mathrm{RF}}}{3}t-\frac{2\mathrm{\&Pi;}}{6})$

Phase place 10: $-\sin (\frac{{\mathrm{\&omega;}}_{\mathrm{RF}}}{3}t-\frac{3\mathrm{\&Pi;}}{6})$

Phase place 11: $-\sin (\frac{{\mathrm{\&omega;}}_{\mathrm{RF}}}{3}t-\frac{4\mathrm{\&Pi;}}{6})$

Figure 10 is the MPLF conversion receiving unit 900 that the 3rd preferred embodiment according to the present invention shows a RF square, and it can use first preferred embodiment in MPLF conversion RF communication system.This receiving unit 900 comprises that an antenna 915, a RF filter those devices 920, a LNA925 and blender 930.The receiving unit 900 of RF square further comprises a PLL 940, a LPF 90 and an analog/digital converter 990.This PLL 940 can produce a demodulation clock ideally, that is, equal 2*f ideally _RFThe local oscillator of/N (LO), its frequency are to be determined by a reference clock (not demonstrating in the drawings).Antenna 915, RF filter 920, LNA 925, LPF 980 and analog/digital converter 990 are similar in operation to first preferred embodiment, therefore will describe omission in detail.

900 of the receiving units of RF square use a PLL.This PLL 940 comprises and uses 2*f ideally ₀One clock generator 942 of/N frequency.This clock generator 942 can produce N phase place ± LO ideally _Cos(k is t) with N phase place ± LO _Sin(it always has the 2N phase signal for k, t) signal.This clock generator 942 is a heterogeneous VCO ideally, and mixing portion 930 also is heterogeneous blender.

As shown in figure 10, the receiving unit 900 of RF square uses heterogeneous blender 932 and 934.Should above heterogeneous blender 932 replace the function of blender array 732 above this, and should below heterogeneous blender 934 replace the function of blender array 734 below this.

The clock signal that this PLL 940 produces in order to modulation and demodulation.But clock generator 942 clockings of this PLL 940, it has the frequency 2*f in order to demodulation and modulation ₀/ N (N=number of phases).This clock generator 942 can produce has frequency 2*f ₀The clock signal of/N is because the frequency limits of implementing according to the complementary metal oxide semiconductor device.For the complementary metal oxide semiconductor of a RF communication system was implemented, the frequency of this clock generator 942 should be the frequency that is different from and is lower than mixing portion 930.

Figure 11 is the 6 phase place examples that show the receiving unit 1000 of the MPLF conversion RF communication system of using heterogeneous input mixer.One PLL 1040 can produce 12 phase place sinusoidal signals, and these signals send a heterogeneous blender 1030 to.Phase place (0,2,4,6,8,10) is that the input of being used as blender 1032 above is used, and multiplies each other with RF input ideally, and it equals cos (ω _RFT) with the product of RF input.Phase place (1,3,5,7,9,11) is the blender 1034 below the input, and is to multiply each other with the RF input ideally, and it is to equal sin (ω _RFT) with the product of RF input.

Figure 12 is the MPLF conversion hop 1100 that the 4th preferred embodiment according to the present invention shows a RF square, and it can use first preferred embodiment in MPLF conversion RF communication system.This receiving unit 1100 comprises an antenna 1105, a blender 1160, a PLL 1140, a plurality of LPF 1180, a plurality of digital-to-analog (D/A) transducer 1190 and is coupling in a power amplifier 1170 between blender 1160 and the antenna 1105.This PLL 1140 can use a clock generator 1142 to come clocking.This clock generator 1142 can use local oscillator (LO) to produce a modulation and demodulation clock signal ideally, and its frequency is by a reference clock (f _RF) decision.

In the 4th preferred embodiment of the translator unit 1100 of a RF square, numerical data is to receive from DSP square (not demonstrating in the drawings), and converts an analog signal to by digital/analog converter 1190, and by LPF 1180 filtering.This blender 1160 be ideally from PLL 1140 receive heterogeneous low frequency (that is, 2*f ₀/ N) clock signal reaches the baseband signal from LPF 1180, is f to produce frequency _RPA modulated rf signal.This blender 1160 comprises the heterogeneous blender 1165 of upwards changing ideally.Figure 12 also shows the heterogeneous embodiment calcspar of upwards changing blender 1165.This blender 1165 uses two control circuit squares 1162 and 1164, but its receive clock signal LO (0 ..., N-1) ,/LO (0 ..., N-1), to produce this modulated RF signal.The RF data of this modulation are to be amplified by power amplifier 1170, and then by antenna 1105 outputs.

As mentioned above, the blender of demodulation can reduce the high-frequency RF signal with clock signal frequency by RF signal and clock signal are multiplied each other.In the 4th preferred embodiment, but this blender 1160 modulation transmissions data ideally, and so that increase the low-frequency transmission data frequency, increment is the combination clock signal frequency.When modulation, noise is remarkable like that not as separating timing to the influence of transmission data.Yet, minimizing clock signal LO (0 ..., N-1) frequency can reduce or remove noise really such as parasitic capacitance.In addition, approximately the frequency limit of the complementary metal oxide semiconductor technology of 1GHz can overcome.Therefore, the 4th preferred embodiment has the advantage identical with the 3rd preferred embodiment.

Figure 13 A is a VCO-mixer structure calcspar according to a preferred embodiment of the present invention.The United States Patent (USP) case that this VCO-mixer circuit has been applied at Kyeongho Lee number 09/121,863 is described in the title " VOC-MIXERSTRUCTURE ", only lists for reference at this.This structure comprises a ployphase voltages control generator VCO 1250 and one heterogeneous blender 1200.This heterogeneous blender 1200 comprises a differential amplifier circuit 1200A and a combinational circuit 1200B.

When use has f _REF=f ₀In one reference frequency signal of reference clock, this heterogeneous VCO 1250 can produce has 2*f ₀A plurality of N phase clock signal LO (i=0 to N-1) of/N frequency, wherein N=N _D* 2, and N _DEqual the delay cell number in heterogeneous VCO 1250.In other words, this VCO 1250 can be with frequency f ₀Reduce to 2*f ₀/ N.So just can reduce the phase noise of heterogeneous VCO and increase frequency range.

Has 2*f ₀A plurality of N phase places of/N frequency middle clock signal LO (0), LO (1) ..., LO (N-1) is input to the combinational circuit 1200B of heterogeneous blender 1200, and is input to this differential amplifier circuit 1200A such as the input signal of RF signal RF+, RF-.But this differential amplifier circuit 1200B difference is amplified this radio frequency signals RF+, RF-.This combinational circuit 1200B is in response to a bias voltage V _Bias, and clock signal LO (0)-LO (N-1) in the middle of the combination N phase place, have initial frequency f with generation ₀Clock signal LOT+, LOT-.This blender 1200 can be reached multiplying each other of clock signal LOT+, LOT-and this RF signal RF+, RF-then.Figure 13 B is a circuit diagram example of describing VCO-mixer structure 1250,1200.Heterogeneous VCO 1250 comprises the delay cell 1250 of series connection ₁-1250 _NDNumber.Based on this configuration, this heterogeneous VCO can produce the middle clock signal LO (0) of a plurality of N phase places-LO (N-1), and these signals have 2*f ₀/ N frequency.Comprise a phase-frequency detector 1254, a charge pump 1256 and a loop filter 1258 in order to VCO 1250 control circuits that produce a frequency control signal, it can export this frequency control signal to this each delay cell 1250 ₁-1250 _NDThis phase-frequency detector 1254 can receive respectively the reference clock signal f from a reference clock divider circuit and a VCO clock divider circuit 1253 _RefWith a VCO clock signal.The frequency of this clock signal LO (φ)-LO (N-1) is by M '/K ' (f _Ref)=2f ₀/ N represents.Therefore, frequency f ₀Be based on reference clock signal f _RefWith this divider circuit 1252,1253.In other words, f _VCOCan be the 2f that sets the M '/K ' of divider circuit 1252,1253 ₀/ N.

The differential amplifier circuit 1200A of this heterogeneous blender 1200 comprises two load resistance R1 ', R2 ', and these load resistances are coupled respectively to two differential amplifier 1200A ₁, 1200A ₂This first differential amplifier 1200A ₁Comprise two nmos pass transistors 1210,1212, and this second differential amplifier 1200A2 also comprises two nmos pass transistors 1214,1216.The drain electrode of this nmos pass transistor 1210,1216 is coupled respectively to this load resistance R1 ', R2 ', and the coupling of the gate pole of this nmos pass transistor 1210,1216 is in order to receive RF signal RF+.In addition, the drain electrode of this nmos pass transistor 1212,1214 is to be coupled respectively to this load resistance R2 ', R1 ', and gate pole is that coupling is in order to receive RF signal RF-.The source electrode of nmos pass transistor 1210,1212 and nmos pass transistor 1214,1216 is coupled to each other, and is connected to the combinational circuit 1200B of heterogeneous blender.

This differential amplifier 1200A ₁, 1200A ₂Difference is amplified this RF signal RF+, RF-respectively, so that obtain more accurate output signal OUT-, OUT+.In addition, this difference is amplified the removable noise that may add this RF signal RF+, RF-.In present preferred embodiment, comprise two differential amplifier 1200A ₁, 1200A ₂Yet, in the embodiment that the present invention substitutes, can also only use one of this differential amplifier to realize.

This combinational circuit 1200B comprises bias voltage nmos pass transistor 1232,1234, the first assembled unit 1200B, reaches the second assembled unit 1200B ₂, the latter two are coupled respectively to bias voltage nmos pass transistor 1232,1234, and a current source I _S1, it is coupled to this first and second assembled unit 1200B ₁, 1200B ₂This first assembled unit 1200B ₁, comprise a plurality of transistor units 1220 ₀, 1220 ₂..., 1220 _N-2, and this second assembled unit comprises more than second transistor unit 1220 ₁, 1220 ₃..., 1220 _N-1

Ideally, each of a plurality of transistor units comprises a plurality of serial transistors, wherein the serial transistor parallel coupled of this serial transistor and a plurality of transistor units.Ideally, each transistor unit comprises two (2) serial transistors.Therefore, in preferred embodiment, in each assembled unit 1200A or 1200B, the whole transistor unit number that N/2 is arranged is so that the sum of nmos pass transistor is 2*N.

The gate pole coupling of this bias voltage nmos pass transistor 1232,1234 is in order to receive bias voltage V _Bias, and the coupling of the transistor gates in this first and second a plurality of transistor units has 2*f accordingly in order to receive one ₀Clock signal LO (i) and/LO (i) in the middle of the N phase place of/N frequency, wherein/LO (i)=LO (N/2+i), i=0,1 ..., N/2-1.In present preferred embodiment, comprise that this bias voltage nmos pass transistor 1232,1234 is in order to avoid mistake.Yet this transistorlike can omit in alternate embodiment.In addition, the sequential turn-on-shutoff operation of the 2*N number N MOS transistor of combinational circuit 1200B is corresponding to the NAND logical circuit, and logical circuit that it in another embodiment can be equal and structure substitute.

Figure 13 B structure allows integrated heterogeneous VCO 1250 and heterogeneous blender 1200 on single-chip, that is, on a single semiconductor-based end, use the complementary metal oxide semiconductor technology.This structure can reduce and comprises the noise that is produced by parasitic capacitance with design.As mentioned above, use the difference of this RF signal RF+ and RF-to amplify at differential amplifier circuit 1200A and can reduce noise.

Has 2*f ₀Clock signal LO (i) is divided by reference frequency f in the middle of the N phase place of/N frequency ₀Also can reduce noise.In a plurality of transistors formed in same substrate, for example the semiconductor-based end of complementary metal oxide semiconductor technology, a plurality of P-N joints just can form in substrate.This parasitic capacitance is present in the P-N joint mostly.If it is very high to apply to the frequency of transistor gates, with 2*f ₀The minimizing frequency of/N mutually quite, the f of higher-frequency ₀Just can cause more noise.

In addition, clock signal LOT+, LOT-that the operation of this differential amplifier circuit 1200A and this combinational circuit 1200B is decided by to have the f0 frequency, the latter two signals are respectively by this first and second assembled unit 1200B ₁, 1200B ₂Provide, this is to have 2*f by combination ₀Clock signal LO (i) realizes in the middle of the N phase place of/N frequency.When applying this bias voltage V _BiasThe time, this nmos pass transistor 1232,1234 just can be transformed into conducting and closed condition based on this output signal LOT+, LOT-.Though this nmos pass transistor 1210,1212,1214 and 1216 can be transformed into conducting state by this PF signal RF+, the RF-that offers gate pole, when this bias voltage nmos pass transistor 1232,1234 in clock signal LOT+, LOT-conducting, just can carry out in order to the amplification of this RF signal RF+, the RF-that produce this output signal OUT+, OUT-and the amplification of clock signal LOT+, LOT-.

Figure 14 describes to work as N _D=3 heterogeneous VCO and another preferred embodiment of heterogeneous blender when the N=6, and Figure 15 A-15H schemes in the time sequential routine that is described in the preferred embodiment circuit shown in Figure 14.This heterogeneous VCO 1250 comprises 3 delay cell 12501-12503, to produce the middle clock signal LO (0) of 6 phase places-LO (5).Comprise delay cell 1250 ₁-1250 ₃(that is, this delay cell 1250 ₁) 5 transistorized circuit examples also demonstrate.In order to illustrate, if this input clock signal has frequency f ₀=1.5GHz, clock signal LO (0) in the middle of 6 phase places-LO (5) just has the frequency of 0.5GHz.

This 6 phase blender 1280 comprises a differential amplifier circuit 1280A and a combinational circuit 1280B.This differential amplifier circuit 1280A comprises one first differential amplifier 1280A ₁, it has nmos pass transistor 1260 and 1262; One second differential amplifier 1280A ₂, having nmos pass transistor 1264 and 1266, these two differential amplifiers are coupled respectively to load resistance R3 and R4.This combinational circuit 1280B comprises first and second assembled unit 1280B ₁, 1280B ₂, the two coupled in common is to current source I _S2This first and second assembled unit 1280B ₁, 1280B ₂Be coupled respectively to this first and second differential amplifier 1280A via bias voltage nmos pass transistor 1282,1284 ₁, 1280A ₂, the latter two are subjected to bias voltage V _BiasBias voltage.Repeatedly, this first and second assembled unit 1250B ₁, 1250B ₂Comprise 6 transistor units 1270 ₀-1270 ₅, and whole 10 transistors are arranged.

Shown in Figure 15 A-15F, this 6 phase place VCO 1250 can produce the frequency f with reduction ₀Clock signal LO (1) in the middle of/3 6 phase places-LO (5).This 6 phase blender 1250 receives the middle clock signal LO (1) of 6 phase places-LO (5) and this RF signal RF+ and RF-.Clock signal LO (1) in the middle of each-LO (5) and/LO (0)-/LO (2) (wherein/LO (0)=LO (3) ,/LO (1)=LO (4) reaches/LO (2)=LO (5)) be applied to this first and second assembled unit 1280B ₁, 1280B ₂A corresponding crystal pipe.This first and second assembled unit 1280B ₁, 1280B ₂Combination has frequency f ₀/ 36 phase places middle clock signal LO (0), LO (1) ..., LO (4), LO (5), have frequency f with generation ₀This clock signal LOT+ and LOT-.

When LO (0) is a high potential and LO (1) is that (LO (4): in the time of height), two output signal LOT+, LOT-are respectively electronegative potential and high potential to electronegative potential.When LO (1) is a high potential and LO (2) is that (LO (5): in the time of height), this output signal LOT+, LOT-are respectively high potential and electronegative potential to electronegative potential.When LO (2) is a high potential and LO (3) is that (LO (0): in the time of height), this output signal LOT+, LOT-are respectively electronegative potential and high potential to electronegative potential.When LO (3) is a high potential and LO (4) is that (LO (1): in the time of height), this output signal LOT+, LOT-are respectively high potential and electronegative potential to electronegative potential.When LO (4) is a high potential and LO (5) is that (LO (2): in the time of height), the output signal LOT+ of this blender 503, LOT-are respectively low and high potentials to electronegative potential.When LO (5) high potential and LO (0) is that (LO (3): in the time of height), this output signal LOT+, LOT-are respectively low and high potentials to electronegative potential.

Each pair nmos transistor is to connect in regular turn in combinational circuit, produces output signal LOT+ and LOT-shown in Figure 15 G and 15H thus.

As mentioned above, this preferred embodiment has various advantage.The preferred embodiment of MPLF conversion RF communication system without any need for high-Q filter, and only use 1 PLL.Therefore, this MPLF transformational structure can be easily integrated on a complementary metal oxide semiconductor chip.In addition, the frequency of channel selecting PLL is from F _RPReduce to (2f _RP)/N, this causes the phase noise of the clock generation circuit of VCO to reduce and channel selecting easy to implement.Especially, this PLL frequency (LO) is different from (for example less than) carrier frequency.As a result, the preferred embodiment of MTLF RF communication system comprises the direct conversion of relevant technologies at least and the advantage of times converts communications system, and removes the shortcoming of two structures.

In addition, one is firm and low noise CO and blender can be made in single substrate, can use the complementary metal oxide semiconductor technology to implement on the semiconductor-based end ideally.Can reduce significantly by the interference that input signal and input clock signal caused, because the modulation of the frequency departure of middle clock signal is single frequently.This phase lock ring road (PLL) frequency range can increase, because the PLL frequency range can easily increase on the low frequency situation.And this result can improve the channel selecting ability of RF front end in the RF communication system.

Previous embodiment is only in order to illustrating, rather than is construed as limiting the invention.Aim of the present invention can easily apply to the device of other types.Description of the invention is to be intended to explanation, rather than limits the scope of applying for a patent.Many substitutes, revises, reaches to change and know in this technology.In claims, the narration that device adds function is intended to cover functional structure described herein, is not only structural equivalent, and also is equal to

Structure.

Claims (18)

1. communication system comprises:

One acceptor unit, its reception comprise the signal of the selection signal with a carrier frequency;

One monolock phase loop, it produces the multi-phase clock signal that is different from a frequency of this carrier frequency more than two have, and wherein, described multi-phase clock signal is combined and has a plurality of local oscillator signals of the second frequency that is higher than this frequency with generation; And

One demodulation mixer, it mixes described received selection signal and described multi-phase clock signal more than two, the selection signal that has the frequency that deducts this carrier frequency with output, wherein, a signal in each described local oscillator signals demodulation I CF signal and the Q CF signal.

2. communication system as claimed in claim 1, wherein this frequency is less than this carrier frequency, this RF communication system is operated under the carrier frequency greater than 1GHz, and wherein this RF communication system is formed on the single CMOS chip, and wherein this phase-locked loop comprises a clock generator.

3. communication system as claimed in claim 1, wherein this acceptor unit is a transmitter-receiver, it further comprises:

One modulation blender, it is with described multi-phase clock signal and transmission data mixing, and to modulate this transmission data, described multi-phase clock signal plays a part local oscillator signals; And

One power amplifier, it amplifies this modulated transmission data, and sends these data to this transmitter-receiver so that transmission.

4. communication system as claimed in claim 1, it further comprises:

One RF filter, it is coupled to this acceptor unit, is used for this selection signal that is received of filtering;

One low noise amplifier, it is coupled to this RF filter, is used for amplifying filtered selection signal with a gain;

One low pass filter, it is coupled to this demodulation mixer, is used for the selection signal that filtering has the frequency that deducts this carrier frequency;

One analog/digital conversion unit, it will become digital signal from the selection conversion of signals of this demodulation mixer; And

One discrete-time signal processing unit, it receives described digital signal.

5. communication system as claimed in claim 1, wherein:

This communication system is a RF receiver part;

Described selection signal is the RF signal;

Described multi-phase clock signal have (frequency of 2* carrier frequency/N), wherein N is the big positive integer of a ratio 2;

This RF communication system forms on a single CMOS chip.

6. communication system as claimed in claim 1, wherein, this demodulation mixer comprises one first blender array and one second blender array, and each of this first and second blenders array comprises a plurality of many input mixers.

7. communication system as claimed in claim 1, wherein, this demodulation mixer comprises one first blender array and one second blender array, each of this first and second blenders array has a plurality of mixer stage, each level of described mixer stage has at least one many input mixer, and wherein the output signal from least one many input mixer of the described multistage first order is imported into described multistage partial at least one many input mixer.

8. communication system as claimed in claim 1, wherein, described multi-phase clock signal more than two comprises multi-to-multi phase clock signal, and each of described multi-to-multi phase clock signal is to comprising an I CF signal and a Q CF signal.

9. communication system as claimed in claim 1 wherein, forms a reference signal by making up described multi-phase clock signal more than two.

10. single-chip RF communication system comprises:

One transmitter-receiver is used for receiving and sending the RF signal;

One monolock phase loop is used for generation and has less than carrier frequency f ₀Basic identical frequency 2*f ₀A plurality of 2N phase clock signals of/N, wherein N is a positive integer, is used as number of phases;

One demodulation mixed cell is used for and will mixes with a plurality of 2N phase clock signals from this phase-locked loop from the RF signal of this transmitter-receiver, and with the RF signal that output has the frequency that deducts this carrier frequency, wherein this demodulation mixer comprises a plurality of two input mixers; Wherein, these a plurality of 2N phase clock signals are combined with at least one signal in demodulation I CF signal and the Q CF signal; And

An analog/digital conversion unit is used for the RF conversion of signals from this demodulation mixed cell is become digital signal.

11. single-chip RF communication system as claimed in claim 10, wherein, this demodulation mixed cell comprises one first blender array, and it comprises described two input mixers half; And one second blender array, it comprises described two input mixers second half, each blender array is respectively imported the N phase clock signal of corresponding 2N phase clock signal together with described RF signal.

12. single-chip RF communication system as claimed in claim 11, wherein, each blender array comprises multi-level mixer, and every grade comprises at least one two input mixer, and the described multistage first order is imported described RF signal and N phase clock signal.

13. single-chip RF communication system as claimed in claim 12, wherein, described multistage blender with corresponding minimizing count K1＞K2＞K3＞...＞Ki, wherein K1 is the first order, K2 is the second level, K3 is the third level, Ki is the i level.

14. single-chip RF communication system as claimed in claim 10, wherein, this demodulation mixed cell comprises one first blender array and one second blender array, each of this first and second blenders array comprises a plurality of many input mixers, wherein forms local oscillator signals by making up described a plurality of 2N phase clock signal.

15. single-chip RF communication system as claimed in claim 10, wherein, described a plurality of 2N phase clock signal is divided into more than first clock signal and more than second clock signal, described more than first clock signal is combined to form an I carrier frequency, and described more than second clock signal is combined to form a Q carrier frequency.

16. a control method that is used for a RF communication system comprises:

Received signal, this signal comprise the selection signal with a carrier frequency;

Generation is more than two multi-phase clock signal, and each multi-phase clock signal has an essentially identical frequency that is different from this carrier frequency, and described multi-phase clock signal is combined and has a plurality of local oscillator signals of the second frequency that is higher than this frequency with generation; And

Select signal to mix received carrier frequency with described multi-phase clock signal more than two, have with output the frequency that deducts this carrier frequency by the selection signal of demodulation, so that from corresponding local oscillator signal demodulation first CF signal of described multi-phase clock signal combination more than two and a signal second CF signal.

17. method as claimed in claim 16, it further comprises:

Received selection signal is carried out RF filtering;

Amplify filtered selection signal with a gain; And

Low-pass filtering have the base band of being reduced to frequency by the selection signal of demodulation;

The selection signal that this low pass filtered frequency is reduced carries out analog/digital conversion, makes it convert digital signal to; And

Described digital signal is carried out discrete-time signal to be handled.

18. method as claimed in claim 16, it further comprises:

The multi-phase clock signal that is combined into described local oscillator signals is mixed with the transmission data-modulated, to modulate this transmission data; And

The transmission data that this is modulated are carried out power amplification, and these data are sent to transmitter-receiver in order to transmission.

Images