KR20000038360A - Method for controlling multiple phase voltages and structure of frequency mixer using the same - Google Patents

Abstract

PURPOSE: A method for controlling multiple phase voltages and a structure of a frequency mixer the same are provided to solve the problem the limit of a CMOS transistor in switching speed and faulty phase noise characteristic by mixing the received RF(Radio Frequency) signal with using multiple phase voltage control oscillation signal. CONSTITUTION: A signal generator having a second frequency, which is a low frequency, as oscillation frequency, generates a plurality of positive and negative multiple phase voltage control oscillation signal having a phase difference as much as predetermined amount. A frequency converter generates a first frequency signal by repeatedly switching in a clock cycle of the second frequency with inputting the multiple phase voltage control oscillation signal generated from the signal generator. A frequency mixer(302) multiplies the output signal of the frequency converter and the received RF signal.

Description

Multiphase Voltage Control Method and Frequency Mixer Structure Using the Same

The present invention relates to a wireless communication apparatus and method, and more particularly, to a wireless communication apparatus and method in which a local oscillator and a frequency mixer for RF reception are implemented in a single functional block.

Today, wireless communication technology is growing rapidly in the electronic communication industry. In other words, continuous research and development of personal portable wireless communication technology is bringing about innovative changes in quality and quantity so that the ultimate goal of communication can be delivered immediately to anyone, anywhere, anytime.

In particular, miniaturization and weight reduction of RF wireless communication devices requires integration of a single one chip such as a front-end RF block and a base-band digital signal processing (DSP) block. .

However, in the current technology, the baseband DS block can be easily implemented as a low-power CMOS technology, but the RF block is not easy to be implemented by the low-power CMOS technology described above. This is because silicon CMOS technology has very low operating frequency characteristics (~ hundreds of MHz), poor phase noise characteristics, and RF reception requiring high cutoff frequency characteristics and low noise characteristics. This is because the specification of the block cannot be satisfied.

Therefore, RF front-end chips in the market are usually manufactured using expensive bipolar or BiCMOS technology. Nevertheless, attempts are being made to one-chip the RF front end using CMOS technology along with the base band block. This is because, although the one-chip design of the RF front end and the baseband DS block is a technically difficult task, it is an essential element for miniaturizing and lightening a wireless transmission / reception terminal.

The radio transceiver according to the prior art usually relies on a superheterodyne scheme, the functional block diagram of which is shown in FIG. Referring to FIG. 1, a conventional superheterodyne transmit / receive system includes a phase comparator 100, a low band filter 101, and a voltage controlled oscillator (VCO) 102. locked loop 105 block, frequency mixers 103 and 104, power amplifier 106, low noise amplifier 107, and the like.

FIEL 105 is the modulation and demodulation frequency determined by the reference clock. LO (f ₁ ) Will generate a frequency LO The size varies depending on the communication system. In other words, the PC system (PCS) LO Frequency is 1.8 GHz, and IMT 2000 systems LO The frequency is set to 2.0 GHz.

Frequency for transmitting a wireless signal through the antenna 110 LO Is input to the power amplifier 106 via a frequency mixer 103 via a modulating step. In the process of receiving the wireless data, the RF signal received through the low noise amplifier 107 is the initial frequency equal to the modulation frequency LO Is frequency-mixed into the frequency mixer 104 to obtain a demodulated baseband signal.

Referring back to FIG. 1, the center block for modulating or demodulating the RF radio signal is comprised of a voltage controlled oscillator (VCO) 102 and a frequency mixer 104, the voltage controlled oscillator 102 and the frequency mixer (described above). There are several difficulties in integrating 104 into a single chip. That is, when implementing the voltage controlled oscillator 102 using CMOS technology, the center frequency is 2.0 GHz due to the high phase noise figure and the low frequency operating characteristics. LO There is a difficulty in generating it.

Accordingly, according to the prior art, a structure in which the CMOS voltage controlled oscillator and the frequency mixer are combined in the manner shown in FIG. 2 is used. That is, the CMOS voltage controlled oscillator (VCO) circuit according to the related art is composed of an automatic amplifier delay circuit based on a ring oscillator structure, and a clock for demodulation. LO And inverted clock Generates.

In addition, as the frequency mixer 121 according to the prior art, a Gilbert multiplier is used, and from the voltage controlled oscillator 120 described above, LO Wow Take a clock signal RF And And multiplication.

However, as described above, in the 2.0 GHz band according to the prior art. LO It is also difficult to generate good frequency mixing results because of the phase noise problem and low operating frequency characteristics of CMOS technology.

It is therefore a first object of the present invention to provide a communication apparatus and method for integrating a voltage controlled oscillator and frequency mixer for RF wireless communication into a single chip.

A second object of the present invention is to provide a communication apparatus and method for integrating a voltage controlled oscillator and frequency mixer for personal portable communication in the 2.0 GHz band into a single chip in addition to the first object.

According to a third object of the present invention, in addition to the first object, in a system in which a frequency operation speed and a noise characteristic are not good due to the characteristics of a transistor to be implemented by a wireless RF frequency, an RF transmission and reception front end voltage controlled oscillator and a frequency mixer are provided. The present invention provides a communication apparatus and method for integrating a single chip.

A fourth object of the present invention is, in addition to the first object, in the oscillator and frequency mixer structure for RF wireless communication, a communication device and method implemented by CMOS which minimizes mutual disturbance between RF signal and local oscillation signal. To provide.

1 is a circuit diagram showing a superheterodyne receiving circuit according to the prior art.

2 is a circuit diagram showing a voltage controlled oscillator and a frequency mixer according to the prior art.

3 is a circuit diagram illustrating a six-phase voltage controlled oscillator and a frequency mixer according to a first embodiment of the present invention.

4 is a timing diagram of a six-phase voltage controlled oscillation signal and an output signal according to the first embodiment of the present invention.

5 is a circuit diagram illustrating a multiple (N) phase voltage controlled oscillator and a frequency mixer according to a second embodiment of the present invention.

<Description of Main Parts of Drawing>

100: phase comparator

101: low pass filter

102: voltage controlled oscillator

103: frequency mixer

105: Piel

501 multi-phase voltage controlled oscillator

502: Multiphase Frequency Mixer

In order to achieve the above object, the present invention provides a frequency conversion method for demodulating a received signal having a first frequency f ₁ as a carrier frequency into a base band, wherein the signal having the first frequency f ₁ as a carrier frequency is used. Receiving; A plurality of N multiphase voltage controlled oscillation signals each having a predetermined phase difference Δ are generated using the second frequency f ₂ , which is lower than the first frequency f ₁ of the received signal, as the oscillation frequency. Making; Converting the multi-phase voltage controlled oscillation signal of the second frequency f ₂ into a signal of a first frequency f ₁ ; Demodulating into a baseband by mixing the received signal with the first frequency signal; It provides a frequency conversion method frequency conversion method comprising the low-band filtering the demodulated signal to the base band.

Hereinafter, with reference to Figures 3 to 5 attached to the frequency converter and method according to the present invention will be described in detail.

3 is a circuit diagram illustrating a configuration of the frequency converter according to the first embodiment of the present invention. Referring to FIG. 3, the frequency converter according to the first embodiment of the present invention enters a demodulation step through band filtering and low noise amplification of the received RF signal. To this end, the circuit diagram shown in FIG. 3 is a diagram showing a six-phase voltage controlled oscillation circuit 301 and a frequency mixing circuit 302.

As a preferred embodiment of the six-phase voltage controlled oscillation circuit 301, a ring oscillator circuit in which cascaded amplifiers 303, 304, and 305 of three stages are connected can be used. The amplifiers 303, 304, and 305 of the oscillation circuit 301 generate a positive output signal and a negative output signal at each output terminal, and a six-phase voltage controlled oscillation signal generated at each output terminal. They have a phase difference of a predetermined magnitude Δ with each other.

The magnitude of the phase difference Δ according to the first embodiment of the present invention may be selected as Δ = 2π / 6. Also output from the six-phase oscillation circuit 301 Wow In between = L (3) , = L (4) , = L (5) Have a relationship of.

The six-phase frequency mixer 302 shown in FIG. 3 is a six-phase voltage controlled oscillation signal output from the six-phase voltage controlled oscillator 301 circuit. LO And A first embodiment of a circuit configuration method for demodulating a received RF signal into a base band using a as a clock signal is provided.

The six-phase frequency mixer 302 is a three-parallel combination circuit of two-input NAND gates consisting of transistors 310, 311, 312, 313, 314, 315, and 316 at the lower left of FIG. 3, and at the lower right of FIG. Three parallel combination circuits of two-input NAND gates composed of transistors 317, 318, 319, 320, 321, 322, and 323, and two pairs of differential amplifier circuits composed of transistors 324, 325, 326, and 327. Consists of.

A receiving RF signal is provided at the positive input terminal of the first differential amplifier composed of the transistors 324 and 325. Is applied, and the inverted RF signal is connected to the negative input terminal. Is applied.

In addition, the inverted RF signal is applied to the positive input terminal of the second differential amplifier including the transistors 326 and 327. Is applied, and the non-inverted RF signal is connected to the negative input terminal. Is applied. Subsequently, output stages of the first differential amplifiers 324 and 325 Is connected to the output terminal of the transistor 326 of the second differential amplifier, the output terminal of the second differential amplifier 326,327 Is connected to the output terminal of the transistor 325 of the first differential amplifier.

Meanwhile, the first signal conversion block including the transistors 310, 311, 312, 313, 314, 315, and 316 has a form in which two pairs of two-input NAND gate circuits are connected in a parallel manner, and each NAND gate The six-phase voltage controlled oscillation signal output from the six-phase voltage controlled oscillator 301 is input to the input terminal of the circuit as a clock.

According to a preferred embodiment of the present invention, an output signal of the six-phase voltage controlled oscillator 301 is input to the input of the first NAND gate including the transistors 310 and 311. LO (0) Wow Can be connected respectively. In addition, an output signal of the six-phase voltage controlled oscillator 301 is provided at input terminals of the second NAND gates 312 and 313 and the third NAND gates 314 and 315. LO (2) And LO (4) And Can be connected.

According to a preferred embodiment of the present invention, the second signal conversion block composed of the transistors 317, 318, 319, 320, 321, 322, and 323 connects two pairs of two input NAND gate circuits in a parallel manner to connect three pairs. The six-phase voltage controlled oscillation signal output from the six-phase voltage controlled oscillator 301 may be input to the clock in the same manner as the first signal conversion block described above.

According to a preferred embodiment of the present invention, the input signal of the fourth NAND gate including the transistors 318 and 319 is an output signal of the six-phase voltage controlled oscillator 301. LO (1) and And the inputs of the fifth NAND gates 320 and 321 and the sixth NAND gates 322 and 323, respectively. LO (3) And LO (5) And Can be connected.

Meanwhile, the bias current supply terminal 330 of the first differential amplifiers 324 and 325 is connected to the output LOT of the first signal conversion block through the bias current supply transistor 316 and the second differential amplifiers 326 and 327. The bias current supply terminal 331 of the output of the second signal conversion block through the bias current supply transistor 317 Is electrically connected to the

4 is a view showing waveforms of output signals of respective main parts of the frequency converter according to the first embodiment of the present invention. Referring to FIG. 4, the output signal of the six phase voltage controlled oscillator May both have a reception RF frequency f ₁ lower frequency than the frequency of f ₂ = f _1/3 that is, each of the oscillating signal may have a phase difference from each other by Δ.

In the frequency converter according to the first embodiment of the present invention, when the oscillation frequency f ₂ is moved to the low frequency band by 1/3 from the RF frequency f ₁ , the integrated frequency is integrated into a single chip using CMOS technology. CMOS transistors can eliminate switching speed limitations and phase noise issues.

Referring back to FIG. 4, an output signal obtained by clocking the output signals 401, 402, 403, 404, 405, and 406 of the six-phase voltage oscillator 301 to the six-phase frequency mixing circuit in the above-described manner, respectively. LOT 407 and The switching frequency of 408 is LO And It can be seen that the frequency is reduced to the frequency f ₁ again by three times the frequency of.

In other words, LO (0) Is HIGH LO (1) This LOW ( L (4) Is the same as when HIGH) LOT Becomes LOW Becomes HIGH. Also, LO (1) Is HIGH L (2) This LOW ( L (5) Is the same as when HIGH) LOT Becomes HIGH Becomes LOW. next, L (2) This HIGH LO (3) Is LOW ( L (0) Is the same as when HIGH) LOT Becomes LOW Becomes HIGH.

Also, LO (3) Is HIGH L (4) This LOW (i.e. LO (1) Is the same as when HIGH) LOT Becomes HIGH Becomes LOW. next, LO (4) Is HIGH LO (5) Is LOW ( LO (2) Is the same as when HIGH) LOT Becomes LOW Becomes HIGH. Finally, LO (5) Is HIGH LO (0) Is LOW (i.e. LO (3) Is HIGH), LOT Is HIGH Becomes LOW.

Thus, the frequency converter according to the first embodiment of the present invention, f ₂ = f ₁ / by 3 as the low-frequency switching of the gate circuit in sequence, the output waveform of the received RF signal and the f ₁ frequency (407, 408) the seungjeok A frequency mixing step is achieved.

5 is a diagram illustrating a frequency conversion device according to a second embodiment of the present invention. The second embodiment generalizes the above-described first embodiment to provide a multi-phase frequency conversion device having a phase difference of N steps. 5, the frequency converter according to the second embodiment of the present invention is composed of a multi-phase voltage controlled oscillator 501 and a frequency mixing circuit 502, the multi-phase voltage controlled oscillator circuit 501 A ring oscillator circuit is constructed in which the amplifiers 503, 504, 505 of the N stages are connected in a cascade manner.

The amplifiers at each stage of the multi-phase voltage controlled oscillator circuit 501 are positive and negative output signals. And Generates. Oscillation signal output from multi-phase voltage controlled oscillator circuit 501 LO And The oscillation frequency of has a frequency of f ₂ = 2 × f ₁ / N, which is a lower frequency band than the RF frequency f ₁ of the received signal. Also, as a preferred embodiment according to the present invention, a multi-phase voltage controlled oscillation signal LO And May have values of phase differences (Δ = 2π / N) of predetermined magnitudes from each other.

The multi-phase frequency mixer 502 shown in FIG. 5 is an N-phase voltage controlled oscillation signal output from the N-phase voltage controlled oscillator 501. LO And A circuit configuration method for demodulating a received RF signal into a baseband using a clock signal is provided.

The multiple (N) phase frequency mixer 502 has an N parallel combination circuit of two input NAND gates consisting of transistors 510, 511, 512, 513, 514, 515, 516 at the bottom left of FIG. 5 and the right of FIG. 5. N parallel combination circuit of two-input NAND gate composed of transistors 517, 518, 519, 520, 521, 522, 523 at the bottom, and two pairs of differential amplifiers composed of transistors 524, 525, 526, and 527. It consists of a circuit.

Receive RF signal at the positive input of the first differential amplifier composed of transistors 524 and 525. Is applied, and the inverted RF signal is connected to the negative input terminal. Is applied.

In addition, the inverted RF signal is applied to the positive input terminal of the second differential amplifier including the transistors 526 and 527. Is applied, and the non-inverted RF signal is connected to the negative input terminal. Is applied. Subsequently, output stages of the first differential amplifiers 524 and 525 Is connected to the output terminal of the transistor 526 of the second differential amplifier, the output terminal of the second differential amplifier 326,327 Is connected to the output terminal of the transistor 525 of the first differential amplifier.

Meanwhile, the first signal conversion block including the transistors 510, 511, 512, 513, 514, 515, and 516 has a form in which two pairs of two-input NAND gate circuits are connected in parallel, and each NAND gate is connected. The N phase voltage controlled oscillation signal output from the N phase voltage controlled oscillator 501 is input to the input terminal of the circuit as a clock.

According to a preferred embodiment of the present invention, the input of the first NAND gate including the transistors 510 and 511 is a signal of the N phase voltage controlled oscillator 501. LO (0) Wow Can be connected respectively. In addition, an output signal of the N-phase voltage controlled oscillator 501 is input to the input terminals of the second NAND gates 512 and 513 and the third NAND gates 514 and 515. LO (2) And LO (4) And Can be connected. Subsequently, an N-phase voltage oscillation signal of the above method is input to an input terminal of the N parallel NAND gate.

In a preferred embodiment according to the present invention, the second signal conversion block composed of transistors 517, 518, 519, 520, 521, 522, 523 is a method of connecting N pairs of two input NAND gate circuits in a parallel manner. The N phase voltage controlled oscillation signal output from the N phase voltage controlled oscillator 501 may be input to the clock in the same manner as the first signal conversion block described above.

In a preferred embodiment of the present invention, an input signal of the N-phase voltage controlled oscillator 501 is provided at an input of a fourth NAND gate including transistors 518 and 519. LO (1) and And the inputs of the fifth NAND gates 520 and 521 and the sixth NAND gates 522 and 523, respectively. LO (3) And LO (5) And Can be connected.

Meanwhile, the bias current supply terminal 530 of the first differential amplifiers 524 and 525 is connected to the output LOT of the first signal conversion block through the bias current supply transistor 516, and the second differential amplifiers 526 and 527. The bias current supply terminal 531 of the output of the second signal conversion block through the bias current supply transistor 517 Is electrically connected to the

The foregoing has outlined rather broadly the features and technical advantages of the present invention to better understand the claims of the invention which will be described later. Additional features and advantages that make up the claims of the present invention will be described below. It should be appreciated by those skilled in the art that the conception and specific embodiments of the invention disclosed may be readily used as a basis for designing or modifying other structures for carrying out similar purposes to the invention.

In addition, the inventive concepts and embodiments disclosed herein may be used by those skilled in the art as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. In addition, such modifications or altered equivalent structures by those skilled in the art may be variously changed, substituted, and changed without departing from the spirit or scope of the invention described in the claims.

As described above, the frequency converter according to the present invention is a structure that solves the problem of the conventional frequency converter, and the present invention uses a low frequency frequency obtained by dividing the received RF signal as an oscillation frequency, and selects a predetermined magnitude (Δ). Limiting switching speed and poor phase noise characteristics of CMOS transistors, which were the obstacles to integration into single chip using CMOS technology by frequency mixing the received RF signals using a multi-phase voltage controlled oscillation signal having a phase difference of Overcome

In addition, unlike the prior art, the frequency converter according to the present invention does not require the use of a suppression filter without an off chip virtual image, and provides a single PEL as CMOS technology, so that LO leakage or magnetic mixing ( There is an advantage that the DC offset does not occur by self-mixing.

Claims (20)

An apparatus for demodulating a baseband by receiving a radio signal having a first frequency f ₁ as an RF frequency, A plurality of N positive and negative values having an oscillation frequency of the second frequency f ₂ , which is lower than the first frequency f ₁ , and having a phase difference Δ of a predetermined magnitude. Signal generating means for generating a multi-phase voltage controlled oscillation signal of the; Frequency converting means for generating a signal of a first frequency f ₁ by sequentially switching at a clock cycle of a second frequency f _{2 with} a multi-phase voltage controlled oscillation signal generated by the signal generating means as an input; Frequency mixing means for multiplying the output signal of the frequency converting means and the received RF radio signal; Frequency conversion device comprising a. 2. The frequency converter of claim 1, wherein the second frequency (f ₂ ) has a relationship of f ₂ = (2 × f ₁ ) / N. The frequency converter of claim 1, wherein a phase difference Δ of the plurality of N output signals has a relationship of Δ = 2π / N. 2. The frequency mixing means of claim 1, wherein the RF signal is multiplied. A positive RF signal is applied to a positive input terminal, a negative RF signal is applied to a negative input terminal, and the bias current supply terminal is switched at the first frequency. A first differential amplifier which connects a positive output of the frequency converting means for generating an output signal; A negative RF signal is applied to a positive input terminal, a positive RF signal is applied to a negative input terminal, and a positive output terminal and the first differential are applied. Connecting the negative output terminal of the amplifier, connecting the negative output terminal and the positive output terminal of the first differential amplifier, and switching to the bias current supply terminal at the first frequency; Second differential amplifier connecting negative output of frequency converting means for generating output signal Frequency converter characterized in that it comprises a. According to claim 1, wherein the frequency conversion means for generating a signal of the first frequency (f ₁ ), Two NAND gates having two input stages are connected in parallel, and the positive and negative multi-phase voltage controlled oscillation signals generated by the signal generating means are alternately sequentially switched to the input terminals of the NAND gate. A first signal conversion circuit coupled to and outputting a positive first frequency f ₁ signal; NAND gates having two input terminals are connected in parallel with N / 2, and positive and negative delayed by a single phase (Δ) than the multi-phase voltage controlled oscillation signal input to the first signal conversion circuit at the NAND gate input terminal. A second signal conversion circuit for outputting a negative first frequency signal by alternately connecting the multi-phase voltage controlled oscillation signals of (iii) sequentially; Frequency converter characterized in that it comprises a. The signal generating means for generating a multi-phase voltage controlled oscillation signal has a ring oscillator type in which a plurality of (N) amplifiers are cascaded, and positive and negative from an output terminal of each amplifier. Outputs an oscillation signal of the second frequency f ₂ of (iii), and output stages of the successive amplifiers generate an oscillation signal having a phase difference by a predetermined phase difference? Device. 2. The frequency converter of claim 1, wherein the frequency converter further comprises a baseband signal processing means. 8. The frequency converter of claim 7, wherein the frequency converter is integrated into a single chip. A frequency conversion method for demodulating a received signal having a first frequency f ₁ as a carrier frequency into a base band, Receiving a signal having the first frequency f ₁ as a carrier frequency; A plurality of N multiphase voltage controlled oscillation signals each having a predetermined phase difference Δ are generated using the second frequency f ₂ , which is lower than the first frequency f ₁ of the received signal, as the oscillation frequency. Making; Converting the multi-phase voltage controlled oscillation signal of the second frequency f ₂ into a signal of a first frequency f ₁ ; Demodulating into a baseband by mixing the received signal with the first frequency signal; Low band filtering the demodulated signal into the base band Frequency conversion method comprising a. 10. The frequency conversion method according to claim 9, wherein the generating of the multi-phase voltage controlled oscillation signal sets a frequency band having a good noise characteristic and a good switching operation characteristic as the second frequency (f ₂ ). The method of claim 9, wherein the receiving of the signal having the first frequency f ₁ as a carrier frequency comprises: Filtering the received signal with a band pass filter; Amplifying the bandpass filter output using a low noise amplifier Frequency conversion method comprising a. The method of claim 9, wherein the generating of the multi-phase voltage controlled oscillation signal comprises: f ₂ = (between the oscillation frequency f ₂ , the carrier frequency f ₁ of the received signal, and the phase difference Δ. 2 × f ₁ ) / N = (2π / N) f ₁ × 1 / π = f ₁ × Δ × 1 / π. 10. The method of claim 9, wherein the generating of the oscillation signal at the multi-phase voltage comprises generating a plurality of N from the output of each stage of the multi-phase voltage controlled oscillator in the form of a ring oscillator composed of a multi-phase amplifier. And generating an oscillation signal sequentially having a phase difference Δ having a positive and negative second frequency f ₁ . The method of claim 9, wherein converting the multi-phase voltage controlled oscillation signal of the second frequency f ₂ into a signal of the first frequency f ₁ comprises switching at a speed of the second frequency f ₂ . Generating an output waveform of switching at a rate of the first frequency (f ₁ ) by sequentially applying a plurality of N multi-phase voltage controlled oscillation signals to the clock of the gate in turn. A frequency mixing device for demodulating a received signal having a first frequency f ₁ as a carrier frequency, A plurality of (N) positive multi-phase voltage controls having a second frequency f ₂ , which is lower than the first frequency f ₁ , as an oscillation frequency and having a phase difference Δ of a predetermined magnitude. Oscillation signal And negative multi-phase voltage controlled oscillation signals Signal generating means for generating a; Frequency mixing means for multiplying the signal of the first frequency f ₁ with the received signal by sequentially switching the multi-phase voltage controlled oscillation signal as a clock input at a clock cycle of a second frequency f ₂ . Frequency converter characterized in that it comprises a. The method of claim 15, wherein the frequency mixing means, Above input LO (0) And said The first NAND gate and the input terminal LO (2) And above Are respectively connected to the second NAND gate and the input terminal; LO (4) And above Are respectively connected to the third NAND gate and the input terminal sequentially LO (N-2) Wow A first block connecting the connected N / 2 NAND gates in parallel with each other; Above input LO (1) And said To the respective (N / 2 + 1) NAND gates and the input terminals LO (3) Wow Are respectively connected to the (N / 2 + 2) NAND gates and sequentially connected to the input terminal by the connection method. LO (N-1) and A second block in which N-th NAND gates connected to each other are connected in parallel with each other; Output of the first block A first differential amplifier connected to a bias current terminal and having a positive and a negative waveform of a received signal connected to an input terminal; Output of the second block Is connected to the bias current terminal, the positive and negative waveforms of the received signal are connected to the input terminal, and the output terminal of the first differential amplifier. Output at the negative input terminal of the first differential amplifier. Differential amplifier connected to positive input terminal Frequency converter characterized in that it comprises a. 16. A plurality of (N) positive multi-phase voltage controlled oscillation signals according to claim 15, wherein said signal generating means is generated. And negative multi-phase voltage controlled oscillation signals Wherein the phase difference Δ has a relationship of Δ = 2π / N. A frequency conversion method for demodulating a received signal having a first frequency f ₁ as a carrier frequency into a base band, Receiving a signal having the first frequency f ₁ as a carrier frequency; A plurality of positive multi-phase voltages each having a predetermined phase difference Δ, with a second frequency f _{2 that} is lower than the first frequency f ₁ of the received signal as an oscillation frequency. Controlled oscillation signal And negative multi-phase voltage controlled oscillation signals Generating a; Positive and negative output signals for switching from the gate circuit having the second frequency f ₂ to an optimum operating frequency band in the speed and noise characteristics to the first frequency f ₁ . Output signal of the gate circuit using a multi-phase voltage controlled oscillation signal of the second frequency f ₂ as a clock signal to generate? Demodulating the baseband by frequency-proliferation mixing with the received signal; Low band filtering the demodulated signal into the base band Frequency conversion method comprising a. 19. The method of claim 18, wherein the step of receiving a signal having the first frequency f ₁ as a carrier frequency, Filtering the received signal with a band pass filter; Amplifying the bandpass filter output using a low noise amplifier Frequency conversion method comprising a. 19. The method of claim 18, wherein the generating of the multi-phase voltage controlled oscillation signal comprises: f ₂ = (between the oscillation frequency f ₂ , the carrier frequency f ₁ of the received signal, and the phase difference Δ. A frequency conversion method characterized by having a relationship of 2 × f ₁ × Δ) / π.