CN103762948B - A kind of CMOS radio-frequency power amplifier being integrated in SOC(system on a chip) - Google Patents
A kind of CMOS radio-frequency power amplifier being integrated in SOC(system on a chip) Download PDFInfo
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- CN103762948B CN103762948B CN201310724049.7A CN201310724049A CN103762948B CN 103762948 B CN103762948 B CN 103762948B CN 201310724049 A CN201310724049 A CN 201310724049A CN 103762948 B CN103762948 B CN 103762948B
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Abstract
The present invention provides a kind of CMOS radio-frequency power amplifier being integrated in SOC(system on a chip), and described power amplifier is integrated in SOC(system on a chip) SOC, it is achieved the function that output signal power amplifies；Described power amplifier includes biasing circuit, first order amplifying circuit, second level amplifying circuit and output matching circuit.The power amplifier of the present invention uses CMOS technology to realize, and is integrated very well in SOC, controls and pulsewidth modulation (PWM) therefore, it is possible to single-chip realizes power；Compared with the power amplifier that conventional discrete component or III V compound semiconductor realize, it is adjustable that the power amplifier of the present invention has dual power, need not single external control chip, be greatly saved the cost of application system, the more convenient debugging of system；And it is adjustable that the power amplifier of the present invention has multiband output, in the multiple application in the range of can being widely used in from 10MHz to 1GHz.
Description
Technical field
The present invention relates to the multi-frequency band radio-frequency integrated circuit technique being applied in SOC, particularly relate to one and be integrated in SOC(system on a chip)
CMOS radio-frequency power amplifier.
Background technology
Radio-frequency power amplifier is positioned at the rear end of transmitter, for amplifying signal and reaching certain output.Both can be used in
In wireless communication system, the signal after modulation is amplified, drives antenna, it is achieved radio communication.Can be used in again in wired system,
Specific industrial control system, such as this power amplifier is driven just to can be applicable in wired industrial control system, driven for emitting lights etc.
Ion illuminator (LEP lamp controller).
Recently as developing rapidly of mobile communication and industrial control technology, more and more Circuits System are integrated into a chips
In, system-on-chip technology is more and more ripe.But conventional power amplifier core many employings Group III-V compound semiconductor system
Making, this power amplifier cost is high, it is difficult to be integrated together with traditional cmos process.And conventional power amplifier wants real
Existing power controls and modulation needs the second chip block and sheet external component to assist, and which adds complexity and the cost of system.
Traditional two stage power amplifier is as it is shown in figure 1, the common bank tube grid of power amplifier two-stage is directly connected to power supply and simply serves
The effect of high voltage protective, and along with the increasingly sophisticated of SOC system and the continuous expansion of function, this connected mode has been difficult to full
The system application that foot is increasingly sophisticated, such as this industrial control system requires to use PWM to control simultaneously and multiband width scope is defeated
Go out power control.Furthermore along with the output raising conventional power amplifier of operating temperature has as well as the rising of temperature
More serious loss.
Conventional power amplifier realize PWM control time, generally at the input of radiofrequency signal, by pwm control signal with
Radio-frequency input signals phase with, radio-frequency input signals is processed as the signal after PWM, is re-fed into power amplifier and puts
Greatly.But this implementation method can cause NM1 transistor transistor PWM is 0 when as shown in Figure 1 to turn off,
Thus PWM be from 0 to 1 when, transistor needs the long period stable from turning off to open, and PWM is believed
Number edge becomes round and smooth, limits switch speed.
Conventional power amplifier, when realizing power and controlling, generally uses MOS transistor or BJT transistor controls power to put
Big device drain voltage.On the one hand this power control mode uses additional sheet external component, waste PCB surface to amass and cost, the opposing party
Face, owing to power amplifier output electric current is very big, causes pressure drop huge on metal-oxide-semiconductor or BJT pipe, so from overall next
Say that the efficiency of power amplifier reduces a lot.
Summary of the invention
The shortcoming of prior art in view of the above, it is an object of the invention to provide a kind of CMOS being integrated in SOC(system on a chip) and penetrates
Frequently power amplifier, for solving that the structure of prior art intermediate power amplifier is complicated, cost of manufacture high, temperature influence is big,
The problems such as output is low.
For achieving the above object and other relevant purposes, the present invention provides a kind of CMOS radio-frequency power being integrated in SOC(system on a chip) to put
Big device, at least includes: biasing circuit, first order amplifying circuit and second level amplifying circuit, wherein:
What the current input terminal of described biasing circuit produced with band-gap reference circuit in SOC(system on a chip) connects with PTAT current
Connecing, two outfans connect with the first input end of described first order amplifying circuit and the first input end of second level amplifying circuit respectively
Connect, be used for providing bias voltage；
Second input of described first order amplifying circuit is connected with the phase-locked loop circuit in SOC(system on a chip), for input radio frequency signal；
3rd input is connected with the output of the micro-control unit in SOC(system on a chip), is used for inputting pulse-width signal；Four-input terminal with
Radio frequency ground connects；Outfan is connected with the second input of second level amplifying circuit and the first end of the first inductance；Described first electricity
Second end of sense connects power supply；
3rd input of described second level amplifying circuit is connected with the digital to analog converter in SOC(system on a chip), is used for controlling power amplification
The gain of device；Four-input terminal and the 5th input are connected with the micro-control unit of SOC(system on a chip), are respectively used to input SWN letter
Number and SWP signal, be used for controlling power amplifier gain control mode；6th input is connected with radio frequency ground；Outfan is with defeated
First end of the input and the second inductance that go out match circuit connects；Second end of described second inductance connects power supply.
As a kind of preferred version of the CMOS radio-frequency power amplifier being integrated in SOC(system on a chip) of the present invention, described biasing circuit
Its output is adjusted to described first order amplifying circuit and the bias voltage of second level amplifying circuit by digital control position.
As a kind of preferred version of the CMOS radio-frequency power amplifier being integrated in SOC(system on a chip) of the present invention, the described first order is put
Big circuit includes the first NMOS tube, the second NMOS tube, wherein:
The grid of described first NMOS tube is connected with described radiofrequency signal, and is connected for inputting biased electrical with described biasing circuit
Pressure；Source electrode is connected with radio frequency ground, and drain electrode is connected with the source electrode of described second NMOS tube；
The grid of described second NMOS tube is connected with pulse-width signal；Drain as outfan and described first inductance and described
Second level amplifying circuit connects.
Further, described first NMOS tube and the second NMOS tube constitute cascode structure, described first NMOS tube
For entering apparatus, described second NMOS tube is cascade device.
Further, described first order amplifying circuit also includes the first capacitance and the first biasing resistor, and described first every straight electricity
Appearance is connected between grid and the described radiofrequency signal of described first NMOS tube, and described first biasing resistor is connected to described first
Between grid and the described biasing circuit of NMOS tube.
As a kind of preferred version of the CMOS radio-frequency power amplifier being integrated in SOC(system on a chip) of the present invention, the described second level is put
Big circuit includes the 3rd NMOS tube, the 4th NMOS tube, the first PMOS, transmission gate NMOS tube, transmission gate PMOS
Pipe, RC circuit, wherein:
The drain electrode of described transmission gate NMOS tube is connected with the drain electrode of transmission gate PMOS, the source of described transmission gate NMOS tube
Pole is connected with the source electrode of transmission gate PMOS, forms transmission gate circuit；
The grid of described 3rd NMOS tube is connected with the outfan of described first order amplifying circuit, and is connected with described biasing circuit
For input offset voltage；Source electrode is connected with radio frequency ground, and drain electrode is connected with the source electrode of described 4th NMOS tube；
The grid of described 4th NMOS tube is by described RC circuit and described transmission gate NMOS tube and transmission gate PMOS
Drain electrode connect, drain electrode be connected with described second inductance and output matching circuit；The grid of described transmission gate NMOS tube connects
SWN signal, the grid of described transmission gate PMOS connects SWP signal, described transmission gate NMOS tube and transmission gate PMOS
The source electrode of pipe is connected with described digital to analog converter；
The grid of described first PMOS connects described SWN signal, drain electrode and described transmission gate NMOS tube and transmission gate
The drain electrode of PMOS is connected, and source electrode connects power supply.
Further, described 3rd NMOS tube and the 4th NMOS tube constitute cascode structure, described 3rd NMOS tube
For entering apparatus, described 4th NMOS tube is cascade device.
Further, described second level amplifying circuit also includes the second capacitance and the second biasing resistor, and described second every straight electricity
Appearance is connected between grid and the outfan of described first order amplifying circuit of described 3rd NMOS tube, described second biasing resistor
It is connected between grid and the described biasing circuit of described 3rd NMOS tube.
As a kind of preferred version of the CMOS radio-frequency power amplifier being integrated in SOC(system on a chip) of the present invention, each NMOS tube
And/or each PMOS is pressure not less than 5.5V.
As a kind of preferred version of the CMOS radio-frequency power amplifier being integrated in SOC(system on a chip) of the present invention, described in be integrated in sheet
The CMOS radio-frequency power amplifier of upper system uses CMOS technology to make.
As it has been described above, the present invention provides a kind of CMOS radio-frequency power amplifier being integrated in SOC(system on a chip), at least include: biasing
Circuit, first order amplifying circuit, second level amplifying circuit, output matching circuit, the first inductance and the second inductance, wherein: institute
The current input terminal stating biasing circuit is connected with PTAT current with what band-gap reference circuit in SOC(system on a chip) produced, and two
Individual outfan is connected with the first input end of described first order amplifying circuit and the first input end of second level amplifying circuit respectively, uses
In providing bias voltage；Second input of described first order amplifying circuit is connected with the phase-locked loop circuit in SOC(system on a chip), is used for
Input radio frequency signal；3rd input is connected with the output of the micro-control unit in SOC(system on a chip), is used for inputting pulse-width signal；
Four-input terminal is connected with radio frequency ground；Outfan is connected with the second input of second level amplifying circuit and the first end of the first inductance；
Second end of described first inductance connects power supply；3rd input of described second level amplifying circuit turns with the digital-to-analogue in SOC(system on a chip)
Parallel operation is connected, for controlling the gain of power amplifier；The micro-control unit of four-input terminal and the 5th input and SOC(system on a chip)
It is connected, is respectively used to input SWN signal and SWP signal, is used for controlling power amplifier gain control mode；6th input
Hold and be connected with radio frequency ground；Outfan is connected with the input of described output matching circuit and the first end of the second inductance；Described second
Second end of inductance connects power supply.The method have the advantages that
First, it is achieved that the pwm pulse width of single-chip and the double control mode of DAC amplitude, improve power amplifier
Efficiency.The power transistor of dual-stage amplifier of the present invention have employed cascode structure, and achieves MCU arteries and veins by RC network
Rush the double control mode of DAC amplitude on width (PWM) and sheet, it is achieved that the application in wired industrial control system, as
For driven for emitting lights plasma lighting system (LEP lamp controller) etc..
Second, it is achieved that the Digital Control of output, control to combine mode with the control of DAC amplitude by bias voltage,
It is capable of the widest power regulating range and fine efficiency optimization；The present invention bias voltage number to dual-stage amplifier
Word quantifies, and by digital control position from " 0000 " to the change of " 1111 ", controls the change of output；And by with SOC sheet
The amplitude of upper DAC controls to combine, it is possible to achieve power amplifier is carried out on output power range and work efficiency fine tune
Joint and optimum configuration.
3rd, it is achieved that the at high temperature power back-off of power amplifier；By introducing just becoming with absolute temperature in band-gap reference
The electric current (IPTAT) of ratio, creates the adjustable bias voltage with PTAT, biased electrical when the temperature increases
Pressure also raises with temperature, thus compensate at high temperature owing to device performance declines the power loss problem caused.
4th, described power amplifier is individually controllable with second level amplifier stage bias voltage due to first order amplifier stage, and radio frequency
Choke induction (L1, L2) and output matching circuit are adjustable in chip exterior, therefore can pass through Joint regulation according to using frequency range
The bias voltage of power amplifier and sheet external inductance and matching element, it is possible to achieve power amplifier is work in 10MHz～1GHz
Making, and typical output power reaches 24dBm, saturation power delivery efficiency reaches 60%.
Accompanying drawing explanation
Fig. 1 is shown as the electrical block diagram of tradition two-stage radio-frequency power amplifier.
Fig. 2 is shown as SOC(system on a chip) SOC that the CMOS radio-frequency power amplifier being integrated in SOC(system on a chip) of the present invention is used
Simplified block diagram.
Fig. 3 is shown as the structural representation of the CMOS radio-frequency power amplifier being integrated in SOC(system on a chip) of the present invention.
Fig. 4 is shown as the circuit knot of the CMOS radio-frequency power amplifier first order amplifying circuit being integrated in SOC(system on a chip) of the present invention
Composition.
Fig. 5 is shown as the circuit knot of the CMOS radio-frequency power amplifier second level amplifying circuit being integrated in SOC(system on a chip) of the present invention
Composition.
On the sheet of the CMOS radio-frequency power amplifier being integrated in SOC(system on a chip) that Fig. 6 is shown as the present invention, VDAC controls and passes
The EDA simulation result figure of system power amplifier sheet outer control.
Fig. 7 is shown as the CMOS radio-frequency power amplifier VPWM control signal being integrated in SOC(system on a chip) and the output of the present invention
The time domain EDA simulation result figure of power signal.
Element numbers explanation
10 biasing circuits
20 first order amplifying circuits
30 second level amplifying circuits
40 output matching circuits
L1 the first inductance
L2 the second inductance
NM1 the first NMOS tube
NM2 the second NMOS tube
NM3 the 3rd NMOS tube
NM4 the 4th NMOS tube
C1 the first capacitance
R1 the first biasing resistor
C2 the second capacitance
R2 the second biasing resistor
NM5 transmission gate NMOS tube
PM5 transmission gate PMOS
PM1 the first PMOS
Detailed description of the invention
Below by way of specific instantiation, embodiments of the present invention being described, those skilled in the art can be by disclosed by this specification
Content understand other advantages and effect of the present invention easily.The present invention can also be added by the most different detailed description of the invention
To implement or application, the every details in this specification can also be based on different viewpoints and application, in the essence without departing from the present invention
Various modification or change is carried out under god.
Refer to Fig. 2～Fig. 7.It should be noted that the diagram provided in the present embodiment illustrates the present invention's the most in a schematic way
Basic conception, the most graphic in component count time only display with relevant assembly in the present invention rather than is implemented according to reality, shape and
Size is drawn, and during its actual enforcement, the kenel of each assembly, quantity and ratio can be a kind of random change, and its assembly layout type
State is likely to increasingly complex.
The structure of SOC(system on a chip) SOC of the present invention is as in figure 2 it is shown, described SOC(system on a chip) SOC includes: microcontroller list
Unit MCU, band-gap reference circuit BG, digital to analog converter DAC, power module DCDC, phase-locked loop circuit PLL and power
Amplifier PA.
As shown in Fig. 3～Fig. 7, the present embodiment provides a kind of CMOS radio-frequency power amplifier being integrated in SOC(system on a chip), at least wraps
Include: biasing circuit 10, first order amplifying circuit 20 and second level amplifying circuit 30, wherein:
In the current input terminal of described biasing circuit 10 and SOC(system on a chip) band-gap reference circuit BG produce and PTAT
Electric current IPTAT connects, two outfans respectively with first input end and the second level amplifying circuit of described first order amplifying circuit 20
The first input end of 30 connects, and is used for providing bias voltage VGS1 and VGS2.
The electric current IBIAS of the input of described biasing circuit 10 be in SOC band-gap reference circuit BG produce become with absolute temperature
Direct ratio electric current IPTAT, therefore at high temperature can make up power amplifier gain with bigger bias current and reduce.
As shown in Figure 4, the second input of described first order amplifying circuit 20 and the phase-locked loop circuit PLL phase in SOC(system on a chip)
Even, for input radio frequency signal RFIN1；3rd input is connected with the output of the micro-control unit MCU in SOC(system on a chip),
For inputting pulse-width modulation PWM signal；Four-input terminal is connected DRVGND with radio frequency ground；Outfan output DRVOUT
Signal is connected, for input radio frequency signal with the second input of second level amplifying circuit 30 and first end of the first inductance L1
RFIN2；Second end of described first inductance L2 connects power supply；
Specifically, described first order amplifying circuit 20 includes the first NMOS tube NM1, the second NMOS tube NM2, described
First NMOS tube NM1 and the second NMOS tube NM2 constitute cascode structure, and the first NMOS tube NM1 is input
Device, the second NMOS tube NM2 is cascade device, wherein:
The grid of described first NMOS tube NM1 is connected with described radiofrequency signal, and is connected for defeated with described biasing circuit 10
Enter bias voltage；Source electrode is connected with radio frequency ground, and drain electrode is connected with the source electrode of described second NMOS tube NM2；
The grid of described second NMOS tube NM2 is connected with pulse-width signal；Drain as outfan and described first inductance
Connect with described second level amplifying circuit 30.
Further, described first order amplifying circuit 20 also includes the first capacitance C1 and the first biasing resistor R1, described
One capacitance C1 is connected between grid and the described radiofrequency signal of described first NMOS tube NM1, described first biasing
Resistance R1 is connected between grid and the described biasing circuit 10 of described first NMOS tube NM1.
It addition, in the present embodiment, each element of described first order amplifying circuit 20 can use CMOS technology to be integrated in sheet
In upper system SOC, and, described first NMOS tube NM1, the pressure of the second NMOS tube NM2 are not less than 5.5V.
As it is shown in figure 5, the 3rd input of described second level amplifying circuit is connected with the digital to analog converter DAC in SOC(system on a chip),
For inputting VDAC signal, to control the gain of power amplifier；Four-input terminal and the 5th input are micro-with SOC(system on a chip)
Control unit is connected, and is respectively used to input SWN signal and SWP signal, is used for controlling power amplifier gain control mode,
It is embodied in: the transmission gate conducting when SWP signal is low level, and SWN signal is high level, now can be turned by digital-to-analogue
Parallel operation DAC controls the gain of power amplifier；6th input is connected with radio frequency ground GNDPA；Outfan and output matching
The input of circuit 40 and the first end of the second inductance connect, and are used for exporting PAOUT signal；The of described second inductance L2
Two ends connect power supply.
Specifically, described second level amplifying circuit 30 include the 3rd NMOS tube NM3, the 4th NMOS tube NM4, first
PMOS PM1, transmission gate NMOS tube NM5, transmission gate PMOS PM5, RC circuit, described 3rd NMOS
Pipe NM3 and the 4th NMOS tube NM4 constitute cascode structure, and described 3rd NMOS tube NM3 is input pipe, described
4th NMOS tube NM4 is cascade device, wherein:
The drain electrode of described transmission gate NMOS tube NM5 is connected with the drain electrode of transmission gate PMOS PM5, described transmission gate
The source electrode of NMOS tube NM5 is connected with the source electrode of transmission gate PMOS PM5, forms transmission gate circuit；
The grid of described 3rd NMOS tube NM3 is connected with the outfan of described first order amplifying circuit 20, and with described biasing
Circuit 10 is connected for input offset voltage；Source electrode is connected with radio frequency ground, drain electrode and the source electrode of described 4th NMOS tube NM4
It is connected；
The grid of described 4th NMOS tube NM4 is by described RC circuit and described transmission gate NMOS tube NM5 and transmission
The drain electrode of door PMOS PM5 connects, and drain electrode is connected with described second inductance and described output matching circuit；Described transmission gate
The grid of NMOS tube NM5 connects SWN signal, and the grid of described transmission gate PMOS PM5 connects SWP signal,
The source electrode of described transmission gate NMOS tube NM5 and transmission gate PMOS PM5 is connected with described digital to analog converter；
The grid of described first PMOS PM1 connects described SWN signal, drain electrode and described transmission gate NMOS tube NM5
And the drain electrode of transmission gate PMOS PM5 is connected, source electrode connects power supply.
Further, described second level amplifying circuit 30 also includes the second capacitance C2 and the second biasing resistor R2, described
Two capacitance C2 be connected to the grid of described 3rd NMOS tube NM3 and described first order amplifying circuit 20 outfan it
Between, described second biasing resistor R2 is connected between grid and the described biasing circuit 10 of described 3rd NMOS tube NM3.
It addition, in the present embodiment, each element of described second level amplifying circuit 30 can use CMOS technology to be integrated in sheet
In upper system SOC, and, described 3rd NMOS tube NM3, the 4th NMOS tube NM4, the first PMOS PM1,
Transmission gate NMOS tube NM5 and the pressure of transmission gate PMOS PM5 are not less than 5.5V.
The biasing circuit 10 of described power amplifier adjusts its output to described first order amplifying circuit 20 by digital control position
And the bias voltage of second level amplifying circuit 30, when digital control position is from 0000～1111, power output is corresponding from low to high,
When digital control position is from 1111～0000, then power output is corresponding from high to low.
By first order amplifying circuit 20 and the numeral of second level amplifying circuit 30 of the bias voltage of combinatorially varying power amplifier
Control bit (VGS1_CONTROL<3:0>, VGS2_CONTROL<3:0>), it is possible to achieve output is in a big way
Interior control.When power amplifier two-stage biasing control bit is set to " 0000 ", power amplifier output minimum power；Work as merit
When rate amplifier two-stage biasing control bit is set to " 1111 ", power amplifier Maximum Power Output.Described first order amplifying circuit
20 and second level amplifying circuit 30 bias control bit and can be respectively provided with the requirement meeting output, according to different application
Require that optimal design-aside control bit can reach high efficiency application.And the electric current producing bias voltage comes from band gap on sheet
Adjustable electric current (IPTAT) with PTAT that benchmark provides, so compensated in high temperature is applied due to
The output that temperature causes reduces problem.First order amplifying circuit 20 and second level amplifying circuit 30 bias control bit and have ten
Six kinds of states, as shown in the table.
| Sequence | VGS1_CONTROL<3:0> | VGS2_CONTROL<3:0> |
| 1 | 0000 | 0000 |
| 2 | 0001 | 0001 |
| 3 | 0010 | 0010 |
| 4 | 0011 | 0011 |
| 5 | 0100 | 0100 |
| 6 | 0101 | 0101 |
| 7 | 0110 | 0110 |
| 8 | 0111 | 0111 |
| 9 | 1000 | 1000 |
| 10 | 1001 | 1001 |
| 11 | 1010 | 1010 |
| 12 | 1011 | 1011 |
| 13 | 1100 | 1100 |
| 14 | 1101 | 1101 |
| 15 | 1110 | 1110 |
| 16 | 1111 | 1111 |
The VDAC signal of the second level amplifying circuit 30 of described power amplifier, by with the digital to analog converter in SOC system
DAC is connected, and regulates the output of digital to analog converter DAC through feedback mechanism and is connected to the 4th NMOS tube by RC circuit
NM4 controls output.Fig. 6 show VDAC on the power amplifier sheet of the present invention and controls and conventional power amplifier
The EDA simulation result of sheet outer control.By simulation result it can be seen that on sheet the output amplitude of DAC defeated to power amplifier
Go out power and can carry out wide range of regulation, and the output degree of regulation of power amplifier is as carrying of DAC precision
High and improve.Its efficiency of the most traditional power control mode is significantly lower than the control mode of the present invention.
Micro-with SOC(system on a chip) SOC of the second NMOS tube NM2 in the first order amplifying circuit 20 of described power amplifier
The output of control unit MCU is connected, for inputting the PWM pulsewidth modulation that in SOC(system on a chip), micro-control unit MCU produces
Signal, to realize the PWM of output signal.Fig. 7 show PWM pulse-width signal and output signal
Time-domain-simulation waveform.It will be seen that PWM pulse width signal is by controlling described first order amplifying circuit 20 from simulation waveform
In the second NMOS tube NM2, can quickly on off state switch.
The power control principle of the CMOS radio-frequency power amplifier being integrated in SOC(system on a chip) of the present embodiment is as follows:
First, control and compensate power transistor (the first NMOS tube NM1 and the 3rd NMOS tube NM3) bias voltage
Size: as it is shown on figure 3, by changing described first order amplifying circuit 20 and the bias voltage VGS1 of second level amplifying circuit 30
And VGS2, to control the first NMOS tube NM1 and the working direct current of the 3rd NMOS tube NM3, thus change
The gain of power amplifier two-stage so that power amplifier output power is adjustable.Conventional power amplifier is deposited at high temperature power and is damaged
The problem lost, caused by the hydraulic performance decline of at high temperature device.The present invention introduces and definitely temperature in biasing circuit 10
Spend the band-gap reference electric current of be directly proportional (PTAT) so that compensate at high temperature along with the liter high bias voltage of temperature improves the most accordingly
The power dissipation concerns of lower power amplifier.
Second, the grid voltage dutycycle of the second NMOS tube NM2 of the first order amplifying circuit 20 of control power amplifier:
As shown in Figure 4, the PWM modulation signal of the output of the micro-control unit MCU in SOC(system on a chip) is by the with power amplifier
Second NMOS tube NM2 of one-level amplifying circuit 20 is connected the PWM realizing power amplifier output.Power amplification
Second NMOS tube NM2 of the first order amplifying circuit 20 of device realizes this modulation by turning on and off.With tradition PWM
Modulating the radiofrequency signal to input to be controlled comparing, this power amplifier realizes the method for PWM control owing to simply changing
The grid voltage of the second NMOS tube NM2, is also equivalent to switch the drain voltage of the first NMOS tube NM1, the most permissible
Realization is switched fast.And this PWM implementation need not add more logic on radio frequency link, simplifies circuit
Structure, enhances reliability.Fig. 7 show the time-domain-simulation waveform of pwm signal VPWM and output signal.
3rd, control the grid voltage amplitude of the 4th NMOS tube NM4 of the second level amplifying circuit 30 of power amplifier: as
Shown in Fig. 5, the second level that the output of the digital to analog converter DAC of SOC(system on a chip) is connected to power amplifier by RC circuit is amplified
The grid of the 4th NMOS tube NM4 of circuit 30.By controlling the 4th NMOS tube NM4 of second level amplifying circuit 30
Impedance realize the control of output.Fig. 6 is shown as VDAC on the power amplifier sheet of the present invention and controls and conventional power
The EDA simulation result of amplifier sheet outer control.From the point of view of simulation result, sheet, the control of output is presented non-linear by DAC,
The duty of this non-linear process and the 4th NMOS tube NM4 is correlated with, because the 4th NMOS tube NM4 is at a letter
The change from linear zone to saturation region is experienced by number cycle.This control mode improves along with the precision of DAC, power amplifier
Output can reach very high accuracy and the widest range of accommodation.Its efficiency of the most traditional power control mode is bright
The aobvious control mode less than the present invention.
Being used alone bias voltage control or DAC amplitude controls, the amplitude of variation of output and the efficiency of power amplifier are excellent
All can be limited in change.In conjunction with the two so that power amplifier has bigger power regulating range, power can also be put simultaneously
The efficiency of big device carries out optimal settings.Use two-stage structure for amplifying, not only solve the problem that input signal driving force is not enough,
Also achieve the double control mode that PWM controls and DAC amplitude controls simultaneously.Compared with traditional power control techniques, use
This power amplifier control mode can simplify sheet external component, reduces PCB surface and amasss, and can realize in the controlling efficiently
Rate and the advantage of wide tuning range.
As it has been described above, the present invention provides a kind of CMOS radio-frequency power amplifier being integrated in SOC(system on a chip), at least include: biasing
Circuit 10, first order amplifying circuit 20, second level amplifying circuit 30, output matching circuit the 40, first inductance and the second inductance,
Wherein: it is electric with PTAT that the current input terminal of described biasing circuit 10 produces with band-gap reference circuit in SOC(system on a chip)
Stream connects, two outfans respectively with the of the first input end of described first order amplifying circuit 20 and second level amplifying circuit 30
One input connects, and is used for providing bias voltage；Second input of described first order amplifying circuit 20 and the lock in SOC(system on a chip)
Phase loop circuit is connected, for input radio frequency signal；3rd input is connected with the output of the micro-control unit in SOC(system on a chip), uses
In input pulse-width signal；Four-input terminal is connected with radio frequency ground；Outfan and the second input of second level amplifying circuit 30
And first inductance the first end be connected；Second end of described first inductance connects power supply；The 3rd of described second level amplifying circuit is defeated
Enter end to be connected with the digital to analog converter in SOC(system on a chip), for controlling the gain of power amplifier；Four-input terminal and the 5th input
End is connected with the micro-control unit of SOC(system on a chip), is respectively used to input SWN signal and SWP signal, is used for controlling power amplification
Device gain control mode；6th input is connected with radio frequency ground；Outfan and the input and second of described output matching circuit 40
First end of inductance connects；Second end of described second inductance connects power supply.The method have the advantages that
First, it is achieved that the pwm pulse width of single-chip and the double control mode of DAC amplitude, improve power amplifier
Efficiency.The power transistor of dual-stage amplifier of the present invention have employed cascode structure, and achieves MCU arteries and veins by RC network
Rush the double control mode of DAC amplitude on width (PWM) and sheet, it is achieved that the application in wired industrial control system, as
For driven for emitting lights plasma lighting system (LEP lamp controller) etc..
Second, it is achieved that the Digital Control of output, control to combine mode with the control of DAC amplitude by bias voltage,
It is capable of the widest power regulating range and fine efficiency optimization；The present invention bias voltage number to dual-stage amplifier
Word quantifies, and by digital control position from " 0000 " to the change of " 1111 ", controls the change of output；And by with SOC sheet
The amplitude of upper DAC controls to combine, it is possible to achieve power amplifier is carried out on output power range and work efficiency fine tune
Joint and optimum configuration.
3rd, it is achieved that the at high temperature power back-off of power amplifier；By introducing just becoming with absolute temperature in band-gap reference
The electric current (IPTAT) of ratio, creates the adjustable bias voltage with PTAT, biased electrical when the temperature increases
Pressure also raises with temperature, thus compensate at high temperature owing to device performance declines the power loss problem caused.
4th, described power amplifier is individually controllable with second level amplifier stage bias voltage due to first order amplifier stage, and radio frequency
Choke induction (L1, L2) and output matching circuit are adjustable in chip exterior, therefore can pass through Joint regulation according to using frequency range
The bias voltage of power amplifier and sheet external inductance and matching element, it is possible to achieve power amplifier is work in 10MHz～1GHz
Making, and typical output power reaches 24dBm, saturation power delivery efficiency reaches 60%.So, the present invention effectively overcomes
Various shortcoming of the prior art and have high industrial utilization.
The principle of above-described embodiment only illustrative present invention and effect thereof, not for limiting the present invention.Any it is familiar with this skill
Above-described embodiment all can be modified under the spirit and the scope of the present invention or change by the personage of art.Therefore, such as
All that in art, tool usually intellectual is completed under without departing from disclosed spirit and technological thought etc.
Effect is modified or changes, and must be contained by the claim of the present invention.
Claims (10)
1. the CMOS radio-frequency power amplifier being integrated in SOC(system on a chip), it is characterised in that at least include: biasing circuit,
One-level amplifying circuit and second level amplifying circuit, wherein:
It is electric with PTAT that the current input terminal of described biasing circuit produces with band-gap reference circuit in SOC(system on a chip)
Stream connects, and two outfans are defeated with the first of the first input end of described first order amplifying circuit and second level amplifying circuit respectively
Enter end to connect, be used for providing bias voltage；
Second input of described first order amplifying circuit is connected with the phase-locked loop circuit in SOC(system on a chip), for input radio frequency
Signal；3rd input is connected with the output of the micro-control unit in SOC(system on a chip), is used for inputting pulse-width signal；4th
Input is connected with radio frequency ground；Outfan is connected with the second input of second level amplifying circuit and the first end of the first inductance；
Second end of described first inductance connects power supply；
3rd input of described second level amplifying circuit is connected with the digital to analog converter in SOC(system on a chip), is used for controlling power
The gain of amplifier；Four-input terminal and the 5th input are connected with the micro-control unit of SOC(system on a chip), are respectively used to input
SWN signal and SWP signal, be used for controlling power amplifier gain control mode；6th input is connected with radio frequency ground；
Outfan is connected with the input of output matching circuit and the first end of the second inductance；Second end of described second inductance connects electricity
Source.
The CMOS radio-frequency power amplifier being integrated in SOC(system on a chip) the most according to claim 1, it is characterised in that: described partially
Circuits adjusts its output to described first order amplifying circuit and the biased electrical of second level amplifying circuit by digital control position
Pressure.
The CMOS radio-frequency power amplifier being integrated in SOC(system on a chip) the most according to claim 1, it is characterised in that: described
One-level amplifying circuit includes the first NMOS tube, the second NMOS tube, wherein:
The grid of described first NMOS tube is connected with described radiofrequency signal, and is connected with described biasing circuit for inputting partially
Put voltage；Source electrode is connected with radio frequency ground, and drain electrode is connected with the source electrode of described second NMOS tube；
The grid of described second NMOS tube is connected with pulse-width signal；Drain as outfan and described first inductance and
Described second level amplifying circuit connects.
The CMOS radio-frequency power amplifier being integrated in SOC(system on a chip) the most according to claim 3, it is characterised in that: described
One NMOS tube and the second NMOS tube constitute cascode structure, and described first NMOS tube is entering apparatus, described
Second NMOS tube is cascade device.
The CMOS radio-frequency power amplifier being integrated in SOC(system on a chip) the most according to claim 3, it is characterised in that: described
One-level amplifying circuit also includes that the first capacitance and the first biasing resistor, described first capacitance are connected to described first
Between grid and the described radiofrequency signal of NMOS tube, described first biasing resistor is connected to the grid of described first NMOS tube
Between pole and described biasing circuit.
The CMOS radio-frequency power amplifier being integrated in SOC(system on a chip) the most according to claim 1, it is characterised in that: described
Second amplifying circuit include the 3rd NMOS tube, the 4th NMOS tube, the first PMOS, transmission gate NMOS tube,
Transmission gate PMOS, RC circuit, wherein:
The drain electrode of described transmission gate NMOS tube is connected with the drain electrode of transmission gate PMOS, described transmission gate NMOS tube
Source electrode be connected with the source electrode of transmission gate PMOS, formed transmission gate circuit；
The grid of described 3rd NMOS tube is connected with the outfan of described first order amplifying circuit, and with described biasing circuit
It is connected for input offset voltage；Source electrode is connected with radio frequency ground, and drain electrode is connected with the source electrode of described 4th NMOS tube；
The grid of described 4th NMOS tube is by described RC circuit and described transmission gate NMOS tube and transmission gate PMOS
The drain electrode of pipe connects, and drain electrode is connected with described second inductance and described output matching circuit；Described transmission gate NMOS tube
Grid connects SWN signal, and the grid of described transmission gate PMOS connects SWP signal, described transmission gate NMOS tube
And the source electrode of transmission gate PMOS is connected with described digital to analog converter；
The grid of described first PMOS connects described SWN signal, drain electrode and described transmission gate NMOS tube and transmission
The drain electrode of door PMOS is connected, and source electrode connects power supply.
The CMOS radio-frequency power amplifier being integrated in SOC(system on a chip) the most according to claim 6, it is characterised in that: described
Three NMOS tube and the 4th NMOS tube constitute cascode structure, and described 3rd NMOS tube is input pipe, and described the
Four NMOS tube are cascade device.
The CMOS radio-frequency power amplifier being integrated in SOC(system on a chip) the most according to claim 6, it is characterised in that: described
Second amplifying circuit also includes that the second capacitance and the second biasing resistor, described second capacitance are connected to the described 3rd
Between grid and the outfan of described first order amplifying circuit of NMOS tube, described second biasing resistor is connected to the described 3rd
Between grid and the described biasing circuit of NMOS tube.
9., according to the CMOS radio-frequency power amplifier being integrated in SOC(system on a chip) described in claim 3～8 any one, its feature exists
Pressure not less than 5.5V in: each NMOS tube and/or each PMOS.
10., according to the CMOS radio-frequency power amplifier being integrated in SOC(system on a chip) described in claim 1～8 any one, it is special
Levy and be: described in be integrated in SOC(system on a chip) CMOS radio-frequency power amplifier use CMOS technology make.
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| CN106055008B (en) * | 2016-06-15 | 2019-01-11 | 泰凌微电子（上海）有限公司 | Current biasing circuit and the method for improving positive temperature coefficient |
| CN107086879A (en) * | 2017-02-27 | 2017-08-22 | 宇龙计算机通信科技(深圳)有限公司 | Adjustable RF circuit, communication terminal and adjustable RF circuit control method |
| CN108462476B (en) * | 2018-02-08 | 2022-04-12 | 芯原微电子(上海)股份有限公司 | Power amplifier and power control method thereof |
| CN108155880B (en) * | 2018-02-22 | 2021-08-13 | 北京遥感设备研究所 | Programmable millimeter wave digital power amplifier |
| CN113162564B (en) * | 2021-03-25 | 2023-05-26 | 成都知融科技有限公司 | CMOS power amplifier with temperature compensation function on chip |
| CN115549703B (en) * | 2022-10-09 | 2024-06-18 | 芯翼信息科技(上海)有限公司 | Transmitter and transceiver integrated with CMOS power amplifier |
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Denomination of invention: Complementary metal-oxide-semiconductor transistor (CMOS) radio frequency power amplifier integrated on system on chip Effective date of registration: 20170929 Granted publication date: 20160928 Pledgee: National integrated circuit industry investment fund, Limited by Share Ltd Pledgor: VeriSilicon Holdings Co., Ltd.|VeriSilicon Microelectronics (Shanghai) Co., Ltd.|VERISILICON MICROELECTRONICS (CHENGDU) CO., LTD.|VeriSilicon Microelectronics (Beijing) Co., Ltd. Registration number: 2017990000922 |
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Address after: Zhangjiang Building 20A, 289 Chunxiao Road, China (Shanghai) Free Trade Pilot Area, Pudong New Area, Shanghai Co-patentee after: VeriSilicon Microelectronics (Beijing) Co., Ltd. Patentee after: Xinyuan Microelectronics (Shanghai) Co., Ltd. Co-patentee after: VERISILICON MICROELECTRONICS (CHENGDU) CO., LTD. Co-patentee after: Core holdings limited company Address before: 201203 Zhangjiang Building 20A, 560 Songtao Road, Zhangjiang High-tech Park, Pudong New Area, Shanghai Co-patentee before: VeriSilicon Microelectronics (Beijing) Co., Ltd. Patentee before: VeriSilicon Microelectronics (Shanghai) Co., Ltd. Co-patentee before: VERISILICON MICROELECTRONICS (CHENGDU) CO., LTD. Co-patentee before: VeriSilicon Holdings Co., Ltd. |