CN115499603B - Reading circuit with image mirroring function and infrared thermal imager - Google Patents

Reading circuit with image mirroring function and infrared thermal imager Download PDF

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Publication number
CN115499603B
CN115499603B CN202211462855.7A CN202211462855A CN115499603B CN 115499603 B CN115499603 B CN 115499603B CN 202211462855 A CN202211462855 A CN 202211462855A CN 115499603 B CN115499603 B CN 115499603B
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input
column
trigger
row
input end
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CN115499603A (en
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李建
骆柏华
倪慧云
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Kunming Thorium Crystal Technology Co ltd
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Kunming Thorium Crystal Technology Co ltd
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/30—Transforming light or analogous information into electric information
    • H04N5/33—Transforming infrared radiation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/04—Synchronising
    • H04N5/06—Generation of synchronising signals

Abstract

The invention provides a reading circuit with an image mirroring function and an infrared thermal imager. The readout circuit includes: the MXN input stage unit circuit array is used for receiving photosensitive current of the infrared focal plane detector and converting the photosensitive current into a voltage signal; the M-bit row shift register has a bidirectional transmission function and comprises M six-input row triggers, and the reading direction is selected according to a row shift direction control signal; the N-bit column shift register has a bidirectional transmission function and comprises N six-input column triggers, and the reading direction is selected according to a column shift direction control signal; and the sampling and holding circuit is used for sequentially receiving voltage signals output by the M multiplied by N input stage unit circuit array which controls the reading direction according to the M-bit row shift register and the N-bit column shift register and performing serial reading. According to the invention, the application field of the infrared focal plane detector assembly can be expanded, and the debugging difficulty, the development cost and the development time of a subsequent infrared thermal imager are reduced.

Description

Reading circuit with image mirroring function and infrared thermal imager
Technical Field
The invention belongs to the technical field of infrared thermal imaging, and particularly relates to a reading circuit with an image mirroring function and an infrared thermal imager.
Background
The infrared focal plane detector assembly is an important photoelectric device for acquiring infrared thermal radiation information of a target scene and is an important component of an infrared thermal imager. The core component of the infrared focal plane detector assembly is an infrared focal plane detector chip set. The infrared Focal Plane detector chip set is formed by flip-chip interconnection of an infrared Focal Plane Array (FPA) chip and a readout circuit chip through indium columns. The basic function of the readout circuit chip is to perform pre-amplification processing on the electrical signals converted by each pixel of the infrared detector array chip, and then serially read out through one or more output buffers (also called multiplexers).
A typical reading circuit mainly comprises an M multiplied by N input stage unit circuit array, a column stage sampling-holding circuit, a row and column stage shift register, an output amplification stage and the like. The readout circuit, which has both analog and digital circuit portions, is typically a digital/analog hybrid Application Specific Integrated Circuit (ASIC).
In an actual application environment of an infrared thermal imaging system, an infrared video image is required to be subjected to mirror image turning in a horizontal direction or a vertical direction according to different application requirements. According to the requirement of mirror image turning in the horizontal or vertical direction, a corresponding image processing program needs to be re-developed to realize the mirror image turning in the horizontal or vertical direction of the infrared video image, so that the practical application requirement of the infrared thermal imaging system is met. The conventional reading circuit has difficulty in realizing mirror inversion of images by changing the circuit structure.
Disclosure of Invention
In order to solve the above problems, the present invention provides a readout circuit with an image mirroring function and an infrared thermal imager, wherein the image mirroring and flipping function in the horizontal or vertical direction of an infrared video image is realized through a control signal on the readout circuit with the image mirroring function.
In a first aspect of the present invention, there is provided a readout circuit having an image mirroring function, comprising: the circuit comprises an M multiplied by N input stage unit circuit array, an M bit row shift register, an N bit column shift register and a sampling and holding circuit;
wherein the content of the first and second substances,
m and N are both positive integers greater than 2;
the MXN input stage unit circuit array is used for receiving photosensitive current of the infrared focal plane detector and converting the photosensitive current into a voltage signal;
the M-bit row shift register has a bidirectional transmission function, comprises M six-input-row flip-flops, is connected to the MXN input-stage unit circuit array, and selects a reading direction according to a row shift direction control signal;
the N-bit column shift register has a bidirectional transmission function, comprises N six-input column triggers and is connected to the MXN input stage unit circuit array through a sampling and holding circuit, and the N-bit column shift register selects a reading direction according to a column shift direction control signal;
and the sampling and holding circuit is used for sequentially receiving the voltage signals output by the M multiplied by N input stage unit circuit array read according to the reading direction of the M-bit row shift register and the N-bit column shift register and performing serial output.
According to an embodiment of the present invention, the M-bit row shift register includes a row complementary clock generator for generating a first row clock signal and a second row clock signal according to an input row clock signal, wherein the first row clock signal is associated with a rising edge of the input row clock signal, and the second row clock signal is associated with a falling edge of the input row clock signal.
According to an embodiment of the invention, the M six-input row flip-flops comprise a first six-input row flip-flop, a second six-input row flip-flop …, an ith six-input row flip-flop …, an Mth six-input row flip-flop, wherein i is an integer and 1<i < M,
the first input end of the first six-input line trigger is connected with a line synchronization signal, the second input end of the first six-input line trigger is connected with the output end of the second six-input line trigger, the third input end of the first six-input line trigger is connected with a line shift direction control signal, the fourth input end of the first six-input line trigger is connected with the first line clock signal, the fifth input end of the first six-input line trigger is connected with the second line clock signal, the sixth input end of the first six-input line trigger is connected with a reset signal, and the output end of the first six-input line trigger is connected with the first input end of the second six-input line trigger;
the first input end of the ith sixth input row trigger is connected with the output end of the (i-1) th six input row trigger, the second input end of the ith sixth input row trigger is connected with the output end of the (i + 1) th six input row trigger, the third input end of the ith sixth input row trigger is connected with a row shifting direction control signal, the fourth input end of the ith sixth input row trigger is connected with the first row clock signal, the fifth input end of the ith sixth input row trigger is connected with the second row clock signal, the sixth input end of the ith sixth input row trigger is connected with a reset signal, and the output end of the ith sixth input row trigger is connected with the first input end of the (i + 1) th input row trigger and the second input end of the (i-1) th input row trigger;
the first input end of the Mth six-input-line trigger is connected with the output end of the M-1 th six-input-line trigger, the second input end of the Mth six-input-line trigger is connected with a line synchronization signal, the third input end of the Mth six-input-line trigger is connected with a line shift direction control signal, the fourth input end of the Mth six-input-line trigger is connected with the first line clock signal, the fifth input end of the Mth six-input-line trigger is connected with the second line clock signal, the sixth input end of the Mth six-input-line trigger is connected with a reset signal, and the output end of the Mth six-input-line trigger is connected with the second input end of the M-1 th six-input-line trigger.
According to an embodiment of the invention, any one of the M six-input row flip-flops comprises:
the first transmission gate, the second transmission gate, the first inverter and the first trigger;
the input end of the first transmission gate is a first input end of the six-input line trigger, the positive control end of the first transmission gate is a third input end of the six-input line trigger, the input end of the first phase inverter is a third input end of the six-input line trigger, and the negative control end of the first transmission gate is an output end of the first phase inverter;
the input end of the second transmission gate is the second input end of the six-input row trigger, the positive control end of the second transmission gate is the output end of the first phase inverter, and the negative control end of the second transmission gate is the third input end of the six-input row trigger;
and the output ends of the first transmission gate and the second transmission gate input signals to the input end of the first trigger according to the row displacement direction control signal of the third input end.
According to the embodiment of the invention, the first trigger comprises a first NMOS transistor, a second inverter, a third inverter, a first PMOS transistor, a first NOR gate circuit,
when the first row clock signal is at a high level, the first NMOS tube is switched on, and the first PMOS tube is switched off;
the output end of the first NMOS tube is connected with the input end of the second phase inverter, the output end of the second inverter and the sixth input end of the six-input row trigger are connected with the input end of a first NOR gate circuit, and the output end of the first NOR gate circuit is connected with the input end of the first PMOS tube;
when the first row clock signal is at a low level, the first PMOS tube is switched on, and the first NMOS tube is switched off so as to latch the output signal of the second phase inverter;
when the second row clock signal is at a high level, the second NMOS transistor is turned on, an output signal of the second inverter is transmitted to the third inverter, and an output end of the third inverter is an output end of the six-input-row flip-flop.
According to an embodiment of the invention, the N-bit column shift register comprises a column complementary clock generator for generating a first column clock signal and a second column clock signal from an input column clock signal, wherein the first column clock signal is associated with a rising edge of the input column clock signal and the second column clock signal is associated with a falling edge of the input column clock signal.
According to an embodiment of the invention, the N six-input column flip-flops comprise a first six-input column flip-flop, a second six-input column flip-flop … jth sixth-input column flip-flop … nth-input column flip-flop, where j is an integer and 1<j < N,
the first input end of the first six-input column trigger is connected with a column synchronization signal, the second input end of the first six-input column trigger is connected with the output end of the second six-input column trigger, the third input end of the first six-input column trigger is connected with a column shift direction control signal, the fourth input end of the first six-input column trigger is connected with the first column clock signal, the fifth input end of the first six-input column trigger is connected with the second column clock signal, the sixth input end of the first six-input column trigger is connected with a reset signal, and the output end of the first six-input column trigger is connected with the first input end of the second six-input column trigger;
the first input end of the jth sixth input column trigger is connected with the output end of the jth-1 sixth input column trigger, the second input end of the jth +1 sixth input column trigger is connected with the output end of the jth +1 sixth input column trigger, the third input end of the jth input column trigger is connected with a column shift direction control signal, the fourth input end of the jth input column trigger is connected with the first column clock signal, the fifth input end of the jth input column trigger is connected with the second column clock signal, the sixth input end of the jth input column trigger is connected with a reset signal, and the output end of the jth +1 sixth input column trigger is connected with the first input end of the jth +1 sixth input column trigger and the second input end of the jth-1 sixth input column trigger;
the first input end of the Nth six-input column trigger is connected with the output end of the N-1 th six-input column trigger, the second input end of the Nth six-input column trigger is connected with the column synchronous signal, the third input end of the Nth six-input column trigger is connected with the column shift direction control signal, the fourth input end of the Nth six-input column trigger is connected with the first column clock signal, the fifth input end of the Nth six-input column trigger is connected with the second column clock signal, the sixth input end of the Nth six-input column trigger is connected with the reset signal, and the output end of the Nth six-input column trigger is connected with the second input end of the N-1 th six-input column trigger.
According to an embodiment of the present invention, any one of the N six-input column flip-flops comprises:
the first transmission gate, the second transmission gate, the third inverter and the fourth flip-flop are connected;
the input end of the third transmission gate is the first input end of the six-input-row flip-flop, the positive control end of the third transmission gate is the third input end of the six-input-row flip-flop, the input end of the fourth inverter is the third input end of the six-input-row flip-flop, and the negative control end of the third transmission gate is the output end of the fourth inverter;
the input end of the fourth transmission gate is the second input end of the six-input-row flip-flop, the positive control end of the fourth transmission gate is the output end of the fourth inverter, and the negative control end of the fourth transmission gate is the third input end of the six-input-row flip-flop;
and the output ends of the third transmission gate and the fourth transmission gate input signals to the input end of the second trigger according to the column shift direction control signal of the third input end.
According to the embodiment of the invention, the second flip-flop comprises a third NMOS transistor, a fourth NMOS transistor, a fifth inverter, a sixth inverter, a second PMOS transistor, and a second NOR gate circuit,
when the first column clock signal is at a high level, the third NMOS tube is switched on, and the second PMOS tube is switched off;
the output end of the third NMOS tube is connected with the input end of a fifth inverter, the output end of the fifth inverter and the sixth input end of the six-input column trigger are connected with the input end of a second NOR gate circuit, and the output end of the second NOR gate circuit is connected with the input end of the second PMOS tube;
when the first column clock signal is at a low level, the second PMOS tube is switched on, and the third NMOS tube is switched off so as to latch an output signal of the fifth inverter;
when the second column clock signal is at a high level, the fourth NMOS transistor is turned on, an output signal of the fifth inverter is transmitted to the sixth inverter, and an output end of the sixth inverter is an output end of the six-input column flip-flop.
In a second aspect of the present invention, there is provided an infrared thermal imager comprising: the infrared focal plane detector and the reading circuit with the image mirror function.
The reading circuit with the image mirroring function provided by the invention realizes the reading of the MXN input stage unit circuit array from top to bottom or from bottom to top by configuring the row shifting direction control signal, thereby realizing the function of turning the MXN infrared video image into an up/down mirror image (namely longitudinal mirroring); by configuring the column shift direction control signal, the M multiplied by N input stage unit circuit array is read from left to right or from right to left, so that the M multiplied by N infrared video image is subjected to a left/right mirror image (namely, transverse mirror image) overturning function. The infrared thermal imager using the reading circuit with the image mirroring function realizes the infrared video image mirroring turning function, thereby expanding the application field of the infrared focal plane detector assembly and reducing the development difficulty, debugging difficulty, development cost and development time of the subsequent infrared thermal imager.
Furthermore, the six-input trigger (comprising a six-input row trigger and a six-input column trigger) is controlled by a pair of complementary non-overlapping clocks, and the trigger with the bidirectional transmission function can be realized by adopting a very small number of transistors. The unique bidirectional transmission function ensures that the reading circuit can realize the horizontal/vertical mirror function; the synchronous reset function of the circuit ensures that the reading circuit can realize the fixed-point windowing (not less than 2 multiplied by 2), the two non-complementary clocks are adopted to avoid the interference problem and the competition hazard phenomenon which are easily caused when the reading circuit is controlled by the same clock signal, and the accuracy of the pulse signal control is improved.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
FIG. 1 is a schematic diagram of a readout circuit with image mirroring function according to the present invention;
FIG. 2 is a schematic diagram of a complementary clock generator provided by the present invention;
FIG. 3 is a schematic diagram of a circuit structure of an M-bit line shift register according to the present invention;
FIG. 4 is a schematic diagram of a circuit structure of a six-input row/column flip-flop provided in the present invention;
FIG. 5 is a schematic circuit diagram of an N-bit column shift register according to the present invention;
FIGS. 6 and 7 are schematic diagrams of waveforms illustrating the operation of the M-bit line shift register according to the present invention;
FIGS. 8 and 9 are schematic diagrams of waveforms for operating the N-bit column shift register according to the present invention;
fig. 10 is a schematic diagram of the operation of the readout circuit with image mirroring function according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Fig. 1 is a schematic diagram of a readout circuit with an image mirroring function according to the present invention. Referring to fig. 1, it can be seen that the readout circuit with an image mirroring function includes: the circuit comprises an MXN input stage unit circuit array, an M-bit row shift register, an N-bit column shift register and a sampling and holding circuit; the M multiplied by N input stage unit circuit array is used for receiving photosensitive current of the infrared focal plane detector and converting the photosensitive current into a voltage signal; m and N are both positive integers greater than 2; the M-bit row shift register has a bidirectional transmission function, comprises M six-input row flip-flops and is connected to the MXN input stage unit circuit array, and selects a reading direction according to a row shift direction control signal; the N-bit column shift register has a bidirectional transmission function, comprises N six-input column triggers and is connected to the MXN input stage unit circuit array through a sampling and holding circuit, and the N-bit column shift register selects a reading direction according to a column shift direction control signal; the sampling and holding circuit is used for sequentially receiving voltage signals output by the M multiplied by N input stage unit circuit array read according to the reading direction of the M-bit row shift register and the N-bit column shift register and performing serial reading.
According to the embodiment of the invention, the readout circuit with the image mirroring function is used for reading the voltage signals of each unit in an array, wherein the voltage signals of each unit are M × N (M and N are both positive integers) pixel units, namely pixels (the pixels comprise a detector Det) on an infrared focal plane detector array chip, and the photosensitive current signals of the pixel units are converted into integrated voltage signals by the mxn input stage unit circuit (the unit circuit comprises an integrated capacitor C _ INT which is used for providing the integrated voltage signals).
According to the embodiment of the present invention, the M-bit Row shift register has a bidirectional transfer function, and can select a reading direction based on a Row shift direction control signal, that is, a reading direction for reading signals in a Row direction in the M × N input stage unit circuit array Row By Row (Row By Row).
According to the embodiments of the present invention, the N-bit column shift register has a bidirectional transfer function, and can select a reading direction based on a column shift direction control signal, that is, a reading direction in which column-by-column (Line by Line) reading is performed for signals in a column direction in the M × N input stage unit circuit array.
According to the embodiment of the invention, the M-bit row shift register and the sampling and holding circuit are connected with the M multiplied by N input stage unit circuit array, and the N-bit column shift register is connected with the M multiplied by N input stage unit circuit array through the sampling and holding circuit.
According to the embodiment of the present invention, signals can be read into the sample and hold circuit according to the read direction of the above M-bit row shift register and N-bit column shift register, and the signals sampled and held in the sample and hold circuit are serially transmitted to the output port of the readout circuit through one or more output buffers.
Fig. 2 is a schematic diagram of a complementary clock generator provided in the present invention, and as shown in fig. 2, the M-bit row shift register includes a row complementary clock generator for generating a first row clock signal and a second row clock signal according to an input row clock signal, wherein the first row clock signal is associated with a rising edge of the input row clock signal, and the second row clock signal is associated with a falling edge of the input row clock signal.
According to an embodiment of the present invention, the Row clock signal CLK _ Row is input to an input terminal of the Row complementary clock generator TCK _ GEN, the first Row clock signal CK1 and the second Row clock signal CK2 are available from an output terminal of the Row complementary clock generator, and the first Row clock signal CK1 is triggered at a rising edge of the Row clock signal CLK and the second Row clock signal CK2 is triggered at a falling edge of the Row clock signal CLK.
Fig. 3 is a schematic circuit diagram of the M-bit row shift register provided in the present invention, in which a six-input row flip-flop SRDFF is represented by a symbol. As can be seen in fig. 3, the M-bit row shift register includes a row complementary clock generator TCK _ GEN, M six-input row flip-flops SRDFF: the first six-input row flip-flop SRDFF <1>, …, the ith six-input row flip-flop SRDFF < I >, … and the Mth six-input row flip-flop SRDFF < M >, I are integers, and 1-I-M.
The first input end IN1 of the first six-input Row trigger SRDFF <1> is connected with a Row synchronizing signal SS _ Row, the second input end IN2 is connected with the output end R <2> of the second six-input Row trigger, the third input end DR is connected with a Row shifting direction control signal DR _ Row, the fourth input end CLK1 is connected with the first Row clock signal CK1, the fifth input end CLK2 is connected with the second Row clock signal CK2, the sixth input end Reset is connected with a Reset signal Reset _ Row, and the output end OUT is connected with the first input end R <1> of the second six-input Row trigger.
The first input end IN1 of the ith sixth input Row flip-flop SRDFF < i > is connected with the output end R < i-1> of the ith-1 sixth input Row flip-flop, the second input end IN2 is connected with the output end R < i +1> of the ith +1 sixth input Row flip-flop, the third input end DR is connected with a Row displacement direction control signal DR _ Row, the fourth input end CLK1 is connected with the first Row clock signal CK1, the fifth input end CLK2 is connected with the second Row clock signal CK2, the sixth input end Reset is connected with a Reset signal Reset _ Row, the output end OUT is connected with the first input end R < i > of the ith +1 sixth input Row flip-flop and the second input end R < i > of the ith-1 sixth input Row flip-flop.
The first input end IN1 of the Mth six-input Row trigger SRDFF < M > is connected with the output end R < M-1> of the Mth-1 sixth-input Row trigger, the second input end IN2 is connected with a Row synchronizing signal SS _ Row, the third input end DR is connected with a Row shifting direction control signal DR _ Row, the fourth input end CLK1 is connected with the first Row clock signal CK1, the fifth input end CLK2 is connected with the second Row clock signal CK2, the sixth input end Reset is connected with a Reset signal Reset _ Row, and the output end OUT is connected with the second input end R < M > of the Mth-1 sixth-input Row trigger.
Fig. 4 is a schematic circuit diagram of a six-input row/column flip-flop provided in the present invention, wherein any one of the M six-input row flip-flops includes: a first transmission gate TG1, a second transmission gate TG2, a first inverter INV1, and a first flip-flop FF1; the input end of the first transmission gate TG1 is a first input end IN1 of the six-input-row trigger, the positive control end of the first transmission gate is a third input end DR of the six-input-row trigger, the input end of the first phase inverter is the third input end DR of the six-input-row trigger, and the negative control end of the first transmission gate is the output end of the first phase inverter; the input end of the second transmission gate is a second input end IN2 of the six-input line trigger, the positive control end of the second transmission gate is the output end of the first phase inverter, and the negative control end of the second transmission gate is a third input end DR of the six-input line trigger; the output ends of the first and second transmission gates input signals to the input end of the first flip-flop according to the Row shift direction control signal DR _ Row of the third input end DR.
According to an embodiment of the invention, said first flip-flop is denoted with the symbol FF 1. As shown in fig. 4, the first flip-flop FF1 includes a first NMOS transistor MN1, a second NMOS transistor MN2, a second inverter INV2, a third inverter INV3, a first PMOS transistor MP1, and a first NOR gate circuit NOR1.
The first NMOS transistor MN1 and the first PMOS transistor are controlled by the first clock signal CK1, that is, the first NMOS transistor MN1 and the first PMOS transistor are connected to the fourth input terminal CLK 1. When the first row clock signal is at a high level, the first NMOS tube is conducted, and the first PMOS tube is disconnected.
The output end of the first NMOS transistor MN1 is connected with the input end of a second inverter INV2, the output end of the second inverter INV2 and a sixth input end reset of the six-input row trigger are connected to the input end of a first NOR gate circuit, and the output end of the first NOR gate circuit is connected with the input end of the first PMOS transistor;
when the first row clock signal is at a low level, the first PMOS transistor MP1 is turned on, and the first NMOS transistor MN1 is turned off, so as to latch an output signal of the second inverter INV 2; in this case, if the input signal of the first flip-flop is at a high level, it is converted into a low level signal by the action of the second inverter INV2, and is converted into a high level signal again by the processing of the first NOR gate NOR1, and is converted into a low level signal again by the processing of the second inverter INV2, that is, the latch of the output signal of the second inverter INV2 is realized. Until the second row clock signal goes high.
According to the embodiment of the invention, the second NMOS transistor MN2 is controlled by the second clock signal CK2, i.e., the second NMOS transistor MN2 is connected to the fifth input terminal CLK 2. When the second row clock signal is at a high level, the second NMOS transistor MN2 is turned on, an output signal of the second inverter INV2 is transmitted to the third inverter INV3, and an output end of the third inverter INV3 is an output end OUT of the six-input row flip-flop. That is, the signal is converted into the same signal as the input signal of the first flip-flop by the action of the third inverter INV3 again.
According to an embodiment of the present invention, the first flip-flop may further include a third PMOS transistor MP3 respectively connected to the output terminal OUT, the power supply VDD, and the output terminal of the second NMOS transistor MN2, and configured to turn on the third inverter INV3 and the power supply VDD when the third inverter INV3 does not output a high level.
By the method, the input and the output of the first trigger are respectively controlled by the two clock signals, so that the interference problem and the competition hazard phenomenon easily caused by the control of the same clock signal are avoided, and the accuracy of the control of the pulse signal is improved.
Fig. 5 is a schematic circuit diagram of an N-bit column shift register according to the present invention, in which a six-input column D flip-flop QCDFF is represented by a symbol. As can be seen from fig. 5, the N-bit column shift register includes N six-input column flip-flops QCDFF: first six-input column flip-flops QCDFF <1>, …, jth sixth-input column D flip-flops QCDFF < J >, …, nth-sixth-input column flip-flops QCDFF < N >, (J is an integer and is made of 1J or N). And, the N-bit column shift register includes a column complementary clock generator TCK _ GEN for generating a first column clock signal CK1 and a second column clock signal CK2 according to an input column clock signal CK _ Col, wherein the first column clock signal CK1 is associated with a rising edge of the input column clock signal CK _ Col, and the second column clock signal CK2 is associated with a falling edge of the input column clock signal CK _ Col. The first column clock signal CK1 is triggered at the rising edge of the column clock signal CK _ Col, and the second column clock signal CK2 is triggered at the falling edge of the clock signal CK _ Col.
The first input terminal IN1 of the first six-input column flip-flop QCDFF <1> is connected with the column synchronization signal SS _ Col, the second input terminal IN2 is connected with the output terminal C <2> of the second six-input column flip-flop QCDFF <2>, the third input terminal DR is connected with the column shift direction control signal DR _ Col, the fourth input terminal CLK1 is connected with the first column clock signal CK1, the fifth input terminal CLK2 is connected with the second column clock signal CK2, the sixth input terminal Reset is connected with the Reset signal Reset _ Col, and the output terminal OUT is connected with the first input terminal C <1> of the second six-input column flip-flop.
The first input terminal IN1 of the jth sixth input column flip-flop QCDFF < j > is connected with the output terminal C < j-1> of the jth-1 sixth input column flip-flop QCDFF < j-1>, the second input terminal IN2 is connected with the output terminal C < j +1> of the jth +1 sixth input column flip-flop QCDFF < j +1>, the third input terminal DR is connected with the column shift direction control signal DR _ Col, the fourth input terminal CLK1 is connected with the first column clock signal CK1, the fifth input terminal CLK2 is connected with the second column clock signal CK2, the sixth input terminal Reset is connected with the Reset signal Reset _ Col, the output terminal OUT is connected with the first input terminal C < j > of the jth +1 sixth input column flip-flop, and the second input terminal C < j > of the jth-1 sixth input column flip-flop.
The first input end IN1 of the Nth six-input column trigger QCDFF < N > is connected with the output end C < N-1> of the N-1 th six-input column trigger QCDFF < N-1>, the second input end IN2 is connected with the column synchronization signal SS _ Col, the third input end DR is connected with the column shift direction control signal DR _ Col, the fourth input end CLK1 is connected with the first column clock signal CK1, the fifth input end CLK2 is connected with the second column clock signal CK2, the sixth input end Reset is connected with the Reset signal Reset _ Col, and the output end OUT is connected with the second input end C < N > of the N-1 th six-input column trigger.
According to an embodiment of the present invention, the circuit structure of the six-input column flip-flop and the above six-input row flip-flop may be the same. Any one of the N six-input column flip-flops comprises: a third transmission gate TG3, a fourth transmission gate TG4, a fourth inverter INV4, and a second flip-flop FF2; an input end of the third transmission gate TG3 is a first input end IN1 of the six-input-column flip-flop, a positive control end of the third transmission gate TG3 is a third input end DR of the six-input-column flip-flop, an input end of the fourth inverter INV4 is a third input end DR of the six-input-column flip-flop, and a negative control end of the third transmission gate is an output end of the fourth inverter INV 4; an input end of the fourth transmission gate TG4 is a second input end IN2 of the six-input column flip-flop, a positive control end of the fourth transmission gate TG4 is an output end of the fourth inverter INV4, and a negative control end of the fourth transmission gate TG4 is a third input end DR of the six-input column flip-flop; the output terminals of the third and fourth transmission gates TG3 and TG4 input signals to the input terminal of the second flip-flop according to the column shift direction control signal DR _ Col of the third input terminal DR.
According to an embodiment of the invention, said second flip-flop is denoted with the symbol FF 2. As can be seen from fig. 4, the second flip-flop includes a third NMOS transistor MN3, a fourth NMOS transistor MN4, a fifth inverter INV5, a sixth inverter INV6, a second PMOS transistor MP2, and a second NOR gate NOR2, where when the first column clock signal is at a high level, the third NMOS transistor MN3 is turned on, and the second PMOS transistor MP2 is turned off; the output end of the third NMOS transistor MN3 is connected to the input end of a fifth inverter INV5, the output end of the fifth inverter INV5 and the sixth input end of the six-input column flip-flop are connected to the input end of a second NOR gate circuit NOR2, and the output end of the second NOR gate circuit NOR2 is connected to the input end of the second PMOS transistor MP 2; when the first column clock signal is at a low level, the second PMOS transistor MP2 is turned on, and the third NMOS transistor MN3 is turned off, so as to latch an output signal of the fifth inverter INV 5; when the second column clock signal is at a high level, the fourth NMOS transistor MN4 is turned on, an output signal of the fifth inverter INV5 is transmitted to the sixth inverter INV6, and an output end of the sixth inverter INV6 is an output end of the six-input column flip-flop. The second flip-flop may further include a fourth PMOS transistor MP4 respectively connected to the output terminal, the power supply, and the output terminal of the fourth NMOS transistor, and configured to turn on the sixth inverter and the power supply when the sixth inverter does not output a high level.
Fig. 6 and fig. 7 are schematic diagrams of operating waveforms of the M-bit row shift register according to the present invention. Referring to fig. 3, 6 and 7, the operating principle of the M-bit line shift register is as follows: the M-bit line shift register adopts M six-input line flip-flops SRDFF, wherein each six-input line flip-flop SRDFF has two data input ports IN1 and IN2, and the line shift direction control signal DR _ Row controls whether the data received by the six-input line flip-flop SRDFF < i > comes from the last SRDFF (namely the six-input line flip-flop SRDFF < i-1 >) or the next SRDFF (namely the six-input line flip-flop SRDFF < i +1 >); the Row synchronization signal SS _ Row is respectively connected with a data input port IN1 of a first SRDFF (namely, a first six-input Row trigger SRDFF <1 >) and a data input port IN2 of an Mth SRDFF (namely, an Mth six-input Row trigger SRDFF < M >), under the control of a Row shift direction control signal DR _ Row, M +1 Row clock signals CK _ Row are sent, so that M-bit Row shift registers sequentially output M signals from R <1> to R < M > (or from R < M > to R <1 >), and a read switch of an M multiplied by N input stage unit circuit array is sequentially opened, thereby transferring an integral signal Row by Row (Roby Row) to a sampling and holding circuit of a column-level processor. As is apparent from fig. 6 and 7, when DR _ Row =1, the M-bit line shift register sequentially outputs M read signals in total from R <1> to R < M >, and when DR _ Row =0, the M-bit line shift register sequentially outputs M read signals in total from R < M > to R <1>.
Fig. 8 and 9 are schematic diagrams of operating waveforms of the N-bit column shift register according to the present invention. Referring to fig. 5, 8 and 9, the operating principle of the N-bit column shift register is as follows: the N-bit column shift register adopts N six-input column triggers QCDFF, wherein each six-input column trigger QCDFF has two data input ports IN1 and IN2, and the column shift direction control signal DR _ Col controls whether the data received by the six-input column trigger QCDFF < j > comes from the left QCDFF (namely the six-input column trigger SRDFF < j-1 >) or the right QCDFF (namely the six-input column D trigger SRDFF < j +1 >); the Column synchronization signal SS _ Col is respectively connected to the data input port IN1 of the first QCDFF (i.e., the first six-input Column flip-flop SRDFF <1 >) and the data input port IN2 of the Nth QCDFF (i.e., the Nth six-input Column flip-flop SRDFF < N >), and N +1 Column clock signals are transmitted under the operation of the Column shift direction control signal DR _ Col, so that the N-bit Column shift register sequentially outputs N signals IN total from C <1> to C < N > (or from C < N > to C <1 >), and the sampling and holding circuit readout switch of the Column level processor is sequentially opened, thereby serially transmitting the sampling and holding signals Column by Column (Column) to the readout circuit chip output port through one or more output buffers. As is apparent from fig. 8 and 9, when DR _ Col =1, the N-bit column shift register sequentially outputs N read signals in total of C <1> to C < N >, and when DR _ Col =0, the N-bit row shift register sequentially outputs N read signals in total of C < N > to C <1>.
In summary, the row shift direction control signal controls the M-bit row shift register to read signals in the M × N input stage cell circuit array from bottom to top or from top to bottom, and the column shift direction control signal controls the N-bit column shift register to read signals in the M × N input stage cell circuit array from left to right or from right to left. Accordingly, the reading order of signals in the M × N input stage cell circuit array can be commonly controlled based on the row shift direction control signal and the column shift direction control signal.
Fig. 10 is a schematic diagram of the operation of the readout circuit with image mirroring function according to the present invention. Referring to fig. 10, the operation principle of the readout circuit with image mirroring function is as follows: let pixel (0,0) = (row 1, column 1), …, pixel (M, N) = (row M, column N), each pixel position is given with respect to the direction of the entire readout circuit (i.e., X and Y directions in fig. 10), and let Z be the center point of an M × N array (i.e., an M × N input stage unit circuit array). Definition of Point A (R) A ；C A ) Is the first corner of the M x N array, corresponding to pixel (0,0); point B (R) B ；C B ) Is a second corner of the M x N array, symmetrical to the first corner about Z, corresponding to the pixel (M, N), and, similarly, the point (R) A ；C B ) Corresponding to pixel (0,N), point (R) B ；C A ) Corresponding to picture element (M, 0). Wherein point A is near the mask mark (1,1) on the read circuit layout and near the pin on the package shell of the infrared focal plane detector assembly.
The control words DR _ Row and DR _ Col are input signals that determine the M × N array address reading direction. DR _ Row determines the Row readout direction, DR _ Col determines the column readout direction, and M-bit Row shift register and N-bit column shift register control the M × N array transmission as shown in table 1:
TABLE 1M XN array mirror flip function control
Figure 315223DEST_PATH_IMAGE001
In summary, the present invention provides a readout circuit for image flipping of an infrared video image, which realizes up/down image and left/right image readout of an mxn infrared pixel array.
The invention also provides an infrared thermal imager, comprising: the infrared focal plane detector and the reading circuit with the image mirror image function. The infrared thermal imager with the reading circuit with the image mirroring function can realize the horizontal/vertical mirroring turning function of the infrared video image, thereby expanding the application field of the infrared thermal imager and reducing the development difficulty, debugging difficulty, development cost and development time of a subsequent infrared focal plane thermal imaging system.
Although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.

Claims (6)

1. A readout circuit having an image mirroring function, comprising: the circuit comprises an MXN input stage unit circuit array, an M-bit row shift register, an N-bit column shift register and a sampling and holding circuit;
wherein the content of the first and second substances,
m and N are both positive integers greater than 2;
the MXN input stage unit circuit array is used for receiving photosensitive current of the infrared focal plane detector and converting the photosensitive current into a voltage signal;
the M-bit row shift register has a bidirectional transmission function, comprises M six-input-row flip-flops, is connected to the MXN input-stage unit circuit array, and selects a reading direction according to a row shift direction control signal;
the N-bit column shift register has a bidirectional transmission function, comprises N six-input column triggers and is connected to the MXN input stage unit circuit array through a sampling and holding circuit, and the N-bit column shift register selects a reading direction according to a column shift direction control signal;
the sampling and holding circuit is used for sequentially receiving voltage signals output by the M multiplied by N input stage unit circuit array read according to the reading direction of the M-bit row shift register and the N-bit column shift register and performing serial reading;
the M-bit line shift register includes a line complement clock generator for generating a first line clock signal and a second line clock signal according to an input line clock signal, wherein the first line clock signal is associated with a rising edge of the input line clock signal, and the second line clock signal is associated with a falling edge of the input line clock signal;
the M six-input row flip-flops comprise a first six-input row flip-flop, a second six-input row flip-flop …, an ith six-input row flip-flop …, an Mth six-input row flip-flop, wherein i is an integer and 1<i < M,
the first input end of the first six-input line trigger is connected with a line synchronization signal, the second input end of the first six-input line trigger is connected with the output end of the second six-input line trigger, the third input end of the first six-input line trigger is connected with a line shift direction control signal, the fourth input end of the first six-input line trigger is connected with the first line clock signal, the fifth input end of the first six-input line trigger is connected with the second line clock signal, the sixth input end of the first six-input line trigger is connected with a reset signal, and the output end of the first six-input line trigger is connected with the first input end of the second six-input line trigger;
the first input end of the ith sixth input row trigger is connected with the output end of the (i-1) th six input row trigger, the second input end of the ith sixth input row trigger is connected with the output end of the (i + 1) th six input row trigger, the third input end of the ith sixth input row trigger is connected with a row shifting direction control signal, the fourth input end of the ith sixth input row trigger is connected with the first row clock signal, the fifth input end of the ith sixth input row trigger is connected with the second row clock signal, the sixth input end of the ith sixth input row trigger is connected with a reset signal, and the output end of the ith sixth input row trigger is connected with the first input end of the (i + 1) th input row trigger and the second input end of the (i-1) th input row trigger;
the first input end of the Mth six-input-row trigger is connected with the output end of the M-1 th six-input-row trigger, the second input end of the Mth six-input-row trigger is connected with a row synchronizing signal, the third input end of the Mth six-input-row trigger is connected with a row shifting direction control signal, the fourth input end of the Mth six-input-row trigger is connected with the first row clock signal, the fifth input end of the Mth six-input-row trigger is connected with the second row clock signal, the sixth input end of the Mth six-input-row trigger is connected with a reset signal, and the output end of the Mth six-input-row trigger is connected with the second input end of the M-1 th six-input-row trigger;
any one of the M six-input line flip-flops comprises:
the first transmission gate, the second transmission gate, the first inverter and the first trigger;
the input end of the first transmission gate is the first input end of the six-input row trigger, the positive control end of the first transmission gate is the third input end of the six-input row trigger, the input end of the first phase inverter is the third input end of the six-input row trigger, and the negative control end of the first transmission gate is the output end of the first phase inverter;
the input end of the second transmission gate is the second input end of the six-input row trigger, the positive control end of the second transmission gate is the output end of the first phase inverter, and the negative control end of the second transmission gate is the third input end of the six-input row trigger;
the output ends of the first transmission gate and the second transmission gate input signals to the input end of the first trigger according to the row displacement direction control signal of the third input end;
the first trigger comprises a first NMOS transistor, a second inverter, a third inverter, a first PMOS transistor and a first NOR gate circuit,
when the first row clock signal is at a high level, the first NMOS tube is switched on, and the first PMOS tube is switched off;
the output end of the first NMOS tube is connected with the input end of the second phase inverter, the output end of the second inverter and the sixth input end of the six-input row trigger are connected with the input end of a first NOR gate circuit, and the output end of the first NOR gate circuit is connected with the input end of the first PMOS tube;
when the first row clock signal is at a low level, the first PMOS tube is switched on, and the first NMOS tube is switched off so as to latch the output signal of the second phase inverter;
when the second row clock signal is at a high level, the second NMOS transistor is turned on, an output signal of the second inverter is transmitted to the third inverter, and an output end of the third inverter is an output end of the six-input-row flip-flop.
2. The readout circuit with image mirroring function of claim 1, wherein the N-bit column shift register comprises a column complementary clock generator for generating a first column clock signal and a second column clock signal according to an input column clock signal, wherein the first column clock signal is associated with a rising edge of the input column clock signal, and the second column clock signal is associated with a falling edge of the input column clock signal.
3. The readout circuit with image mirroring functionality of claim 2, wherein the N six-input column flip-flops comprise a first six-input column flip-flop, a second six-input column flip-flop … a jth six-input column flip-flop … an Nth six-input column flip-flop, wherein j is an integer and 1<j < N,
the first input end of the first six-input column trigger is connected with a column synchronization signal, the second input end of the first six-input column trigger is connected with the output end of the second six-input column trigger, the third input end of the first six-input column trigger is connected with a column shift direction control signal, the fourth input end of the first six-input column trigger is connected with the first column clock signal, the fifth input end of the first six-input column trigger is connected with the second column clock signal, the sixth input end of the first six-input column trigger is connected with a reset signal, and the output end of the first six-input column trigger is connected with the first input end of the second six-input column trigger;
the first input end of the jth sixth input column trigger is connected with the output end of the jth-1 sixth input column trigger, the second input end of the jth +1 sixth input column trigger is connected with the output end of the jth +1 sixth input column trigger, the third input end of the jth input column trigger is connected with a column shift direction control signal, the fourth input end of the jth input column trigger is connected with the first column clock signal, the fifth input end of the jth input column trigger is connected with the second column clock signal, the sixth input end of the jth input column trigger is connected with a reset signal, and the output end of the jth +1 sixth input column trigger is connected with the first input end of the jth +1 sixth input column trigger and the second input end of the jth-1 sixth input column trigger;
the first input end of the Nth six-input column trigger is connected with the output end of the N-1 th six-input column trigger, the second input end of the Nth six-input column trigger is connected with the column synchronous signal, the third input end of the Nth six-input column trigger is connected with the column shift direction control signal, the fourth input end of the Nth six-input column trigger is connected with the first column clock signal, the fifth input end of the Nth six-input column trigger is connected with the second column clock signal, the sixth input end of the Nth six-input column trigger is connected with the reset signal, and the output end of the Nth six-input column trigger is connected with the second input end of the N-1 th six-input column trigger.
4. A readout circuit with image mirroring functionality according to claim 3, wherein any one of the N six-input column flip-flops comprises:
the first transmission gate, the second inverter and the third flip-flop;
the input end of the third transmission gate is the first input end of the six-input-row flip-flop, the positive control end of the third transmission gate is the third input end of the six-input-row flip-flop, the input end of the fourth inverter is the third input end of the six-input-row flip-flop, and the negative control end of the third transmission gate is the output end of the fourth inverter;
the input end of the fourth transmission gate is the second input end of the six-input-row trigger, the positive control end of the fourth transmission gate is the output end of the fourth inverter, and the negative control end of the fourth transmission gate is the third input end of the six-input-row trigger;
and the output ends of the third transmission gate and the fourth transmission gate input signals to the input end of the second trigger according to the column shift direction control signal of the third input end.
5. The readout circuit with image mirroring function of claim 4, wherein the second flip-flop comprises a third NMOS transistor, a fourth NMOS transistor, a fifth inverter, a sixth inverter, a second PMOS transistor, a second NOR gate circuit,
when the first column clock signal is at a high level, the third NMOS tube is switched on, and the second PMOS tube is switched off;
the output end of the third NMOS tube is connected with the input end of a fifth inverter, the output end of the fifth inverter and the sixth input end of the six-input column trigger are connected with the input end of a second NOR gate circuit, and the output end of the second NOR gate circuit is connected with the input end of the second PMOS tube;
when the first column clock signal is at a low level, the second PMOS tube is switched on, and the third NMOS tube is switched off so as to latch the output signal of the fifth inverter;
when the second column clock signal is at a high level, the fourth NMOS transistor is turned on, an output signal of the fifth inverter is transmitted to the sixth inverter, and an output end of the sixth inverter is an output end of the six-input column flip-flop.
6. An infrared thermal imager, comprising: an infrared focal plane detector and a readout circuit with image mirroring functionality as claimed in any of the claims 1-5.
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CN101009762A (en) * 2007-01-26 2007-08-01 东南大学 Read-out circuit of infrared focal plane
CN114915737A (en) * 2022-07-18 2022-08-16 昆明钍晶科技有限公司 Reading circuit for image turning of infrared video image and infrared focal plane detector

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JP4693424B2 (en) * 2005-01-18 2011-06-01 東芝モバイルディスプレイ株式会社 Bidirectional shift register drive circuit, bidirectional shift register

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Publication number Priority date Publication date Assignee Title
US6232939B1 (en) * 1997-11-10 2001-05-15 Hitachi, Ltd. Liquid crystal display apparatus including scanning circuit having bidirectional shift register stages
CN101009762A (en) * 2007-01-26 2007-08-01 东南大学 Read-out circuit of infrared focal plane
CN114915737A (en) * 2022-07-18 2022-08-16 昆明钍晶科技有限公司 Reading circuit for image turning of infrared video image and infrared focal plane detector

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