CN115472720B - Light emitting diode epitaxial wafer, preparation method thereof and light emitting diode - Google Patents
Light emitting diode epitaxial wafer, preparation method thereof and light emitting diode Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title claims abstract description 8
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- 238000002203 pretreatment Methods 0.000 claims abstract description 11
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- 229910002704 AlGaN Inorganic materials 0.000 claims description 14
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- 235000012431 wafers Nutrition 0.000 description 37
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- 239000004065 semiconductor Substances 0.000 description 7
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- 238000005240 physical vapour deposition Methods 0.000 description 5
- 230000008569 process Effects 0.000 description 3
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- 230000007547 defect Effects 0.000 description 2
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- 229910052594 sapphire Inorganic materials 0.000 description 2
- 239000010980 sapphire Substances 0.000 description 2
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- 238000001755 magnetron sputter deposition Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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- 239000002245 particle Substances 0.000 description 1
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Abstract
The invention discloses a light-emitting diode epitaxial wafer, a preparation method thereof and a light-emitting diode, wherein the light-emitting diode epitaxial wafer comprises a substrate, and a buffer layer, an intrinsic GaN layer, an insertion layer, an N-type GaN layer, a multi-quantum well layer, an electronic barrier layer and a P-type GaN layer which are sequentially laminated on the substrate; the insertion layer comprises Si x N 1‑x Crack layer, al 1‑y Sc y An N pre-treatment layer and a GaN cap layer, the Si x N 1‑x Crack layer, al 1‑y Sc y The N pretreatment layer and the GaN cap layer are sequentially stacked on the intrinsic GaN layer, wherein the value range of x is 0.1-0.4; the value range of y is 0.1-0.3. The light-emitting diode epitaxial wafer prepared by the invention has lower working voltage and better antistatic capability.
Description
Technical Field
The invention relates to the technical field of photoelectricity, in particular to a light emitting diode epitaxial wafer, a preparation method of the light emitting diode epitaxial wafer and a light emitting diode.
Background
Currently, gaN-based light emitting diodes have been widely applied to the solid state lighting field and the display field, and attract more and more people to pay attention. GaN-based leds have been produced industrially and are used in backlights, illuminations, landscape lamps, etc.
For the LED device with the conventional structure, during the growth of the N-type semiconductor layer, the concentration of the N-type doping is very high, the crystalline integrity of the GaN material is reduced with the incorporation of the N-type doping, and the high N-type doping introduces a large stress. Moreover, because the growth temperature of intrinsic GaN is very high, the stress accumulated from the buffer layer reaches the maximum value when growing the N-type GaN layer, so that the warp is very large when growing the N-type doping, the stress accumulation makes the N-type doping difficult, especially the edge position of the epitaxial wafer often causes the N-type doping to be uneven, so that the working voltage is increased, the defects of surface atomization and the like of the epitaxial wafer caused by the large warp are easy to occur, the lattice quality is poor, and the antistatic capability of the light emitting diode is influenced.
Disclosure of Invention
The invention aims to provide an epitaxial wafer of a light-emitting diode, which can release the stress of a bottom layer, increase the flatness of the epitaxial layer and increase the uniformity of N-type doping, thereby reducing the working voltage and increasing the antistatic capability of the light-emitting diode.
The invention also provides a preparation method of the light-emitting diode epitaxial wafer, which is simple in process and high in production yield.
In order to solve the technical problem, the invention provides a light emitting diode epitaxial wafer, which comprises a substrate, and a buffer layer, an intrinsic GaN layer, an insertion layer, an N-type GaN layer, a multi-quantum well layer, an electronic barrier layer and a P-type GaN layer which are sequentially stacked on the substrate;
the insertion layer comprises Si x N 1-x Crack layer, al 1-y Sc y An N pre-treatment layer and a GaN cap layer, the Si x N 1-x Crack layer, al 1-y Sc y The N pretreatment layer and the GaN cap layer are sequentially stacked on the intrinsic GaN layer, wherein the value range of x is 0.1-0.4; the value range of y is 0.1-0.3.
In one embodiment, the thickness of the insertion layer is from 50nm to 70nm;
wherein, said Si x N 1-x The thickness of the crack layer is 10nm-20nm;
the Al is 1-y Sc y The thickness of the N pretreatment layer is 20nm-30nm;
the thickness of the GaN cap layer is 20nm-30nm.
In one embodiment, the buffer layer has a thickness of 10nm to 100nm;
the thickness of the intrinsic GaN layer is 300nm-800nm;
the thickness of the N-type GaN layer is 1-3 μm, and the N-type GaN layer is Si-dopedThe doping concentration of the Si is 5 multiplied by 10 18 -1×10 19 cm -3 ；
The thickness of the P-type GaN layer is 10nm-50nm, the P-type GaN layer is Mg doped, and the doping concentration of Mg is 5 multiplied by 10 17 -1×10 20 cm -3 。
In one embodiment, the multiple quantum well layer comprises InGaN quantum well layers and GaN quantum barrier layers which are alternately stacked, and the number of stacking periods is 3-15;
the thickness of the InGaN quantum well layer is 2nm-4nm;
the thickness of the GaN quantum barrier layer is 9nm-11nm.
In one embodiment, the electron blocking layer includes AlGaN layers and InGaN layers alternately stacked with a stacking period number of 3 to 15;
the thickness of the AlGaN layer is 5nm-7nm;
the thickness of the InGaN layer is 5nm-7nm.
In order to solve the above problems, the present invention further provides a method for preparing an epitaxial wafer of a light emitting diode, comprising the following steps:
preparing a substrate;
depositing a buffer layer, an intrinsic GaN layer, an insertion layer, an N-type GaN layer, a multi-quantum well layer, an electronic barrier layer and a P-type GaN layer on the substrate in sequence;
the insertion layer comprises Si x N 1-x Crack layer, al 1-y Sc y An N pre-treatment layer and a GaN cap layer, the Si x N 1-x Crack layer, al 1-y Sc y The N pretreatment layer and the GaN cap layer are sequentially stacked on the intrinsic GaN layer, wherein the value range of x is 0.1-0.4; the value range of y is 0.1-0.3.
In one embodiment, the Si is accomplished by the following method x N 1-x Deposition of a crack layer:
controlling the temperature of the reaction chamber at 1100-1150 ℃ and the pressure at 50-100 Torr, and introducing H 2 /N 2 As carrier gas, introducing NH 3 As a source of N, siH is introduced 4 As a Si source, the deposition was completed.
At one endIn one embodiment, the Al is accomplished by the following method 1-y Sc y Deposition of N pretreatment layer:
controlling the temperature of the reaction chamber at 200-1000 deg.C and the pressure at 5-10 mTorr, introducing Ar as carrier gas, and introducing N 2 And (4) taking the ScAl alloy target as a sputtering target to finish deposition.
In one embodiment, the deposition of the GaN cap layer is accomplished using the following method:
controlling the temperature of the reaction chamber at 900-1000 ℃, controlling the pressure at 100-300 Torr, and introducing H 2 /N 2 As carrier gas, introducing NH 3 And (4) preparing an N source, and introducing TMGa as a Ga source to finish deposition.
In one embodiment, depositing the buffer layer on the front side of the substrate is accomplished using the following method:
controlling the temperature of the reaction chamber to be 500-700 ℃, controlling the pressure to be 200-400 Torr, introducing TMAl as an Al source, and introducing NH 3 As an N source, finishing the deposition of a buffer layer on the front surface of the substrate;
and/or, depositing the intrinsic GaN layer on the buffer layer is accomplished using:
controlling the temperature of the reaction chamber at 1100-1150 deg.C and the pressure at 100-500 Torr, and introducing NH 3 As an N source, introducing TMGa as a Ga source to finish the deposition of the intrinsic GaN layer on the buffer layer;
and/or, depositing the N-type GaN layer on the insertion layer is completed by adopting the following method:
controlling the temperature of the reaction chamber to 1100-1150 ℃ and the pressure to be 100-500 Torr, and introducing SiH 4 As a source of Si, NH was introduced 3 As an N source, introducing TMGa as a Ga source to finish the deposition of the N-type GaN layer on the insertion layer;
and/or, depositing the P-type GaN layer on the electron blocking layer is completed by adopting the following method:
controlling the temperature of the reaction chamber at 800-1000 ℃, the pressure at 100-300 Torr, and introducing NH 3 Introducing TMGa as Ga source and CP as N source 2 Mg as Mg source to form the electron resistorAnd depositing the P-type GaN layer on the barrier layer.
In one embodiment, depositing the multiple quantum well layer on the N-type GaN layer is accomplished using the following method:
alternately depositing InGaN quantum well layers and GaN quantum barrier layers on the N-type GaN layers, wherein the number of stacked layers is 3-15;
wherein the depositing of the InGaN quantum well layer comprises:
controlling the temperature of the reaction chamber at 700-800 deg.C, the pressure at 100-500 Torr, introducing TMIn as In source, introducing NH 3 As an N source, introducing TMGa as a Ga source to finish deposition;
the deposition step of the GaN quantum barrier layer comprises the following steps:
controlling the temperature of the reaction chamber to be 800-900 ℃, controlling the pressure to be 100-500 Torr, and introducing NH 3 And (4) introducing TMGa as an N source to finish deposition.
In one embodiment, depositing the electron blocking layer on the multiple quantum well layer is accomplished using the following method:
alternately depositing AlGaN layers and InGaN layers on the multi-quantum well layer, wherein the number of stacked layers is 3-15;
wherein the depositing of the AlGaN layer comprises:
controlling the temperature of the reaction chamber at 900-1000 ℃, controlling the pressure at 100-500 Torr, introducing TMAl as an Al source and NH 3 As an N source, introducing TMGa as a Ga source to finish deposition;
the depositing of the InGaN layer comprises:
controlling the temperature of the reaction chamber at 900-1000 ℃, controlling the pressure at 100-500 Torr, introducing TMIn as an In source and NH 3 And (4) introducing TMGa as an N source to finish deposition.
Correspondingly, the invention also provides a light-emitting diode which comprises the light-emitting diode epitaxial wafer.
The implementation of the invention has the following beneficial effects:
according to the light emitting diode epitaxial wafer provided by the invention, the insertion layer is added between the intrinsic GaN layer and the N-type semiconductor layer, so that the bottom layer stress is fully released before the heavily doped N-type GaN semiconductor grows, the flatness of the epitaxial layer is increased, the stress of the N-type heavily doped growth is reduced, the uniformity of N-type doping is increased, the incorporation of N-type doping is increased, the working voltage is successfully reduced, the surface flatness of the epitaxial wafer is increased, and the antistatic capability of a light emitting diode is increased.
Drawings
FIG. 1 is a schematic structural diagram of an epitaxial wafer of a light emitting diode provided by the present invention, wherein a substrate 1, a buffer layer 2, an intrinsic GaN layer 3, and Si are provided x N 1-x Crack layer 41, al 1-y Sc y The N pre-treatment layer 42, the GaN cap layer 43, the N-type GaN layer 5, the multi-quantum well layer 6, the electron blocking layer 7, and the P-type GaN layer 8.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below.
Unless otherwise stated or contradicted, terms or phrases used herein have the following meanings:
in the present invention, the terms "combination thereof", "any combination thereof", and the like include all suitable combinations of any two or more of the listed items.
In the present invention, "preferred" is only an embodiment or an example for better description, and it should be understood that the scope of the present invention is not limited thereto.
In the present invention, the technical features described in the open type include a closed technical solution including the listed features, and also include an open technical solution including the listed features.
In the present invention, the numerical range is defined to include both end points of the numerical range unless otherwise specified.
At present, the traditional N-type semiconductor layer has the defects of large accumulated stress during growth, large warpage, easy surface atomization, poor lattice quality and influence on the antistatic capacity of the light-emitting diode. And the warpage is large, so that the N-type doping is not uniform, and the working voltage of the light emitting diode is high.
In order to solve the above problems, the present invention provides an led epitaxial wafer, as shown in fig. 1, including a substrate 1, and a buffer layer 2, an intrinsic GaN layer 3, an insertion layer 4, an N-type GaN layer 5, a multi-quantum well layer 6, an electron blocking layer 7, and a P-type GaN layer 8 sequentially stacked on the substrate 1;
the insertion layer 4 comprises Si x N 1-x Crack layer 41, al 1-y Sc y An N pre-treatment layer 42 and a GaN cap layer 43, the Si x N 1-x Crack layer 41, al 1-y Sc y The N pretreatment layer 42 and the GaN cap layer 43 are sequentially stacked on the intrinsic GaN layer 3, wherein the value range of x is 0.1-0.4; the value range of y is 0.1-0.3.
According to the light emitting diode epitaxial wafer provided by the invention, the insertion layer 4 is added between the intrinsic GaN layer 3 and the N-type GaN layer 5, so that the bottom layer stress is fully released before the heavily doped N-type GaN semiconductor grows, the flatness of the epitaxial layer is increased, the stress of N-type heavily doped growth is reduced, the uniformity of N-type doping is increased, the incorporation of N-type doping is increased, the working voltage is successfully reduced, the surface flatness of the epitaxial wafer is increased, and the antistatic capability of a light emitting diode is increased.
It is noted that the present invention first grows Si on the undoped intrinsic GaN layer x N 1-x In the crack layer, the SiN material has high flatness in a growth state of high Si doping and low pressure and high temperature, but is easy to have slight cracks, and the slight nano-scale cracks release the early accumulated stress of the epitaxial layer in the occurrence process. Then growing Al 1-y Sc y The N pretreatment layer has good lattice matching with the GaN material when Sc is doped to 10-30%, and can be used as a transition layer between SiN and GaN, and further the AlScN grown by the PVD method has higher flatness and can well fill fine cracks generated by the SiN material. If only Si is added x N 1-x A cracked layer, then unhealed cracks will make the lattice quality worse, thus having a reverse effect. Finally, in Al 1-y Sc y A GaN cap layer is superposed behind the N pretreatment layer to prevent Sc atoms from entering the N-type halfAnd the conductor layer influences N-type doping. Before the growth of the N-type layer, the stress of the bottom layer is well released, the warpage is small, the surface flatness is high, and the incorporation and uniform distribution of N-type doping are facilitated.
In one embodiment, the thickness of the insertion layer is from 50nm to 70nm; wherein, said Si x N 1-x The thickness of the crack layer is 10nm-20nm; the Al is 1-y Sc y The thickness of the N pretreatment layer is 20nm-30nm; the thickness of the GaN cap layer is 20nm-30nm. Preferably, the thickness of the insertion layer is 56nm to 64nm; wherein, said Si x N 1-x The thickness of the crack layer is 12nm-18nm; the Al is 1-y Sc y The thickness of the N pretreatment layer is 22nm-28nm; the thickness of the GaN cap layer is 22nm-28nm.
Specifically, the light emitting diode epitaxial wafer comprises the following layered structure. In one embodiment, the buffer layer is an AlGaN buffer layer or an AlN buffer layer. The buffer layer is mainly used for providing crystal seeds, relieving lattice mismatch of the substrate and the epitaxial layer and improving the lattice quality of the epitaxial wafer. In one embodiment, the buffer layer has a thickness of 10nm to 100nm.
The intrinsic GaN layer is an undoped GaN layer, and in one embodiment, the intrinsic GaN layer has a thickness of 300nm to 800nm.
The N-type GaN layer mainly provides electrons, and in one embodiment, the thickness of the N-type GaN layer is 1-3 μm, the N-type GaN layer is doped with Si with the doping concentration of 5 × 10 18 -1×10 19 cm -3 (ii) a The P-type GaN layer mainly provides holes, and in one embodiment, the thickness of the P-type GaN layer is 10nm-50nm, the P-type GaN layer is doped with Mg, and the doping concentration of Mg is 5 x 10 17 -1×10 20 cm -3 。
The multiple quantum well layer is a core structure of light emitting of the light emitting diode. In one embodiment, the multiple quantum well layer comprises InGaN quantum well layers and GaN quantum barrier layers which are alternately stacked, and the number of stacking periods is 3-15; the thickness of the InGaN quantum well layer is 2nm-4nm; the thickness of the GaN quantum barrier layer is 9nm-11nm.
The electron blocking layer is mainly used for blocking electrons and preventing the electrons from overflowing, and in one embodiment, the electron blocking layer comprises AlGaN layers and InGaN layers which are alternately stacked, and the stacking period number is 3-15; the thickness of the AlGaN layer is 5nm-7nm; the thickness of the InGaN layer is 5nm-7nm.
Correspondingly, the invention also provides a preparation method of the light-emitting diode epitaxial wafer, which comprises the following steps:
s1, preparing a substrate;
in one embodiment, the substrate is a sapphire substrate. Then, controlling the temperature of the reaction chamber to be 1000-1200 ℃, controlling the pressure of the reaction chamber to be 200-600 Torr, and reacting in H 2 And carrying out high-temperature annealing on the substrate for 5-8 min under the atmosphere, and cleaning particles and oxides on the surface of the substrate.
S2, sequentially depositing a buffer layer, an intrinsic GaN layer, an insertion layer, an N-type GaN layer, a multi-quantum well layer, an electronic barrier layer and a P-type GaN layer on the substrate;
the insertion layer comprises Si x N 1-x Crack layer, al 1-y Sc y An N pre-treatment layer and a GaN cap layer, the Si x N 1-x Crack layer, al 1-y Sc y The N pretreatment layer and the GaN cap layer are sequentially stacked on the intrinsic GaN layer, wherein the value range of x is 0.1-0.4; the value range of y is 0.1-0.3.
In one embodiment, the step S2 comprises the steps of:
s21, depositing the buffer layer on the front surface of the substrate by adopting the following method:
in one embodiment, the buffer layer is an AlGaN buffer layer or an AlN buffer layer. Preferably, the buffer layer is an AlN buffer layer, and the AlN buffer layer is prepared by the following method: controlling the temperature of the reaction chamber to be 500-700 ℃, controlling the pressure to be 200-400 Torr, introducing TMAl as an Al source, and introducing NH 3 And as an N source, finishing the deposition of a buffer layer on the front surface of the substrate.
S22, depositing the intrinsic GaN layer on the buffer layer by adopting the following method:
the reaction was cooled to room temperatureThe temperature is controlled between 1100 ℃ and 1150 ℃, the pressure is 100Torr to 500Torr, NH is introduced 3 And introducing TMGa as an N source to finish the deposition of the intrinsic GaN layer on the buffer layer.
S23, completing the Si by adopting the following method x N 1-x Deposition of a crack layer:
controlling the temperature of the reaction chamber at 1100-1150 ℃ and the pressure at 50-100 Torr, and introducing H 2 /N 2 As carrier gas, introducing NH 3 As a source of N, siH is introduced 4 As a Si source, the deposition was completed.
In the invention, si is grown on the intrinsic GaN layer x N 1-x The crack layer is prepared by the method, preferably, the pressure is 60Torr-80Torr, the temperature of the reaction chamber is controlled to be 1140-1150 ℃, and the value of x is in the range of 0.2-0.4. The SiN material has high flatness in the growth state of high Si doping, low pressure and high temperature, but slight cracks can occur, and the generation process of the slight nano-scale cracks is also the release of the early accumulated stress of the epitaxial layer. Si x N 1-x The crack layer is favorable for fully releasing the stress of the bottom layer before the heavily doped N-type GaN semiconductor grows, the flatness of the epitaxial layer is increased, the stress of the N-type heavily doped growth is reduced, and the uniformity of N-type doping is increased.
But if only Si is added x N 1-x A cracked layer, then unhealed cracks will make the lattice quality worse, thus having a reverse effect. In response to this problem, the present application introduces Al 1-y Sc y And N, pretreating the layer.
S24, completing the Al by adopting the following method 1-y Sc y Deposition of N pretreatment layer:
controlling the temperature of the reaction chamber at 200-1000 deg.C and the pressure at 5-10 mTorr, introducing Ar as carrier gas, and introducing N 2 And (4) taking the ScAl alloy target as a sputtering target to finish deposition.
Preferably, the epitaxial wafer is transferred to a PVD, i.e. Al is done in a magnetron sputtering apparatus 1-y Sc y And depositing an N pretreatment layer. The Al is 1-y Sc y When the Sc doping in the N pretreatment layer is 10-30%The AlScN material and the GaN material have good lattice matching and can be used as a transition layer between SiN and GaN, and furthermore, the AlScN grown by the PVD method has higher flatness and can well fill fine cracks generated by the SiN material.
S25, completing the deposition of the GaN cap layer by adopting the following method:
controlling the temperature of the reaction chamber at 900-1000 ℃, controlling the pressure at 100-300 Torr, and introducing H 2 /N 2 As carrier gas, introducing NH 3 And (4) preparing an N source, and introducing TMGa as a Ga source to finish deposition.
Preferably, the epitaxial wafer is transferred back into the MOCVD apparatus to complete the deposition of the GaN cap layer.
In the presence of Al 1-y Sc y And a GaN cap layer is superposed behind the N pretreatment layer, so that Sc atoms can be prevented from entering the N-type semiconductor layer to influence N-type doping. Therefore, before the growth of the N-type layer, the stress of the bottom layer is well released, the warpage is small, the surface flatness is high, and the incorporation and uniform distribution of N-type doping are facilitated.
S26, depositing the N-type GaN layer on the insertion layer by adopting the following method:
controlling the temperature of the reaction chamber at 1100-1150 deg.C and the pressure at 100-500 Torr, and introducing SiH 4 As a source of Si, NH was introduced 3 As an N source, introducing TMGa as a Ga source to finish the deposition of the N-type GaN layer on the insertion layer;
s27, depositing the multi-quantum well layer on the N-type GaN layer is completed by the following method:
alternately depositing InGaN quantum well layers and GaN quantum barrier layers on the N-type GaN layers, wherein the number of stacked layers is 3-15;
wherein the depositing of the InGaN quantum well layer comprises:
controlling the temperature of the reaction chamber at 700-800 deg.C, the pressure at 100-500 Torr, introducing TMIn as In source, introducing NH 3 As an N source, introducing TMGa as a Ga source to finish deposition;
the deposition step of the GaN quantum barrier layer comprises the following steps:
the temperature of the reaction chamber is controlled To be 800-900 ℃, and the pressure is controlled To be 100Torr-500Torr, introduction of NH 3 And (4) introducing TMGa as an N source to finish deposition.
S28, depositing the electron barrier layer on the multi-quantum well layer by adopting the following method:
alternately depositing AlGaN layers and InGaN layers on the multi-quantum well layer, wherein the number of stacked layers is 3-15;
wherein the depositing of the AlGaN layer comprises:
controlling the temperature of the reaction chamber at 900-1000 ℃, controlling the pressure at 100-500 Torr, introducing TMAl as an Al source and NH 3 As an N source, introducing TMGa as a Ga source to finish deposition;
the depositing of the InGaN layer comprises:
controlling the temperature of the reaction chamber at 900-1000 ℃, controlling the pressure at 100-500 Torr, introducing TMIn as an In source and NH 3 And (4) introducing TMGa as an N source to finish deposition.
S29, depositing the P-type GaN layer on the electron blocking layer by adopting the following method:
controlling the temperature of the reaction chamber at 800-1000 ℃, the pressure at 100-300 Torr, and introducing NH 3 Introducing TMGa as Ga source and CP as N source 2 And Mg is used as a Mg source to finish the deposition of the P-type GaN layer on the electron blocking layer.
Correspondingly, the invention also provides a light-emitting diode which comprises the light-emitting diode epitaxial wafer.
The deposition process is completed by using MOCVD equipment or PVD equipment, and the deposition method is not limited in the invention. The Al source, N source, ga source, si source, mg source, sc source, and In source are exemplary ones, and are not limited to the above.
The invention is further illustrated by the following specific examples:
example 1
The embodiment provides a light emitting diode epitaxial wafer, which comprises a substrate, and a buffer layer, an intrinsic GaN layer, an insertion layer, an N-type GaN layer, a multi-quantum well layer, an electronic barrier layer and a P-type GaN layer which are sequentially stacked on the substrate;
the insertion layer comprises Si x N 1-x Crack layer, al 1-y Sc y An N pre-treatment layer and a GaN cap layer, the Si x N 1-x Crack layer, al 1-y Sc y The N pretreatment layer and the GaN cap layer are sequentially stacked on the intrinsic GaN layer, wherein x is 0.3; y is 0.2.
The preparation method of the light-emitting diode epitaxial wafer comprises the following steps:
s1, preparing a substrate; the substrate is a sapphire substrate.
S2, sequentially depositing a buffer layer, an intrinsic GaN layer, an insertion layer, an N-type GaN layer, a multi-quantum well layer, an electronic barrier layer and a P-type GaN layer on the substrate;
specifically, S2 includes the steps of:
s21, depositing the buffer layer on the front surface of the substrate by adopting the following method:
controlling the temperature of the reaction chamber at 600 ℃, introducing TMAl as an Al source, and introducing NH 3 And as an N source, depositing a buffer layer on the front surface of the substrate, completing the deposition and controlling the thickness of the deposited buffer layer to be 30nm.
S22, depositing the intrinsic GaN layer on the buffer layer by adopting the following method:
the temperature of the reaction chamber is controlled at 1150 ℃, NH is introduced 3 As an N source, introducing TMGa as a Ga source to finish deposition and control the deposition thickness to be 400nm;
s23, completing the Si by adopting the following method x N 1-x Deposition of a crack layer:
the temperature of the reaction chamber was controlled at 1050 ℃ and the pressure was 70Torr, and H was introduced thereinto 2 /N 2 As carrier gas, introducing NH 3 As a source of N, siH is introduced 4 As a source of Si, completing the deposition and controlling the Si deposited x N 1-x The thickness of the crack layer was 15nm.
S24, completing the Al by adopting the following method 1-y Sc y Deposition of N pretreatment layer:
controlling the temperature of a reaction chamber at 600 ℃ and the pressure of 7mTorr in a PVD device, and introducing Ar as a carrierGas, introducing N 2 As reaction gas, and using ScAl alloy target as sputtering target to complete deposition and control the deposited Al 1-y Sc y The thickness of the N pretreatment layer was 25nm.
S25, completing the deposition of the GaN cap layer by adopting the following method:
the temperature of the reaction chamber was controlled at 950 ℃ and the pressure was 200Torr, and H was introduced thereinto 2 /N 2 As carrier gas, introducing NH 3 And (3) as an N source, introducing TMGa as a Ga source, finishing deposition and controlling the thickness of the deposited GaN cap layer to be 25nm.
S26, depositing the N-type GaN layer on the insertion layer by adopting the following method:
controlling the temperature of the reaction chamber at 1050 ℃, and introducing SiH 4 As a source of Si, NH was introduced 3 As N source, introducing TMGa as Ga source, completing deposition and controlling the deposition thickness to be 2 mu m, and the doping concentration of Si to be 1 x 10 19 cm -3 ；
S24, depositing the multi-quantum well layer on the N-type GaN layer by adopting the following method:
alternately depositing InGaN quantum well layers and GaN quantum barrier layers on the N-type GaN layers, wherein the number of stacked layers is 10;
wherein the depositing of the InGaN quantum well layer comprises:
controlling the temperature of the reaction chamber at 800 ℃, introducing an In source and introducing NH 3 As an N source, introducing TMGa as a Ga source to finish deposition and control the deposition thickness to be 3nm;
the deposition step of the GaN quantum barrier layer comprises the following steps:
controlling the temperature of the reaction chamber at 800 ℃, and introducing NH 3 And (3) as an N source, introducing TMGa as a Ga source, finishing deposition and controlling the deposition thickness to be 10nm.
S28, depositing the electron barrier layer on the multi-quantum well layer by adopting the following method:
alternately depositing AlGaN layers and InGaN layers on the multi-quantum well layer, wherein the number of stacked layers is 8;
wherein the depositing of the AlGaN layer comprises:
the reaction was cooled to room temperatureControlling the temperature at 950 ℃, controlling the pressure at 300Torr, introducing TMAl as an Al source, introducing NH 3 As an N source, introducing TMGa as a Ga source to finish deposition and control the deposition thickness to be 6nm;
the depositing of the InGaN layer comprises:
controlling the temperature of the reaction chamber at 950 ℃ and the pressure at 300Torr, introducing TMIn as an In source and NH 3 And (3) introducing TMGa as an N source, and finishing deposition to control the deposition thickness to be 6nm.
S29, depositing the P-type GaN layer on the electron blocking layer by adopting the following method:
controlling the temperature of the reaction chamber at 850 ℃, introducing an Mg source as a doping source, and introducing NH 3 As N source, introducing TMGa as Ga source, completing deposition and controlling the deposition thickness to be 4nm and the Mg doping concentration to be 5 x 10 19 cm -3 。
Example 2
The embodiment provides a light emitting diode epitaxial wafer, which comprises a substrate, and a buffer layer, an intrinsic GaN layer, an insertion layer, an N-type GaN layer, a multi-quantum well layer, an electronic barrier layer and a P-type GaN layer which are sequentially stacked on the substrate;
the insertion layer comprises Si x N 1-x Crack layer, al 1-y Sc y An N pre-treatment layer and a GaN cap layer, the Si x N 1-x Crack layer, al 1-y Sc y The N pretreatment layer and the GaN cap layer are sequentially stacked on the intrinsic GaN layer, wherein x is 0.4; y is 0.1.
The method for preparing the epitaxial wafer of the light emitting diode is as in example 1.
Example 3
The embodiment provides a light emitting diode epitaxial wafer, which comprises a substrate, and a buffer layer, an intrinsic GaN layer, an insertion layer, an N-type GaN layer, a multi-quantum well layer, an electronic barrier layer and a P-type GaN layer which are sequentially stacked on the substrate;
the insertion layer comprises Si x N 1-x Crack layer, al 1-y Sc y An N pre-treatment layer and a GaN cap layer, the Si x N 1-x Crack layer, al 1-y Sc y N pretreatmentThe physical layer and the GaN cap layer are sequentially laminated on the intrinsic GaN layer, wherein x is 0.1; y is 0.3.
The method for preparing the epitaxial wafer of the light emitting diode is as in example 1.
Comparative example 1
The comparative example provides a light emitting diode epitaxial wafer, which comprises a substrate, and a buffer layer, an intrinsic GaN layer and Si which are sequentially laminated on the substrate x N 1-x The GaN-based high-performance electronic barrier layer comprises a crack layer, an N-type GaN layer, a multi-quantum well layer, an electronic barrier layer and a P-type GaN layer, wherein x is 0.3; y is 0.2.
The method for preparing the epitaxial wafer of the light emitting diode is as in example 1.
Comparative example 2
The comparative example provides a light emitting diode epitaxial wafer, which comprises a substrate, and a buffer layer, an intrinsic GaN layer, an N-type GaN layer, a multi-quantum well layer, an electronic barrier layer and a P-type GaN layer which are sequentially stacked on the substrate.
The method for preparing the epitaxial wafer of the light emitting diode is as in example 1.
The light emitting diode epitaxial wafers prepared in examples 1 to 3 and comparative examples 1 to 2 were used to prepare chips for performance testing, and the test results are shown in table 1.
Table 1 shows the results of the performance tests of the light emitting diode epitaxial wafers obtained in examples 1 to 3 and comparative examples 1 to 2
The light emitting diode epitaxial wafer has the advantages that the light emitting diode epitaxial wafer has a specific insertion layer structure, so that the flatness of the epitaxial wafer is higher, the working voltage is lower, and the antistatic capability is better. If only a SiN crack layer is added, the unheated cracks may make the lattice quality worse, thereby having a reverse effect.
While the foregoing is directed to the preferred embodiment of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention.
Claims (10)
1. The light emitting diode epitaxial wafer is characterized by comprising a substrate, and a buffer layer, an intrinsic GaN layer, an insertion layer, an N-type GaN layer, a multi-quantum well layer, an electronic barrier layer and a P-type GaN layer which are sequentially stacked on the substrate;
the insertion layer comprises Si x N 1-x Crack layer, al 1-y Sc y An N pre-treatment layer and a GaN cap layer, the Si x N 1-x Crack layer, al 1- y Sc y The N pretreatment layer and the GaN cap layer are sequentially stacked on the intrinsic GaN layer from bottom to top, wherein the value range of x is 0.1-0.4; the value range of y is 0.1-0.3.
2. The light emitting diode epitaxial wafer of claim 1, wherein the thickness of the insertion layer is 50nm to 70nm;
wherein, said Si x N 1-x The thickness of the crack layer is 10nm-20nm;
the Al is 1-y Sc y The thickness of the N pretreatment layer is 20nm-30nm;
the thickness of the GaN cap layer is 20nm-30nm.
3. The light emitting diode epitaxial wafer according to claim 1, wherein the buffer layer has a thickness of 10nm to 100nm;
the thickness of the intrinsic GaN layer is 300nm-800nm;
the thickness of the N-type GaN layer is 1-3 μm, the N-type GaN layer is doped with Si, and the doping concentration of the Si is 5 x 10 18 -1×10 19 cm -3 ；
The thickness of the P-type GaN layer is 10nm-50nm, the P-type GaN layer is Mg doped, and the doping concentration of Mg is 5 multiplied by 10 17 -1×10 20 cm -3 。
4. The light emitting diode epitaxial wafer of claim 1, wherein the multiple quantum well layer comprises InGaN quantum well layers and GaN quantum barrier layers which are alternately stacked, and the number of stacking periods is 3 to 15;
the thickness of the InGaN quantum well layer is 2nm-4nm;
the thickness of the GaN quantum barrier layer is 9nm-11nm.
5. The light emitting diode epitaxial wafer according to claim 1, wherein the electron blocking layer comprises AlGaN layers and InGaN layers alternately stacked, the number of stacking cycles is 3 to 15;
the thickness of the AlGaN layer is 5nm-7nm;
the thickness of the InGaN layer is 5nm-7nm.
6. A preparation method of the light-emitting diode epitaxial wafer as claimed in any one of claims 1 to 5, characterized by comprising the following steps:
preparing a substrate;
depositing a buffer layer, an intrinsic GaN layer, an insertion layer, an N-type GaN layer, a multi-quantum well layer, an electronic barrier layer and a P-type GaN layer on the substrate in sequence;
the insertion layer comprises Si x N 1-x Crack layer, al 1-y Sc y An N pre-treatment layer and a GaN cap layer, the Si x N 1-x Crack layer, al 1- y Sc y The N pretreatment layer and the GaN cap layer are sequentially stacked on the intrinsic GaN layer, wherein the value range of x is 0.1-0.4; the value range of y is 0.1-0.3.
7. The method for preparing a light emitting diode epitaxial wafer according to claim 6, wherein the Si is completed by the following method x N 1-x Deposition of a crack layer:
controlling the temperature of the reaction chamber at 1100-1150 ℃ and the pressure at 50-100 Torr, and introducing H 2 /N 2 As carrier gas, introducing NH 3 As a source of N, siH is introduced 4 As a Si source, the deposition was completed.
8. The method for preparing an epitaxial wafer for light-emitting diodes according to claim 6,characterized in that the Al is accomplished by the following method 1-y Sc y Deposition of N pretreatment layer:
controlling the temperature of the reaction chamber at 200-1000 deg.C and the pressure at 5-10 mTorr, introducing Ar as carrier gas, and introducing N 2 And (4) as reaction gas, and taking the ScAl alloy target as a sputtering target to finish deposition.
9. The method for preparing the light-emitting diode epitaxial wafer as claimed in claim 6, wherein the deposition of the GaN cap layer is completed by the following method:
controlling the temperature of the reaction chamber to be 900-1000 ℃, controlling the pressure to be 100-300 Torr, and introducing H 2 /N 2 As carrier gas, introducing NH 3 And (4) preparing an N source, and introducing TMGa as a Ga source to finish deposition.
10. A light emitting diode comprising the light emitting diode epitaxial wafer as claimed in any one of claims 1 to 5.
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