CN115440818A - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN115440818A CN115440818A CN202110620561.1A CN202110620561A CN115440818A CN 115440818 A CN115440818 A CN 115440818A CN 202110620561 A CN202110620561 A CN 202110620561A CN 115440818 A CN115440818 A CN 115440818A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- Engineering & Computer Science (AREA)
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- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
A semiconductor structure and a forming method thereof are provided, wherein the forming method comprises the following steps: providing a substrate, wherein an initial fin portion protruding from the substrate and an isolation layer which is located on the substrate and covers part of the side wall of the initial fin portion are formed on the substrate, the substrate comprises a first device area used for forming a first device, and the initial fin portion comprises a channel area along the extending direction of the initial fin portion; in the first device region, removing the initial fin part exposed out of the isolation layer in the channel region at partial height, and reserving the residual initial fin part as a first fin part; forming a first gate oxide layer, wherein the first gate oxide layer covers the top and the side wall of the first fin part of the channel region; after the first gate oxide layer is formed, a gate structure crossing the first fin portion of the channel region is formed on the isolation layer, and the gate structure comprises a high-k dielectric layer covering the first gate oxide layer and a gate electrode layer located on the high-k dielectric layer. The invention reduces the depth-to-width ratio of the gap between the adjacent first fin parts in the channel region and improves the filling property of the grid structure between the adjacent first fin parts.
Description
Technical Field
Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same.
Background
With the rapid development of semiconductor manufacturing technology, semiconductor devices are being developed toward higher element density and higher integration. Transistors are currently being widely used as one of the basic semiconductor devices. Therefore, with the increase of the density and the integration of the semiconductor device, the size of the gate of the planar transistor is shorter and shorter, the control capability of the conventional planar transistor on channel current is weakened, a short channel effect occurs, leakage current is increased, and the electrical performance of the semiconductor device is affected finally.
In order to better accommodate the reduction in feature size, semiconductor processing is gradually beginning to transition from planar MOSFETs to three-dimensional transistors with higher power efficiency, such as fin field effect transistors (finfets). However, in the case of further reduction in feature size, it is difficult to further improve the performance of the finfet.
Disclosure of Invention
Embodiments of the present invention provide a semiconductor structure and a method for forming the same, which improve the working performance of the semiconductor structure.
To solve the above problems, an embodiment of the present invention provides a semiconductor structure, including: a substrate including a first device region for forming a first device; the fin portion is raised from the substrate and comprises a first fin portion located in the first device region, and the fin portion comprises a channel region along the extending direction of the fin portion; the isolation layer is positioned on the substrate and covers partial side walls of the fin parts, the top of the isolation layer is lower than the top of the fin part of the channel region, and the part, higher than the isolation layer, of the first fin part serves as a first effective fin part; the first gate oxide layer covers the top and the side wall of the first effective fin part of the channel region; the grid structure is positioned on the substrate and stretches across the first fin part, and comprises a high-k dielectric layer covering the first grid oxidation layer and a grid electrode layer positioned on the high-k dielectric layer; and the source-drain doping layer is positioned in the fin parts on two sides of the grid structure, and in the first device region, the top of the source-drain doping layer is higher than that of the first fin part of the channel region.
Correspondingly, an embodiment of the present invention further provides a method for forming a semiconductor structure, including: providing a substrate, wherein an initial fin portion protruding from the substrate and an isolation layer which is located on the substrate and covers a part of side walls of the initial fin portion are formed on the substrate, the substrate comprises a first device area used for forming a first device, and the initial fin portion comprises a channel area along the extending direction of the initial fin portion; in the first device region, removing the initial fin part exposed out of the channel region at the partial height of the isolation layer, and reserving the residual initial fin part as a first fin part; forming a first gate oxide layer, wherein the first gate oxide layer covers the top and the side wall of the first fin part of the channel region; after the first gate oxide layer is formed, a grid electrode structure crossing the first fin portion of the channel region is formed on the isolation layer, and the grid electrode structure comprises a high-k dielectric layer covering the first gate oxide layer and a grid electrode layer located on the high-k dielectric layer.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
in the semiconductor structure provided by the embodiment of the invention, under the trend that the semiconductor structure is more compact, in the first device region, the top of the source-drain doping layer is higher than the top of the first fin portion of the channel region, that is, the height of the first fin portion of the channel region is reduced, so that the aspect ratio of a gap between adjacent first fin portions in the channel region is reduced, the formation of a gate structure is facilitated, the filling property of the gate structure between adjacent first fin portions in the channel region is improved, and meanwhile, when the gate structure is formed, the probability of generating a void defect (void defect) due to the overlarge filling depth between adjacent first fin portions in the channel region is reduced.
In the method for forming the semiconductor structure provided by the embodiment of the invention, under the trend that the semiconductor structure is increasingly compact, the initial fin part exposed out of the isolation layer at partial height in the channel region is removed in the first device region, the residual initial fin part is reserved as the first fin part, the depth-to-width ratio of a gap between adjacent first fin parts in the channel region is reduced, the formation of the gate structure is facilitated, the filling property of the gate structure between the adjacent first fin parts in the channel region is improved, meanwhile, the probability of generating a void defect (void defect) due to the overlarge filling depth between the adjacent first fin parts in the channel region when the gate structure is formed is reduced, the top of the first fin part in the channel region is lower, the formation of the first fin layer with larger thickness according to the device performance requirement is facilitated, the high-voltage resistance of the first device is increased, and the working performance of the semiconductor structure is improved.
Drawings
Fig. 1 to 5 are schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure;
FIGS. 6-9 are schematic structural diagrams illustrating a semiconductor structure according to an embodiment of the present invention;
fig. 10 to fig. 22 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Detailed Description
The performance of semiconductor structures is still desired. There are reasons why the performance of semiconductor structures has yet to be improved when analyzed in conjunction with a method of forming the semiconductor structures.
Fig. 1 to 5 are schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure.
With reference to fig. 1 and fig. 2 in combination, fig. 1 is a top view, fig. 2 is a cross-sectional view of fig. 1 based on an AA direction, a substrate 10 is provided, a fin 20 protruding from the substrate 10 is formed on the substrate 10, the substrate 10 includes a first device region 10I for forming a first device, and a second device region 10C for forming a second device, an operating voltage of the first device is greater than an operating voltage of the second device, an interlayer dielectric layer 13 (shown in fig. 1) is formed on the substrate 10, a gate opening 15 (shown in fig. 1) is formed in the interlayer dielectric layer 13, the gate opening 15 crosses the fin 20, a region of the fin 20 exposed by the gate opening 15 is used as a channel region 20C along an extending direction of the fin 20, a dummy gate oxide layer 30 is further formed on the fin 20, and the dummy gate oxide layer 30 covers a top and a sidewall of the fin 20 of the channel region 20C.
Referring to fig. 3, the dummy gate oxide layer 30 is removed to expose the surface of the fin portion 20 of the channel region 20 c.
Referring to fig. 4, after removing the dummy gate oxide layer 30, a gate oxide layer (not labeled) is formed on the fin portion 20, the gate oxide layer covers the top and the sidewall of the fin portion 20 of the channel region 20C, and the gate oxide layer includes a first gate oxide layer 31 located in the first device region 10I and a second gate oxide layer 32 located in the second device region 10C.
Since the operating voltage of the first device is greater than the operating voltage of the second device, typically, the thickness of the first gate oxide 31 of the first device region 10I is greater than the thickness of the second gate oxide 32 of the second device region 10C.
Referring to fig. 5, after the gate oxide layer is formed, a gate structure 50 crossing the fin portion 20 of the channel region 20c is formed in the gate opening 15, where the gate structure 50 includes a high-k dielectric layer 51 covering the gate oxide layer and a gate electrode layer 52 on the high-k dielectric layer 51.
With the increase of the density and the integration of the semiconductor device, the distance between the adjacent fins 20 is continuously reduced, that is, the aspect ratio between the adjacent fins 20 is continuously increased, the filling property of the gate structure 50 between the adjacent fins 20 is increasingly poor, especially for the first device region 10I, the first gate oxide layer 31 is generally thick, after the gate oxide layer is formed, the distance between the adjacent fins 20 of the first device region 10I is further reduced, that is, the aspect ratio between the adjacent fins 20 of the first device region 10I is further increased, so that the difficulty of filling the gate structure 50 between the adjacent fins 20 of the first device region 10I is further increased, and meanwhile, the probability of generating a void defect due to the poor filling property of the gate structure 50 is also increased, which affects the working performance of the semiconductor structure.
In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein an initial fin portion protruding from the substrate and an isolation layer which is located on the substrate and covers a part of side walls of the initial fin portion are formed on the substrate, the substrate comprises a first device area used for forming a first device, and the initial fin portion comprises a channel area along the extending direction of the initial fin portion; in the first device region, removing the initial fin part exposed out of the channel region at the partial height of the isolation layer, and reserving the residual initial fin part as a first fin part; forming a first gate oxide layer, wherein the first gate oxide layer covers the top and the side wall of the first fin part of the channel region; after the first gate oxide layer is formed, a grid electrode structure crossing the first fin portion of the channel region is formed on the isolation layer, and the grid electrode structure comprises a high-k dielectric layer covering the first gate oxide layer and a grid electrode layer located on the high-k dielectric layer.
In the method for forming a semiconductor structure provided by the embodiment of the invention, under the trend of increasingly compact semiconductor structures, in the first device region, the initial fin part exposed out of the isolation layer in the channel region is removed, and the remaining initial fin part is kept as the first fin part, so that the depth-to-width ratio of a gap between adjacent first fin parts in the channel region is reduced, the formation of the gate structure is facilitated, the filling property of the gate structure between adjacent first fin parts in the channel region is improved, and meanwhile, the probability of void defects (void defects) caused by overlarge filling depth between adjacent first fin parts in the channel region is reduced when the gate structure is formed.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 6 to 9 are schematic structural diagrams of a semiconductor structure according to an embodiment of the invention. Fig. 6 is a plan view, fig. 7 is a cross-sectional view of fig. 6 taken along the direction AA, fig. 8 is a cross-sectional view of fig. 6 taken along the direction BB, and fig. 9 is a cross-sectional view of fig. 6 taken along the direction CC.
The semiconductor structure includes: a substrate 101 including a first device region 101I for forming a first device; a fin (not shown) protruding from the substrate 101, the fin including a first fin 211 located in the first device region 101I, the fin including a channel region 201c (as shown in fig. 11) along an extending direction of the fin; an isolation layer 121 located on the substrate 101 and covering a portion of the sidewall of the fin, where the top of the isolation layer 121 is lower than the top of the fin of the channel region 201c, and a portion of the first fin 211 higher than the isolation layer 121 is used as a first effective fin 231; a first gate oxide layer 311 covering the top and the sidewall of the first effective fin portion 231 of the channel region 201 c; a gate structure 501 located on the substrate 101 and crossing the first fin portion 211, where the gate structure 501 includes a high-k dielectric layer 511 covering the first gate oxide layer 311, and a gate electrode layer 521 located on the high-k dielectric layer 511; the source-drain doping layer 161 is located in the fin portions on two sides of the gate structure 501, and in the first device region 101I, the top of the source-drain doping layer 161 is higher than the top of the first fin portion 211 of the channel region 201c.
The substrate 101 provides a process operation basis for the formation process of the semiconductor structure. The semiconductor structure comprises a fin field effect transistor.
In this embodiment, the substrate 101 is made of silicon, in other embodiments, the substrate may also be made of other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be a silicon-on-insulator substrate or another type of substrate such as a germanium-on-insulator substrate. The material of the substrate may be a material suitable for process requirements or easy integration.
In this embodiment, the substrate 101 includes a first device region 101I for forming a first device and a second device region 101C for forming a second device, and an operating voltage of the first device is greater than an operating voltage of the second device.
In this embodiment, the first device is an input/output (IO) device, and the second device is a core (core) device. The core device is used for realizing the main functions of the integrated circuit, the input and output device is used for providing corresponding input signals for the core device or outputting corresponding signals of the core device, and the working voltage of the input and output device is higher than that of the core device. For example, the operating voltage of the core device is 0.4V to 1.2V, and the operating voltage of the input/output device is 1.0V to 3.5V.
It should be noted that the first device region 101I and the second device region 101C may be adjacent or not adjacent.
In this embodiment, a semiconductor structure is taken as an example of a fin field effect transistor, and the semiconductor structure includes a fin portion protruding from the substrate 101, and the fin portion is used for providing a channel of the fin field effect transistor.
In this embodiment, the fin portion and the substrate 101 are an integrated structure. In other embodiments, the fin may also be a semiconductor layer epitaxially grown on the substrate, thereby achieving the purpose of precisely controlling the height of the fin.
In this embodiment, the fin portion includes a first fin portion 211 located in the first device region 101I and a second fin portion 221 located in the second device region 101C, where the first fin portion 211 is configured to provide a channel of a first device, and the second fin portion 221 is configured to provide a channel of a second device.
Referring to fig. 6, along the extending direction of the fin (as shown in the X direction in fig. 6), the fin includes a channel region 201c. The fin of the channel region 201c is used as a channel of a transistor.
In this embodiment, in the channel region 201c, the top of the first fin 211 is lower than the top of the second fin 221.
The operating voltage of the first device is greater than the operating voltage of the second device, the top of the first fin portion 211 in the channel region 201c is lower, so that the depth-to-width ratio of a gap between adjacent first fin portions 211 in the channel region 201c is reduced, and the formation of the first gate oxide layer 311 with a larger thickness is facilitated, so that the high-voltage resistance of the first device is increased, and the improvement of the operating performance of the semiconductor structure is facilitated.
In this embodiment, the material of the first fin 211 includes silicon, germanium, silicon germanium, or iii-v semiconductor material; the material of the second fin 221 includes silicon, germanium, silicon germanium, or a iii-v semiconductor material.
Specifically, the material of the first fin 211 depends on the performance of a first device, and the material of the second fin 221 depends on the performance of a second device.
In this embodiment, the material of the fin portion is the same as that of the substrate 101, the material of the first fin portion 211 is silicon, and the material of the second fin portion 221 is also silicon.
The isolation layer 121 serves as a Shallow Trench Isolation (STI) structure for isolating adjacent transistors.
The isolation layer 121 is made of an insulating material. In this embodiment, the isolation layer 121 is made of silicon oxide.
In this embodiment, the isolation layer 121 covers a portion of the sidewall of the fin, and the top of the isolation layer 121 is lower than the top of the fin of the channel region 201c, so that the fin of the channel region 201c with a partial height can serve as a channel of a transistor.
Specifically, a portion of the first fin 211 higher than the isolation layer 121 serves as a first effective fin 231, and a portion of the second fin 221 higher than the isolation layer 121 serves as a second effective fin 241, so that the transistor only uses the first effective fin 231 and the second effective fin 241 as channels.
In the channel region 201c, the top of the first fin portion 211 is lower than the top of the second fin portion 221, and the top of the first effective fin portion 231 is lower than the top of the second effective fin portion 241.
In this embodiment, in the channel region 201c, the ratio of the height d1 of the first effective fin 231 to the height d2 of the second effective fin 241 is not too large or too small. If the ratio of the height d1 of the first effective fin portions 231 to the height d2 of the second effective fin portions 241 is too large, the height d1 of the first effective fin portions 231 is too large, so that it is difficult to reduce the width-depth ratio of the gap between adjacent first effective fin portions 231 in the first device region 101I, and it is difficult to form the first gate oxide layer 311 with a larger thickness, and it is difficult to increase the high voltage resistance of the first device, and meanwhile, when the gate structure 501 is formed, a void defect is easily generated due to too large filling depth between adjacent first effective fin portions 231 in the channel region 201c, and the filling performance of the gate structure 501 is affected, so that the working performance of the semiconductor structure is affected; if the ratio of the height d1 of the first effective fin 231 to the height d2 of the second effective fin 241 is too small, the height d1 of the first effective fin 231 is too small, which makes it difficult for the first effective fin 231 to have a sufficient height as a channel of the first device, thereby affecting the performance of the semiconductor structure. Therefore, in the present embodiment, in the channel region 201c, the height d1 of the first effective fin 231 is 5% to 95% of the height d2 of the second effective fin 241. For example, the height d1 of the first effective fin 231 is 30%, 50%, or 70% of the height d2 of the second effective fin 241.
The first gate oxide layer 311 is used for isolating the gate structure 501 from the first effective fin portion 231, and the second gate oxide layer 321 is used for isolating the gate structure 501 from the second effective fin portion 241.
In this embodiment, the operating voltage of the first device is greater than the operating voltage of the second device, and the thickness of the second gate oxide 321 is smaller than that of the first gate oxide 311. The larger thickness of the first gate oxide layer 311 increases the breakdown resistance between the gate structure 501 and the first effective fin 231 in the first device region 101I, so that the first device can operate at a higher voltage.
The first gate oxide layer 311 and the second gate oxide layer 321 need a better isolation performance, and in this embodiment, the material of the first gate oxide layer 311 includes SiO 2 And La 2 O 3 One or two of them; the material of the second gate oxide layer 321 comprises SiO 2 And La 2 O 3 One or two of them.
The gate structure 501 is used to control the turning on and off of the channel of the transistor. In this embodiment, the gate structure 501 is a metal gate structure.
The high-k dielectric layer 511 is used for isolating the gate electrode layer 521 from the first effective fin portion 231 and the second effective fin portion 241, and reducing the leakage probability of the semiconductor structure.
In this embodiment, the material of the high-k dielectric layer 511 includes a high-k dielectric material. Wherein, the high-k dielectric material is a dielectric material with a relative dielectric constant larger than that of silicon oxide. Specifically, the material of the high-k dielectric layer 511 comprises HfO 2 、ZrO 2 HfSiO, hfSiON, hfTaO, hfTiO, hfZrO or Al 2 O 3 One or more of (a).
In this embodiment, the material of the gate electrode layer 521 includes one or more of TiN, taN, ta, ti, tiAl, W, AL, tiSiN, and TiAlC. The gate electrode layer 521 includes a work function layer (not shown), and an electrode layer (not shown) on the work function layer. The work function layer is used for adjusting the threshold voltage of the transistor, and the electrode layer is used for leading out the electrical property of the metal gate structure.
In other embodiments, the gate structure may also be a polysilicon gate structure according to process requirements.
In this embodiment, the semiconductor structure further includes: and the side wall 141 covers the side wall of the gate structure 501.
The sidewall spacers 141 are used for protecting the sidewalls of the gate structure 501. The sidewall 141 may have a single-layer structure or a stacked-layer structure, and the material of the sidewall 141 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the sidewall spacers 141 are of a single-layer structure, and the material of the sidewall spacers 141 is silicon nitride.
In this embodiment, the semiconductor structure further includes: and the interlayer dielectric layer 131 is positioned on the isolation layer 121, and the interlayer dielectric layer 131 covers the side wall of the sidewall spacer 141 and exposes the top of the gate structure 501.
The interlayer dielectric layer 131 is used for isolation between adjacent devices, and the interlayer dielectric layer 131 is also used for providing a process foundation for forming the gate structure 501.
The interlayer dielectric layer 131 is made of an insulating material and includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride.
In the forming process of the semiconductor structure, after forming the first source-drain doping layer 161 in the first fin portion 211 at two sides of the gate structure 501, forming an interlayer dielectric layer 131, wherein the interlayer dielectric layer 131 covers the source-drain doping layer 161 and exposes the first fin portion 211 of the channel region 201 c; and removing the first fin portion 211 at a part of the height of the channel region 201c exposed by the interlayer dielectric layer 131. Therefore, the top of the source-drain doping layer 161 is higher than the top of the first fin 211 of the channel region 201c.
Under the trend that the semiconductor structure is more compact, in the first device region 101I, the top of the source-drain doping layer 161 is higher than the top of the first fin portion 211 of the channel region 201c, that is, the height of the first fin portion 211 of the channel region 201c is reduced, which reduces the aspect ratio of the gap between the adjacent first fin portions 211 in the channel region 201c, is beneficial to forming the gate structure 501, and improves the filling property of the gate structure 501 between the adjacent first fin portions 211 in the channel region 201c, and at the same time, reduces the probability of generating a void defect due to an excessively large filling depth between the adjacent first fin portions 211 in the channel region 201c when forming the gate structure 501, and moreover, the top of the first fin portion 211 in the channel region 201c is lower, which is beneficial to forming the first gate oxide layer 311 with a large thickness, thereby increasing the high voltage resistance of the first device, and in sum, all of which are beneficial to improving the working performance of the semiconductor structure.
The source-drain doping layer 161 is used as a source region or a drain region of the formed fin field effect transistor. Specifically, the doping type of the source-drain doping layer 161 is the same As the channel conductivity type of the corresponding transistor, and for an NMOS transistor, the doping ions in the source-drain doping layer 161 are N-type ions, and the N-type ions include P ions, as ions, or Sb ions; for a PMOS transistor, the doped ions In the source-drain doped layer 161 are P-type ions, and the P-type ions include B ions, ga ions, or In ions.
Fig. 10 to fig. 22 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Referring to fig. 10 to 12 in combination, fig. 10 is a top view, fig. 11 is a cross-sectional view of fig. 10 based on the AA direction, fig. 12 is a cross-sectional view of fig. 10 based on the BB direction, a substrate 100 is provided, an initial fin 200 protruding from the substrate 100 is formed on the substrate 100, and an isolation layer 120 is formed on the substrate 100 and covers a portion of a sidewall of the initial fin 200, the substrate 100 includes a first device region 100I for forming a first device, and the initial fin includes a channel region 200c along an extending direction of the initial fin 200 (as shown in fig. 10).
The substrate 100 provides a process operation basis for the formation process of the semiconductor structure. The semiconductor structure comprises a fin field effect transistor.
In this embodiment, the substrate 100 is made of silicon, in other embodiments, the substrate may also be made of other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium, and the substrate may also be a silicon-on-insulator substrate or another type of substrate such as a germanium-on-insulator substrate. The material of the substrate may be a material suitable for process requirements or easy integration.
In this embodiment, the substrate 100 includes a first device region 100I for forming a first device, and further includes a second device region 100C for forming a second device, and an operating voltage of the first device is greater than an operating voltage of the second device.
In this embodiment, the first device is an input/output (IO) device, and the second device is a core (core) device. The core device is used for realizing the main functions of the integrated circuit, the input and output device is used for providing corresponding input signals for the core device or outputting corresponding signals of the core device, and the working voltage of the input and output device is higher than that of the core device. For example, the operating voltage of the core device is 0.4V to 1.2V, and the operating voltage of the input/output device is 1.0V to 3.5V.
It should be noted that the first device region 100I and the second device region 100C may be adjacent or not adjacent.
In this embodiment, taking the semiconductor structure as a fin field effect transistor as an example, an initial fin 200 protruding from the substrate 100 is formed on the substrate 100, and the initial fin 200 is used for providing a channel of the fin field effect transistor.
In this embodiment, the initial fin 200 and the substrate 100 are a unitary structure. In other embodiments, the initial fin portion may also be a semiconductor layer epitaxially grown on the substrate, so as to achieve the purpose of accurately controlling the height of the initial fin portion.
Referring to fig. 10, the initial fin 200 includes a channel region 200c along an extending direction of the initial fin 200 (as indicated by X direction in fig. 10). The initial fin 200 of the channel region 200c serves as a channel for the transistor.
In the present embodiment, the material of the initial fin 200 includes silicon, germanium, silicon germanium, or a iii-v semiconductor material. In this embodiment, the material of the initial fin 200 is the same as that of the substrate 100, and the material of the initial fin 200 is silicon.
In this embodiment, the initial fin 200 on the substrate 100 of the second device region 100C serves as a second fin 220, and the second fin 220 is used to provide a channel of a second device.
In this embodiment, the second fin portion 220 is made of silicon.
The isolation layer 120 serves as a shallow trench isolation structure for isolating adjacent transistors.
The material of the isolation layer 120 is an insulating material. In this embodiment, the material of the isolation layer 120 is silicon oxide.
In this embodiment, the isolation layer 120 covers a portion of the sidewalls of the initial fin 200, and the top of the isolation layer 120 is lower than the top of the initial fin 200 of the channel region 200c, so that a portion of the initial fin 200 higher than the isolation layer 120 is used to provide a channel.
In this embodiment, the height of the initial fin portion exposed out of the isolation layer is a first height d2.
In this embodiment, in the step of providing the substrate 100, a dummy gate oxide layer 300 is further formed on the top and the sidewalls of the initial fin portion 200 exposed from the isolation layer 120.
As an example, the material of the dummy gate oxide layer 300 is silicon oxide.
In this embodiment, the interlayer dielectric layer 130 is formed on the isolation layer 120, the gate opening 150 is formed in the interlayer dielectric layer 130, the gate opening 150 crosses the initial fin portion 200 and exposes the top and the sidewall of the initial fin portion 200 of the channel region 200c, and the active drain doping layer 160 is formed in the initial fin portion 200 at two sides of the gate opening 150.
The interlayer dielectric layer 130 is used for isolating adjacent devices, and the interlayer dielectric layer 130 is also used for providing a process basis for forming the gate opening 150.
The interlayer dielectric layer 130 is made of an insulating material and comprises one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride.
The gate opening 150 is used to provide a spatial location for a subsequently formed gate structure.
The source-drain doping layer 160 is used as a source region or a drain region of the formed fin field effect transistor. Specifically, the doping type of the source-drain doping layer 160 is the same As the channel conductivity type of the corresponding transistor, and for an NMOS transistor, the doping ions in the source-drain doping layer 160 are N-type ions, and the N-type ions include P ions, as ions, or Sb ions; for a PMOS transistor, the doped ions In the source-drain doped layer 160 are P-type ions, and the P-type ions include B ions, ga ions, or In ions.
In this embodiment, a sidewall spacer 140 is further formed on the sidewall of the gate opening 150, and the interlayer dielectric layer 130 covers the sidewall spacer 140.
The sidewall spacers 140 are used to protect sidewalls of a subsequently formed gate structure. The sidewall 140 may have a single-layer structure or a stacked-layer structure, and the material of the sidewall 140 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the sidewall spacers 140 have a single-layer structure, and the material of the sidewall spacers 140 is silicon nitride.
In this embodiment, before forming the interlayer dielectric layer 130, the method further includes: a dummy gate layer (not labeled) is formed on the isolation layer 120, and the dummy gate layer crosses over the initial fin 200 and covers the top and sidewalls of the initial fin 200 of the channel region 200c.
The dummy gate layer is used for occupying a space position for forming a gate structure subsequently.
In this embodiment, the dummy gate layer covers the dummy gate oxide layer 300, and the sidewall spacers 140 cover the sidewalls of the dummy gate layer.
As an example, the material of the dummy gate layer is polysilicon.
In this embodiment, source-drain doping layers 160 are formed in the initial fin portions 200 on both sides of the dummy gate layer, after the source-drain doping layers 160 are formed, the interlayer dielectric layer 130 is formed on the substrate 100 on the side of the dummy gate layer, and the interlayer dielectric layer 130 is exposed out of the top of the dummy gate layer to prepare for removing the dummy gate layer subsequently.
In this embodiment, the step of forming the gate opening 150 includes: and removing the pseudo gate layer.
Referring to fig. 13 and 14 in combination, fig. 13 and 14 are cross-sectional views based on fig. 11, in the first device region 100I, the initial fins 200 exposed to the height of the isolation layer 120 in the channel region 200c are removed, and the remaining initial fins 200 are remained as the first fins 210.
Under the trend that the semiconductor structure is more compact, in the first device region 100I, the initial fin portion 200 exposed out of the channel region 200c at a partial height of the isolation layer 120 is removed, the remaining initial fin portion 200 is kept as the first fin portion 210, the aspect ratio of the gap between the adjacent first fin portions 210 in the channel region 200c is reduced, the formation of the gate structure is facilitated, the filling property of the gate structure between the adjacent first fin portions 210 in the channel region 200c is improved, and meanwhile, the probability of generating a void defect due to the excessively large filling depth between the adjacent first fin portions 210 in the channel region 200c when the gate structure is formed is reduced, and the top of the first fin portion 210 in the channel region 200c is lower, so that the formation of a first gate oxide layer with a larger thickness according to the device performance requirements is facilitated, and the improvement of the working performance of the semiconductor structure is facilitated.
The first fin 210 is used to provide a channel for a first device.
In this embodiment, the first fin portion 210 is made of silicon.
In this embodiment, in the first device region 100I, in the step of removing the initial fin portion 200 exposed to the partial height of the isolation layer 120 in the channel region 200c, the initial fin portion 200 exposed to the partial height of the isolation layer 120 in the channel region 200c is removed by using a dry etching process.
The dry etching process has anisotropic etching characteristics, has better etching directionality, and is beneficial to improving the forming quality and the dimensional accuracy of the first fin portion 210, and the dry etching process can better control process parameters, has higher process controllability, and is easy to obtain more accurate pattern transfer.
In this embodiment, the height of the remaining initial fin 200 of the channel region 200c exposed out of the isolation layer 120 is a second height d1, and the ratio of the second height d1 to the first height d2 should not be too large or too small. If the ratio of the second height d1 to the first height d2 is too large, the height d1 of the first fin portion 210 is too large, so that it is difficult to reduce the width-depth ratio of the gap between the adjacent first fin portions 210 in the first device region 100I, which makes it difficult to subsequently form a first gate oxide layer with a larger thickness, which makes it difficult to increase the high-voltage resistance of the first device, and meanwhile, when a gate structure is subsequently formed, because the filling depth between the adjacent first fin portions 210 in the channel region 200c is too large, a void defect is easily generated, which affects the filling property of the gate structure, which affects the working performance of the semiconductor structure; if the ratio of the second height d1 to the first height d2 is too small, the height d1 of the first fin 210 is too small, which makes it difficult to have the first fin 210 with a sufficient height as a channel of a first device, thereby affecting the performance of the semiconductor structure. Therefore, in the first device region 100I, in the step of removing the initial fins 200 in the channel region 200c exposed to the height of the isolation layer 120, the height of the channel region 200c with the remaining initial fins 200 exposed to the isolation layer 120 is a second height d1, and the proportion of the second height d1 to the first height d2 is 5% to 95%. For example, the second height d1 is 30%, 50%, or 70% of the first height d2.
Specifically, referring to fig. 13, in the first device region 100I, the step of removing the initial fin 200 exposed to the partial height of the isolation layer 120 in the channel region 200c includes: a first mask layer 410 is formed overlying the second fin 220, and the first mask layer 410 exposes the initial fin 200 of the channel region 200c in the first device region 100I.
In the first device region 100I, the first mask layer 410 exposes the initial fin portion 200 of the channel region 200C in preparation for removing the initial fin portion 200 of a partial height, and meanwhile, the first mask layer 410 is also used for protecting the second fin portion 220 located in the second device region 100C.
In the present embodiment, the first mask layer 410 is a stacked structure, and the first mask layer 410 includes a planarization layer (not labeled) and a photoresist layer (not labeled) on the planarization layer.
In this embodiment, the material of the planarization layer is a Spin On Carbon (SOC) material. The spin-coated carbon is formed by a spin-coating process, so that the process cost is low; moreover, the top surface flatness of the planarization layer is improved by adopting spin-on carbon.
In this embodiment, in the step of forming the first mask layer 410, the first mask layer 410 covers the dummy gate oxide layer 300 on the second fin portion 220.
Referring to fig. 14, after forming the first mask layer 410, before removing the initial fin 200 of the channel region 200c exposed by the first mask layer 410, the method further includes: the dummy gate oxide layer 300 exposed by the first mask layer 410 is removed.
Removing the dummy gate oxide layer 300 exposed by the first mask layer 410, exposing the surface of the first fin portion 210, and preparing for forming a first gate oxide layer subsequently.
With continued reference to fig. 14, in the first device region 100I, the initial fin portion 200 of the channel region 200c exposed by the first mask layer 410 is removed, and the remaining initial fin portion 200 is retained as the first fin portion 210.
The initial fin portions 200 of the channel region 200c with a partial height exposed by the first mask layer 410 are removed, so that damage to the second fin portions 220 during the process of removing the initial fin portions 200 with a partial height in the first device region 100I is reduced.
Specifically, the initial fin 200 of the channel region 200c is removed along the gate opening 150 of the first device region 100I to a partial height.
Referring to fig. 15, fig. 15 is a cross-sectional view based on fig. 14, after the first fin portion 210 is formed, the first mask layer 410 is removed in preparation for a subsequent formation of a second gate oxide layer.
Specifically, the dummy gate oxide layer 300 in the gate opening 150 of the first device region 100I is removed.
With continued reference to fig. 15, a first gate oxide layer 310 is formed, the first gate oxide layer 310 covering the top and sidewalls of the first fin portion 210 of the channel region 200c.
The first gate oxide layer 310 is used to isolate a subsequently formed gate structure from the first fin portion 210.
In this embodiment, an oxidation process is used to form the first gate oxide layer 310, so that the first gate oxide layer 310 is only formed on the top and the sidewall of the first fin portion 210 exposed to the isolation layer 120.
The first gate oxide layer 310 needs a better isolation performance, and in this embodiment, the material of the first gate oxide layer 310 includes SiO 2 And La 2 O 3 One or two of them.
It should be noted that the dummy gate oxide layer 300 is formed on the top and the sidewall of the second fin portion 220, and in the process of forming the first gate oxide layer 310, the dummy gate oxide layer 300 protects the top and the sidewall of the second fin portion 220, so that the first gate oxide layer 310 is selectively formed on the top and the sidewall of the first fin portion 210 in the channel region 200c.
With combined reference to fig. 16 and 17, fig. 16 and 17 are cross-sectional views based on fig. 5, and after forming the first gate oxide layer 310 and before subsequently forming a second gate oxide layer, the method further includes: forming a second mask layer 420 covering the first gate oxide layer 310, wherein in the second device region 200C, the second mask layer 420 exposes the dummy gate oxide layer 300 in the channel region.
The second mask layer 420 exposes the dummy gate oxide layer 300 located in the channel region, so as to prepare for removing the dummy gate oxide layer 300 in the second device region 100C subsequently, and at the same time, the second mask layer 420 also protects the first gate oxide layer 310 located in the first device region 100I.
In this embodiment, the second mask layer 420 is a stacked structure, and the second mask layer 420 includes a planarization layer (not shown) and a photoresist layer (not shown) on the planarization layer.
In this embodiment, the material of the planarization layer is a Spin On Carbon (SOC) material. The spin-coated carbon is formed by a spin-coating process, so that the process cost is low; moreover, by using spin-on carbon, the top surface flatness of the planarization layer is advantageously improved.
Referring to fig. 17, the dummy gate oxide layer 300 exposed by the second mask layer 420 is removed.
And removing the pseudo gate oxide layer 300 exposed by the second mask layer 420 to expose the surface of the second fin portion 220, so as to prepare for forming a second gate oxide layer subsequently. Referring to fig. 18, fig. 18 is a cross-sectional view based on fig. 17, after removing the dummy gate oxide layer 300 exposed by the second mask layer 420, removing the second mask layer 420 in preparation for forming a gate structure subsequently.
With continued reference to fig. 18, before the subsequent formation of the gate structure, the method further includes: forming a second gate oxide layer 320, wherein the second gate oxide layer 320 covers the top and the side wall of the second fin portion 220 of the channel region 200c, and the thickness of the second gate oxide layer 320 is smaller than that of the first gate oxide layer 310.
The second gate oxide layer 320 is used for isolating a subsequently formed gate structure and the second fin portion 220.
In this embodiment, an oxidation process is used to form the second gate oxide layer 320, so that the second gate oxide layer 320 is formed only on the top and the sidewalls of the second fin portion 220 exposed from the isolation layer 120.
In this embodiment, if the operating voltage of the first device is greater than the operating voltage of the second device, the thickness of the second gate oxide layer 320 is smaller than the thickness of the first gate oxide layer 310. The greater thickness of the first gate oxide layer 310 improves the breakdown resistance between the gate structure and the first fin 210 in the first device region 100I, thereby enabling the first device to operate at a higher voltage.
The second gate oxide layer 320 needs a better isolation performance, and in this embodiment, the material of the second gate oxide layer 320 includes SiO 2 And La 2 O 3 One or two of them.
It should be noted that, a first gate oxide layer 310 is formed on the top and the sidewall of the first fin portion 210, and in the process of forming the second gate oxide layer 320, the first gate oxide layer 310 protects the top and the sidewall of the first fin portion 210, so that the second gate oxide layer 320 is selectively formed on the top and the sidewall of the second fin portion 220 in the channel region 200c.
Referring to fig. 19 to 22 in combination, fig. 19 is a cross-sectional view based on fig. 18, fig. 20 is a top view of a gate structure and a fin portion, fig. 21 is a cross-sectional view based on BB direction of fig. 20, fig. 22 is a cross-sectional view based on CC direction of fig. 20, after forming the first gate oxide layer 310, a gate structure 500 of the first fin portion 210 crossing the channel region 200c is formed on the isolation layer 120, wherein the gate structure 500 includes a high-k dielectric layer 510 covering the first gate oxide layer 310, and a gate electrode layer 520 located on the high-k dielectric layer 510.
In this embodiment, in the step of forming the gate structure 500, the high-k dielectric layer 510 further covers the second gate oxide layer 320.
In this embodiment, the gate structure 500 is formed in the gate opening 150.
The gate structure 500 is used to control the turning on and off of the channel of the transistor. In this embodiment, the gate structure 500 is a metal gate structure.
The high-k dielectric layer 510 is used for isolating the gate electrode layer 520 from the first fin portion 210 and the second fin portion 220, and reducing the leakage probability of the semiconductor structure.
In this embodiment, the material of the high-k dielectric layer 510 includes a high-k dielectric material. Wherein, the high-k dielectric material is a dielectric material with a relative dielectric constant larger than that of silicon oxide. Specifically, the material of the high-k dielectric layer 510 includes HfO 2 、ZrO 2 HfSiO, hfSiON, hfTaO, hfTiO, hfZrO or Al 2 O 3 One or more of (a).
In this embodiment, the material of the gate electrode layer 520 includes one or more of TiN, taN, ta, ti, tiAl, W, AL, tiSiN, and TiAlC. The gate electrode layer 520 includes a work function layer (not shown), and an electrode layer (not shown) on the work function layer. The work function layer is used for adjusting the threshold voltage of the transistor, and the electrode layer is used for leading out the electrical property of the metal gate structure.
In other embodiments, the gate structure may also be a polysilicon gate structure according to process requirements.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (17)
1. A semiconductor structure, comprising:
a substrate including a first device region for forming a first device;
the fin portion protrudes from the substrate, the fin portion comprises a first fin portion located in the first device region, and the fin portion comprises a channel region along the extending direction of the fin portion;
the isolation layer is positioned on the substrate and covers partial side walls of the fin parts, the top of the isolation layer is lower than the top of the fin part of the channel region, and the part, higher than the isolation layer, of the first fin part serves as a first effective fin part;
the first gate oxide layer covers the top and the side wall of the first effective fin part of the channel region;
the grid structure is positioned on the substrate and stretches across the first fin part, and comprises a high-k dielectric layer covering the first grid oxide layer and a grid electrode layer positioned on the high-k dielectric layer;
and the source-drain doping layer is positioned in the fin parts on two sides of the grid structure, and in the first device region, the top of the source-drain doping layer is higher than that of the first fin part of the channel region.
2. The semiconductor structure of claim 1, wherein the substrate further comprises a second device region for forming a second device, the operating voltage of the first device being greater than the operating voltage of the second device;
the fin portion further comprises a second fin portion located in the second device region, and in the channel region, the top of the first fin portion is lower than the top of the second fin portion;
the part, higher than the isolation layer, of the second fin part is used as a second effective fin part;
the semiconductor structure further includes: the second gate oxide layer covers the top and the side wall of the second effective fin part of the channel region, and the thickness of the second gate oxide layer is smaller than that of the first gate oxide layer;
the grid electrode structure further stretches across the second fin portion, and the high-k dielectric layer further covers the second gate oxide layer.
3. The semiconductor structure of claim 2, wherein a height of the first effective fin is 5% to 95% of a height of the second effective fin in the channel region.
4. The semiconductor structure of claim 1, wherein a material of the first fin comprises silicon, germanium, silicon germanium, or a group iii-v semiconductor material.
5. The semiconductor structure of claim 2, wherein a material of the second fin comprises silicon, germanium, silicon germanium, or a group iii-v semiconductor material.
6. The semiconductor structure of claim 1, wherein the material of the first gate oxide layer comprises SiO 2 And La 2 O 3 One or two of them; the material of the high-k dielectric layer comprises HfO 2 、ZrO 2 HfSiO, hfSiON, hfTaO, hfTiO, hfZrO and Al 2 O 3 One or more of; the material of the gate electrode layer comprises one or more of TiN, taN, ta, ti, tiAl, W, AL, tiSiN and TiAl C.
7. The semiconductor structure of claim 2, wherein the material of said second gate oxide layer comprises SiO 2 And La 2 O 3 One or two of them.
8. The semiconductor structure of claim 2, wherein the first device is an input-output device and the second device is a core device.
9. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein an initial fin portion protruding from the substrate and an isolation layer which is located on the substrate and covers a part of side walls of the initial fin portion are formed on the substrate, the substrate comprises a first device area used for forming a first device, and the initial fin portion comprises a channel area along the extending direction of the initial fin portion;
in the first device region, removing the initial fin part exposed out of the channel region at the partial height of the isolation layer, and reserving the residual initial fin part as a first fin part;
forming a first gate oxide layer, wherein the first gate oxide layer covers the top and the side wall of the first fin part of the channel region;
after the first gate oxide layer is formed, a grid electrode structure crossing the first fin portion of the channel region is formed on the isolation layer, and the grid electrode structure comprises a high-k dielectric layer covering the first gate oxide layer and a grid electrode layer located on the high-k dielectric layer.
10. The method of claim 9, wherein in the step of providing the substrate, the substrate further comprises a second device region for forming a second device, the initial fin on the substrate of the second device region is used as a second fin, and an operating voltage of the first device is greater than an operating voltage of the second device;
before forming the gate structure, the method further comprises: forming a second gate oxide layer, wherein the second gate oxide layer covers the top and the side wall of the second fin part of the channel region, and the thickness of the second gate oxide layer is smaller than that of the first gate oxide layer;
in the step of forming the gate structure, the high-k dielectric layer also covers the second gate oxide layer.
11. The method of forming a semiconductor structure of claim 10, wherein in the first device region, removing the initial fin portion of the channel region exposed to a partial height of the isolation layer comprises: forming a first mask layer covering the second fin portion, wherein the first mask layer exposes the initial fin portion of the channel region in the first device region;
in the first device area, removing the initial fin part of the channel area with the partial height exposed by the first mask layer, and reserving the residual initial fin part as a first fin part;
and removing the first mask layer after the first fin part is formed.
12. The method for forming a semiconductor structure of claim 11, wherein in the step of providing a substrate, a dummy gate oxide layer is further formed on the top and sidewalls of the initial fin portion exposed out of the isolation layer;
in the step of forming the first mask layer, the first mask layer covers the pseudo gate oxide layer on the second fin portion;
after the first mask layer is formed, before removing the initial fin portion of the channel region with the partial height exposed by the first mask layer, the method further includes: removing the pseudo gate oxide layer exposed by the first mask layer;
after the first gate oxide layer is formed and before the second gate oxide layer is formed, the method further comprises the following steps: forming a second mask layer covering the first gate oxide layer, wherein in the second device area, the second mask layer exposes the pseudo gate oxide layer positioned in the channel area;
removing the pseudo gate oxide layer exposed by the second mask layer;
and removing the second mask layer.
13. The method for forming the semiconductor structure according to claim 9, wherein in the step of providing the substrate, an interlayer dielectric layer is formed on the isolation layer, a gate opening is formed in the interlayer dielectric layer, the gate opening crosses over the initial fin portion and exposes the top and the sidewalls of the initial fin portion of the channel region, and an active drain doping layer is formed in the initial fin portion on both sides of the gate opening;
forming the gate structure in the gate opening.
14. The method of forming a semiconductor structure of claim 13, further comprising, prior to forming said interlevel dielectric layer: forming a pseudo gate layer on the isolation layer, wherein the pseudo gate layer crosses the initial fin part and covers the top and the side wall of the initial fin part of the channel region;
forming the source-drain doping layers in the initial fin parts on two sides of the pseudo gate layer;
after the source-drain doping layer is formed, forming the interlayer dielectric layer on the substrate on the side part of the pseudo gate layer, wherein the interlayer dielectric layer is exposed out of the top of the pseudo gate layer;
the step of forming the gate opening includes: and removing the pseudo gate layer.
15. The method for forming the semiconductor structure according to claim 9, wherein in the step of removing the initial fin portion of the channel region exposed to the partial height of the isolation layer in the first device region, the initial fin portion of the channel region exposed to the partial height of the isolation layer is removed by a dry etching process.
16. The method of forming a semiconductor structure of claim 10, wherein in the step of providing a substrate, the first device is an input-output device and the second device is a core device.
17. The method of forming a semiconductor structure of claim 11, wherein in the step of providing a substrate, the initial fin is exposed to the isolation layer at a first height;
in the first device region, in the step of removing the initial fin portion of the channel region exposed out of the isolation layer at a partial height, the height of the channel region with the remaining initial fin portion exposed out of the isolation layer is a second height, and the second height accounts for 5% to 95% of the first height.
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| CN (1) | CN115440818A (en) |
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2021
- 2021-06-03 CN CN202110620561.1A patent/CN115440818A/en active Pending
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