CN116031259A - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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Publication number
CN116031259A
CN116031259A CN202111258439.0A CN202111258439A CN116031259A CN 116031259 A CN116031259 A CN 116031259A CN 202111258439 A CN202111258439 A CN 202111258439A CN 116031259 A CN116031259 A CN 116031259A
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fin
layer
device region
region
gate
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郑二虎
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Abstract

A semiconductor structure and a method of forming the same, the method comprising: providing a substrate, wherein the substrate comprises a first device region and a second device region, the device working voltage of the first device region is smaller than that of the second device region, and the fin part comprises a channel region along the extending direction; in the second device region, thinning the fin part of the channel region; forming a pseudo gate structure crossing the fin part of the channel region on the substrate, wherein the pseudo gate structure comprises a gate oxide layer and a pseudo gate layer covering the gate oxide layer; forming source-drain doped layers in fin parts on two sides of the pseudo gate layer; forming an interlayer dielectric layer on the substrate to expose the top of the pseudo gate layer; removing the pseudo gate structure of the first device region and the pseudo gate layer of the second device region to form a gate opening; a gate structure is formed in the gate opening. The invention reduces the width of the fin parts of the channel region so as to increase the space between the fin parts of the adjacent channel regions, thereby improving the formation quality of the grid electrode structure.

Description

Semiconductor structure and forming method thereof
Technical Field
Embodiments of the present disclosure relate to semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.
Background
With the gradual development of semiconductor process technology, the development trend of the semiconductor process node following moore's law is continuously reduced. To accommodate the reduction in process nodes, the channel length of MOSFET field effect transistors is also correspondingly reduced. However, as the channel length of the device is shortened, the distance between the source and the drain of the device is shortened, so that the control capability of the gate to the channel is deteriorated, and the difficulty of pinching off (pin off) the channel by the gate voltage is also increased, so that the phenomenon of subthreshold leakage (subthreshold leakage), namely the so-called short-channel effect (SCE), is more likely to occur.
Accordingly, to better accommodate the demand for device scaling, semiconductor processes are increasingly beginning to transition from planar MOSFETs to three-dimensional transistors with higher efficiency, such as Fin Field effect transistors (Fin Field-Effect Transistor, finFET). In the FinFET, the gate can control the ultrathin body (fin part) from at least two sides, and compared with a planar MOSFET, the gate has stronger control capability on a channel, and can well inhibit short channel effect; and finfets have better compatibility with existing integrated circuit fabrication than other devices.
Disclosure of Invention
The embodiment of the invention solves the problem of providing a semiconductor structure and a forming method thereof, and improves the performance of the semiconductor structure.
To solve the above problems, an embodiment of the present invention provides a semiconductor structure, including: the substrate comprises a first device region and a second device region, wherein the device working voltage of the first device region is smaller than that of the second device region; the fin parts are respectively positioned on the substrates of the first device region and the second device region, the fin parts comprise a channel region and non-channel regions positioned at two sides of the channel region along the extending direction of the fin parts, part of the fin parts with the height being used as bottom fin parts, the fin parts with the rest heights being used as effective fin parts, the effective fin parts are positioned at the tops of the bottom fin parts, wherein the side walls of the effective fin parts of the channel region in the second device region are retracted inwards relative to the side walls of the fin parts of the non-channel regions at the same side, the width of the effective fin parts of the channel region in the second device region is smaller than the width of the fin parts of the non-channel region, and the width of the effective fin parts of the channel region in the first device region is larger than the width of the effective fin parts of the channel region in the second device region. The isolation layer is positioned on the substrate at the side part of the fin part, covers the side wall of the bottom fin part and exposes the effective fin part; the grid structure is positioned on the isolation layer and spans the effective fin part, and comprises a grid dielectric layer covering the top and the side wall of the effective fin part of the channel region and a grid electrode layer covering the grid dielectric layer, and the thickness of the grid dielectric layer of the second device region is larger than that of the first device region; the side walls are positioned at two sides of the grid structure and cover the side walls of the grid structure; the source-drain doped layer is positioned in the effective fin parts at two sides of the grid structure and is positioned at one side of the side wall far away from the grid structure.
Correspondingly, the embodiment of the invention also provides a method for forming the semiconductor structure, which comprises the following steps: providing a substrate, wherein the substrate comprises a first device region and a second device region, the device working voltage of the first device region is smaller than that of the second device region, and the fin comprises a channel region along the extending direction of the fin; in the second device region, thinning the fin part of the channel region to reduce the width of the fin part of the channel region; after thinning the fin part of the channel region, forming a pseudo gate structure on the substrate, wherein the pseudo gate structure spans the fin part of the channel region and covers part of the top and part of the side wall of the fin part of the channel region, and the pseudo gate structure comprises a gate oxide layer and a pseudo gate layer covering the gate oxide layer; forming source-drain doping layers in fin parts on two sides of the pseudo gate layer; forming an interlayer dielectric layer covering the source-drain doped layer on the substrate, wherein the interlayer dielectric layer covers the side wall of the pseudo gate layer and exposes the top of the pseudo gate layer; removing the pseudo gate structure of the first device region and the pseudo gate layer of the second device region, and forming a gate opening in the interlayer dielectric layer; a gate structure is formed in the gate opening.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
in the semiconductor structure provided by the embodiment of the invention, the device working voltage of the first device region is smaller than that of the second device region, the effective fin side wall of the channel region is retracted inwards relative to the fin side wall of the non-channel region on the same side in the second device region, so that the effective fin width of the channel region in the second device region is reduced, the space between the fin parts of the adjacent channel regions is correspondingly increased, and therefore, the process window for forming the gate electrode layer in the second device region is increased under the condition that the gate dielectric layer thickness of the second device region is correspondingly larger than that of the first device region, the covering capacity or filling capacity of the gate electrode layer between the fin parts is improved, the forming quality of the gate structure is improved, in addition, in the second device region, the side wall of the effective fin part of the channel region is retracted inwards relative to the side wall of the bottom fin part of the channel region on the same side, namely, the width of the effective fin part of the channel region is reduced, and the source-drain doping layers are arranged in the effective fin parts on two sides of the gate structure, and the influence on the source-drain doping layers is reduced due to the fact that the width of the fin parts of the non-channel region is not reduced, so that the forming quality and the forming volume of the source-drain doping layers are guaranteed, and the performance of the source-drain doping layers is guaranteed; in summary, the embodiments of the present invention improve the performance of semiconductor structures.
In the method for forming a semiconductor structure provided by the embodiment of the invention, the device working voltage of the first device region is smaller than the device working voltage of the second device region, when the gate opening is formed in the interlayer dielectric layer, the dummy gate structure of the first device region and the dummy gate layer of the second device region are removed, that is, the gate oxide layer is reserved in the gate opening of the second device region and is used as a part of the gate dielectric layer of the device, so that the thickness of the gate dielectric layer of the second device region is larger than that of the first device region, therefore, before the dummy gate structure is formed on the substrate, thinning treatment is carried out on the fin part of the channel region in the second device region, the width of the fin part of the channel region is reduced, and the space between the fin parts of adjacent channel regions is increased, the process window for forming the gate structure in the gate opening of the second device region is increased, the covering capacity or filling capacity of the gate structure among the fin parts is improved, the forming quality of the gate structure is improved, in addition, thinning treatment is only carried out on the fin parts of the channel region, thinning treatment is not carried out on the fin parts of the non-channel region, the fin parts of the non-channel region maintain the initial width, source-drain doping layers are formed in the fin parts on two sides of the pseudo gate layer, namely, the source-drain doping layers are formed in the fin parts of the non-channel region, and the influence on the source-drain doping layers is correspondingly reduced due to the fact that the width of the fin parts of the non-channel region is not reduced, so that the forming quality and the forming volume of the source-drain doping layers are guaranteed, and the performance of the source-drain doping layers is guaranteed; in summary, the embodiments of the present invention improve the performance of semiconductor structures.
Drawings
FIG. 1 is a schematic diagram of a semiconductor structure;
FIGS. 2-5 are schematic diagrams illustrating the structure of an embodiment of a semiconductor structure according to the present invention;
fig. 6 to 37 are schematic views illustrating steps corresponding to the method for forming a semiconductor structure according to an embodiment of the present invention.
Detailed Description
The performance of current semiconductor structures is still to be improved. The reason why the performance of a semiconductor structure is to be improved is now analyzed in conjunction with a method of forming the semiconductor structure.
Fig. 1 is a schematic structural diagram of a semiconductor structure.
The semiconductor structure includes: a substrate 10; a fin 20 protruding above the substrate 10; an isolation layer 30 located on the substrate 10 at the side of the fin 20, wherein the isolation layer 30 covers part of the side wall of the fin 20; and a gate structure 40 on the isolation layer 30, wherein the gate structure 40 spans across the fin 20 and covers a portion of the top and a portion of the sidewall of the fin 20, and the gate structure 40 includes a gate dielectric layer 41 and a gate electrode layer 42 covering the gate dielectric layer 41.
In a practical process, the substrate 10 generally includes a plurality of device regions for forming devices with different operating voltages, for example, the substrate 10 includes a core region for forming a core device and a high voltage region for forming a high voltage device, and the operating voltage of the high voltage device is greater than that of the core device.
In order to prevent problems such as electrical breakdown, the higher the operating voltage of the device, the greater the thickness of the corresponding gate dielectric layer 41. Accordingly, in the forming process of the semiconductor structure, in the device region with the larger thickness of the gate dielectric layer 41, after the gate dielectric layer 41 is formed, the smaller the remaining space between the adjacent fin portions 20 is, so that the smaller the process window for forming the gate electrode layer 42 is, the coverage capability or filling capability of the gate electrode layer 42 between the fin portions 20 is reduced, and further the forming quality of the gate structure 40 is degraded, and the performance of the semiconductor structure is correspondingly reduced.
In order to solve the technical problem, an embodiment of the present invention provides a semiconductor structure, including: the substrate comprises a first device region and a second device region, wherein the device working voltage of the first device region is smaller than that of the second device region; the fin parts are respectively positioned on the substrates of the first device region and the second device region, the fin parts comprise a channel region and non-channel regions positioned at two sides of the channel region along the extending direction of the fin parts, part of the fin parts with the height being used as bottom fin parts, the fin parts with the rest heights being used as effective fin parts, the effective fin parts are positioned at the tops of the bottom fin parts, wherein the side walls of the effective fin parts of the channel region in the second device region are retracted inwards relative to the side walls of the fin parts of the non-channel regions at the same side, the width of the effective fin parts of the channel region in the second device region is smaller than the width of the fin parts of the non-channel region, and the width of the effective fin parts of the channel region in the first device region is larger than the width of the effective fin parts of the channel region in the second device region. The isolation layer is positioned on the substrate at the side part of the fin part, covers the side wall of the bottom fin part and exposes the effective fin part; the grid structure is positioned on the isolation layer and spans the effective fin part, and comprises a grid dielectric layer covering the top and the side wall of the effective fin part of the channel region and a grid electrode layer covering the grid dielectric layer, and the thickness of the grid dielectric layer of the second device region is larger than that of the first device region; the side walls are positioned at two sides of the grid structure and cover the side walls of the grid structure; the source-drain doped layer is positioned in the effective fin parts at two sides of the grid structure and is positioned at one side of the side wall far away from the grid structure.
The effective fin side walls of the channel region are retracted inwards relative to the fin side walls of the non-channel region at the same side in the second device region, so that the effective fin width of the channel region in the second device region is reduced, the space between the fin parts of the adjacent channel regions is correspondingly increased, and therefore when the thickness of the gate dielectric layer of the second device region is correspondingly larger than that of the gate dielectric layer of the first device region, a process window for forming a gate electrode layer in the second device region is increased, the covering capacity or filling capacity of the gate electrode layer between the fin parts is improved, the formation quality of a gate structure is improved, and in the second device region, the effective fin side walls of the channel region are retracted inwards relative to the bottom fin side walls of the channel region at the same side, that is, the width of the effective fin parts of the channel region is only reduced, and the source drain doping layer is located in the effective fin parts at the two sides of the gate structure, and the source drain doping layer is not reduced, so that the volume of the source doping layer is correspondingly reduced, the source doping layer is guaranteed, the drain doping layer is guaranteed, and the source doping layer is guaranteed, and the drain doping layer is guaranteed, and the source doping layer is guaranteed. In summary, the embodiments of the present invention improve the performance of semiconductor structures.
In order that the above objects, features and advantages of embodiments of the invention may be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
Fig. 2 to 5 are schematic structural views of an embodiment of the semiconductor structure of the present invention, fig. 2 is a top view of a first device region, fig. 3 (a) is a cross-sectional view along AA1 direction of fig. 2, fig. 3 (b) is a cross-sectional view along DD1 direction of fig. 2, fig. 4 is a top view of a second device region, fig. 5 (a) is a cross-sectional view along BB1 direction of fig. 4, and fig. 5 (b) is a cross-sectional view along CC1 direction of fig. 4.
The semiconductor structure includes: a substrate 500 comprising a first device region 500A and a second device region 500B, the first device region 500A having a device operating voltage that is less than the device operating voltage of the second device region 500B; the fin 510 is located on the substrate 500 of the first device region 500A and the second device region 500B, respectively, along the extending direction of the fin 510, the fin 510 includes a channel region 10A, and non-channel regions 10B located at two sides of the channel region 10A, the fin 510 with a part of the height is used as a bottom fin 511, the fin 510 with the remaining height is used as an effective fin 512, the effective fin 512 is located at the top of the bottom fin 511, wherein the side wall of the effective fin 512 of the channel region 10A in the second device region 500B is retracted inwards relative to the side wall of the fin 510 of the non-channel region 10B on the same side, the width of the effective fin 512 of the channel region 10A in the second device region 500B is smaller than the width of the fin 510 of the non-channel region 10B, and the width of the effective fin 512 of the channel region 10A in the first device region 500A is larger than the width of the effective fin 512 of the channel region 10A in the second device region 500B. An isolation layer 501 on the substrate 500 at the side of the fin 510, wherein the isolation layer 501 covers the sidewall of the bottom fin 511 and exposes the effective fin 512; a gate structure 850 located on the isolation layer 501 and crossing the effective fin 512, wherein the gate structure 850 includes a gate dielectric layer 830 covering the top and the sidewall of the effective fin 512 of the channel region 10A, and a gate electrode layer 820 covering the gate dielectric layer 830, and the thickness of the gate dielectric layer 830 of the second device region 500B is greater than the thickness of the gate dielectric layer 830 of the first device region 500A; side walls (not shown) located at both sides of the gate structure 850 and covering the side walls of the gate structure 850; the source-drain doped layer 730 is located in the effective fin 512 at two sides of the gate structure 850, and is located at a side of the sidewall remote from the gate structure 850.
The substrate 500 is used to provide a process platform for the formation of semiconductor structures.
The material of the substrate 500 includes silicon, germanium, silicon carbide, gallium arsenide, indium gallium, silicon on insulator, or germanium on insulator. In this embodiment, the material of the substrate 500 is silicon.
In this embodiment, the substrate 500 includes a first device region 500A and a second device region 500B, where the device operating voltage of the first device region 500A is less than the device operating voltage of the second device region 500B.
Specifically, the first device region 500A is used to form a core device, and the second device region 500B is used to form a High Voltage (High Voltage) device or an input/output (I/O) device.
It should be noted that, the core device mainly refers to a device used inside a chip, and generally adopts lower working voltages (generally 1.0V, 1.2V, 1.5V and 1.8V), and the input/output device is a device used when the chip interacts with an external interface, and the working voltage of such a device is generally higher and depends on compatible working voltages (generally 1.8V, 2.5V, 3.3V and 5V) of the external interface.
In other embodiments, the first device region and the second device region may also be used to form other types of devices. For example, the first device region is used to form a low voltage device (LV device), the second device region is used to form a high voltage device (HV device), and the operating voltage of the low voltage device is less than the operating voltage of the high voltage device.
In this embodiment, the semiconductor structure is a fin field effect transistor (FinFET), and therefore, a fin 510 is formed on the substrate 400, and the fin 510 is used to provide a channel of the transistor.
The projection of the gate structure 850 onto the substrate 500 is orthogonal to the projection of the fin 510 onto the substrate 500, and thus the fin 510 includes a channel region 10a and non-channel regions 10b located on both sides of the channel region 10a along the extension direction.
The channel region 10a is used to form a gate structure 850 at a position where the non-channel region 10b is used to form the source drain doped layer 730, so that the device conduction channel is turned on or off by the gate structure 850.
Specifically, the material of fin 510 includes silicon, silicon germanium, or a group iii-v semiconductor material. The material of the fin 510 depends on the channel conductivity type and performance requirements of the transistor. In this embodiment, the fin 510 is made of silicon. As an example, the fin 510 and the substrate 500 are a unitary structure. Accordingly, the material of the fin 510 is the same as that of the substrate 500, and the material of the fin 510 is silicon.
The isolation layer 501 is used to achieve isolation between different device regions. Specifically, the isolation layer 501 is a Shallow Trench Isolation (STI) structure.
The material of the isolation layer 501 is an insulating material. For example, the material of the isolation layer 501 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, and silicon oxycarbonitride. As an example, the material of the isolation layer 501 is silicon oxide.
In this embodiment, the gate structure 501 is located on the isolation layer 501, and the gate structure 501 only covers part of the top and part of the sidewall of the fin 510 exposed from the isolation layer 501, so that the fin 510 exposed from the isolation layer 501 is used as an effective fin 512, and the effective fin 512 is used to provide a conductive channel for transistor operation. Accordingly, the fin 510 covered by the isolation layer 501 serves as a bottom fin 511.
Referring to fig. 5 (a) in combination, in the present embodiment, in the second device region 500B, the sidewalls of the effective fin 512 of the channel region 10a are recessed with respect to the sidewalls of the fin 510 of the non-channel region 10B on the same side, that is, in the second device region 500B, the width of the effective fin 512 of the channel region 10a is smaller than the width of the fin 510 of the non-channel region 10B along the direction perpendicular to the sidewalls of the fin 510 (i.e., the direction perpendicular to the extending direction of the fin 510).
The device operating voltage of the first device region 500A is smaller than the device operating voltage of the second device region 500B, and when the device operating voltage is larger, the thickness of the gate dielectric layer of the device is required to be larger, that is, the thickness of the gate dielectric layer 830 of the second device region 500B is larger than the thickness of the gate dielectric layer 830 of the first device region 500A.
Therefore, by making the sidewalls of the effective fin 512 of the channel region 10A retract inward relative to the sidewalls of the fin 510 of the non-channel region 10B on the same side in the second device region 500B, the width of the effective fin 512 of the channel region 10A in the second device region 500B is reduced, and the space between the fins 510 of the adjacent channel region 10A is correspondingly increased, so that in the case that the thickness of the gate dielectric layer 830 of the second device region 500B is correspondingly greater than that of the gate dielectric layer 830 of the first device region 500A, the process window for forming the gate electrode layer 820 in the second device region 500B is increased, and the coverage or filling capability of the gate electrode layer 820 between the fins 510 is improved, thereby being beneficial to improving the formation quality of the gate structure 850 of the second device region 500B and correspondingly improving the performance of the semiconductor structure.
Note that in the second device region 500B, the dimension of the effective fin 512 sidewall of the channel region 10a that is recessed inward with respect to the fin 510 sidewall of the non-channel region 10B on the same side is not too small or too large. If the effective fin 512 sidewalls of the channel region 10a are too small to be recessed inwardly with respect to the fin 510 sidewalls of the non-channel region 10B on the same side, the effect of increasing the space between the fins 510 of adjacent channel regions 10a is likely to be poor, resulting in poor effect of increasing the process window for forming the gate electrode layer 820 in the second device region 500B; if the sidewalls of the effective fin 512 of the channel region 10a are too large in the inward-retracted dimension relative to the sidewalls of the fin 510 of the non-channel region 10b on the same side, the width of the effective fin 512 of the channel region 10a is easily reduced, which not only easily causes the electrical performance of the device to be shifted, but also easily reduces the mechanical strength of the effective fin 512 of the channel region 10a, and accordingly increases the probability of deformation of the effective fin 512 of the channel region 10 a. For this purpose, in the second device region 500B, the effective fin 512 sidewall of the channel region 10a is recessed 1 nm to 3 nm relative to the fin 510 sidewall of the non-channel region 10B on the same side. For example, the effective fin 512 sidewalls of the channel region 10a are recessed 1.5 nanometers, 2 nanometers, or 2.5 nanometers relative to the fin 510 sidewalls of the non-channel region 10b on the same side.
The width of the effective fin 512 of the channel region 10a refers to: the lateral dimensions of the active fin 512 are along a direction parallel to the surface of the substrate 500 and perpendicular to the direction in which the fin 510 extends.
In this embodiment, in the second device region 500B, the sidewalls of the effective fin 512 of the channel region 10a are recessed inward with respect to the sidewalls of the bottom fin 511 of the channel region 10a on the same side, that is, the sidewalls of the bottom fin 511 of the channel region 10a are flush with the sidewalls of the bottom fin 511 of the non-channel region 10B on the same side, so that only the width of the effective fin 512 of the channel region 10a is reduced, and the width of the bottom fin 511 is larger, which is beneficial to ensure the mechanical strength of the entire fin 510.
Moreover, the source-drain doped layer 730 is located in the effective fin 512 at two sides of the gate structure 850, and since the fin width of the non-channel region 10b is not reduced, the influence on the source-drain doped layer 730 is reduced, so that the formation quality and volume of the source-drain doped layer 730 are ensured, and the performance of the source-drain doped layer 730 is ensured.
In addition, in the process of forming the semiconductor structure, after the isolation layer 501 is formed, the effective fin 512 of the channel region 10a may be thinned to reduce the width of the effective fin 512 of the channel region 10a, and compared with the scheme of thinning the effective fin and the bottom fin of the channel region before forming the isolation layer, in this embodiment, the aspect ratio of the space surrounded by the effective fin 512 and the isolation layer 501 is smaller, which is favorable for reducing the process difficulty of the thinning and improving the process effect of the thinning, thereby being favorable for precisely controlling the width of the effective fin 512 of the channel region 10 a.
The gate structure 850 is used to control the turning on or off of the conduction channel of the transistor. In this embodiment, the gate structure 850 spans the active fin 512 and covers the top and sidewalls of the active fin 512 of the channel region 10a, thereby implementing control over the conduction channel.
Specifically, the gate structure 850 includes a gate dielectric layer 830, and a gate electrode layer 820 covering the gate dielectric layer 830.
The gate dielectric layer 830 is used to isolate the gate electrode layer 820 from the channel. The gate dielectric layer 830 material includes HfO 2 、ZrO 2 、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、Al 2 O 3 、SiO 2 And La (La) 2 O 3 One or more of the following.
In this embodiment, the gate structure 850 is a metal gate structure. Thus, gate dielectric layer 830 includes high-k gate dielectric layer 810. The material of the high-k gate dielectric layer 810 is a high-k dielectric material, where the high-k dielectric material refers to a dielectric material having a relative permittivity greater than that of silicon oxide. Specifically, the material of the high-k gate dielectric layer 810 may be selected from HfO 2 、ZrO 2 HfSiO, hfSiON, hfTaO, hfTiO, hfZrO or Al 2 O 3 Etc. As an example, the material of the high-k gate dielectric layer 810 is HfO 2 。
In this embodiment, the gate dielectric layer 830 of the second device region 500B further includes a gate oxide layer 800 between the high-k gate dielectric layer 810 and the active fin 512. As an example, the material of the gate oxide layer 800 is silicon oxide. In other embodiments, the gate oxide layer may also be silicon oxynitride.
In this embodiment, in the second device region 500B, the gate oxide layer 800 covers the top of the bottom fin 511 exposed by the effective fin 512, so as to reduce the influence of the bottom fin on the device performance.
In this embodiment, the gate dielectric layer 830 of the first device region 500A only includes the high-k gate dielectric layer 810, and the gate dielectric layer 830 of the second device region 500B includes the gate oxide layer 800 and the high-k gate dielectric layer 810 covering the gate oxide layer 800, so that the thickness of the gate dielectric layer 830 of the second device region 500B is greater than that of the gate dielectric layer 830 of the first device region 500A, so as to meet different requirements of the device operating voltages of the first device region 500A and the second device region 500B.
In other embodiments, in the first device region, the gate dielectric layer further includes a gate oxide layer located between the high-k gate dielectric layer and the active fin. The device working voltage of the first device region is smaller than that of the second device region, so that the thickness of the gate oxide layer of the first device region is smaller than that of the second device region.
The gate electrode layer 820 is used to electrically lead out the gate structure 850. The material of the gate electrode layer 820 includes one or more of TiN, taN, ta, ti, tiAl, W, al, tiSiN and TiAlC.
As one example, the gate electrode layer 820 includes a work function layer and an electrode layer covering the work function layer. In other embodiments, the gate electrode layer may also include only a work function layer. Wherein the work function layer is used to adjust the operating voltage of the formed transistor. It will be appreciated that the material, thickness and number of layers of the work function layer may be different in each device region depending on the performance requirements of the transistor in the different device regions.
In this embodiment, along the extending direction of the fin 510, the adjacent gate structures 850 in the first device region 500A have a first pitch (pitch), and the adjacent gate structures 850 in the second device region 500B have a second pitch. The pitch here refers to: along the extending direction of the fin 510, the sum of the width (width) of one gate structure 850 and the pitch (space) of the adjacent gate structure 850.
Since the device operating voltage of the first device region 500A is smaller than the device operating voltage of the second device region 500B, the width of the gate structure 850 of the second device region 500B is greater than the width of the gate structure 850 of the first device region 500A along the extending direction of the fin 510, and correspondingly, the second pitch is greater than the first pitch.
Specifically, the second pitch is at least twice as large as the first pitch, so that in the second device region 500B, the length of the effective fin 512 of the channel region 10a along the extending direction of the fin 510 is larger, and thus, in the process of thinning the effective fin 512 of the channel region 10a, the process window of the thinning is larger and the process difficulty of the thinning is lower. For example, during the thinning process, it is generally necessary to use a shielding layer with mask openings to define the area of the thinning process, and the second pitch is larger, which correspondingly increases the size of the mask openings and the distance between adjacent mask openings along the extending direction of the fin 510, so as to increase the process window of the photolithography process used to form the mask openings, and facilitate the thinning process of the exposed effective fin 512 through the mask openings.
The source/drain doped layer 730 is used as a source or drain region of the transistor being formed.
Specifically, the doping type of the source/drain doping layer 730 is the same as the channel conductivity type of the corresponding transistor. When the transistor is a PMOS transistor, the material of the source drain doped layer 730 includes silicon germanium doped with P-type ions, including B, ga or In. When the transistor is an NMOS transistor, the material of the source-drain doped layer 730 includes silicon or silicon carbide doped with N-type ions including P, as or Sb.
The side walls are used to protect the side walls of the gate structure 850 and define the formation positions of the source/drain doped layers 730. The description of the side wall is not repeated here.
In this embodiment, the semiconductor structure further includes: an interlayer dielectric layer 502 is located on the substrate at the side of the gate structure 850 and covers the sidewalls of the gate structure 850. Specifically, the interlayer dielectric layer 502 covers the sidewall of the sidewall.
The interlayer dielectric layer 502 is used to achieve electrical isolation between adjacent devices. The interlayer dielectric layer 502 is made of an insulating material. In this embodiment, the material of the interlayer dielectric layer 502 is silicon oxide. In other embodiments, the material of the interlayer dielectric layer may be silicon nitride or silicon oxynitride or other dielectric materials.
Fig. 6 to 37 are schematic views illustrating steps corresponding to the method for forming a semiconductor structure according to an embodiment of the present invention.
Referring to fig. 6 and 7, fig. 6 (a) is a top view of a first device region, fig. 6 (B) is a cross-sectional view along the AA1 direction of fig. 6 (a), fig. 7 (a) is a top view of a second device region, fig. 7 (B) is a cross-sectional view along the BB1 direction of fig. 7 (a), a substrate (not labeled) is provided, including a substrate 100, and a fin 110 located on the substrate 100, the substrate 100 includes a first device region 100A and a second device region 100B, a device operating voltage of the first device region 100A is less than a device operating voltage of the second device region 100B, and the fin 110 includes a channel region 10A along an extension direction of the fin 110.
The substrate 100 is used to provide a process platform for the formation of semiconductor structures.
The material of the substrate 100 includes silicon, germanium, silicon carbide, gallium arsenide, indium gallium, silicon on insulator, or germanium on insulator. In this embodiment, the material of the substrate 100 is silicon.
In this embodiment, the device operating voltage of the first device region 100A is smaller than the device operating voltage of the second device region 100B.
Specifically, the first device region 100A is used to form a core device, and the second device region 100B is used to form a High Voltage (High Voltage) device or to form an input/output device.
In other embodiments, the first device region and the second device region may also be used to form other types of devices. For example, the first device region is used to form a low voltage device, and the second device region is used to form a high voltage device, where the operating voltage of the low voltage device is less than the operating voltage of the high voltage device.
The fin 510 is used to provide a channel of a fin field effect transistor. The projection of the gate structure formed later on the substrate 100 is orthogonal to the projection of the fin 110 on the substrate 100, and therefore, the fin 110 includes a channel region 10a and non-channel regions 10b located at two sides of the channel region 10a along the extending direction.
The channel region 10a is used to form a gate structure at a position so that the channel is turned on or off by the gate structure, and the non-channel region 10b is used to form a source-drain doped layer.
In this embodiment, along the extending direction of the fin 110, adjacent channel regions 10A in the first device region 100A have a first pitch, and adjacent channel regions 10A in the second device region 100B have a second pitch. The pitch here refers to: along the extending direction of the fin 110, the sum of the width (width) of one channel region 10a and the spacing (space) between adjacent channel regions 10 a.
Since the device operation voltage of the first device region 100A is smaller than the device operation voltage of the second device region 100B, the width of the gate structure of the second device region 100B is greater along the extending direction of the fin 110, and accordingly, the width of the channel region 10A of the second device region 100B is greater than the width of the channel region 10A of the first device region 100A, and the second pitch is greater than the first pitch.
Specifically, the second pitch is at least twice as large as the first pitch, so that in the subsequent process of thinning the fin 110 sidewall of the channel region 10a in the second device region 100B, the process window of the thinning is increased, and the process difficulty of the thinning is reduced.
For example, during the thinning process, it is generally necessary to use a shielding layer having a mask opening to define the area of the thinning process, and the second pitch is larger, which correspondingly makes the size of the mask opening and the distance between adjacent mask openings along the extending direction of the fin 110 larger, thereby increasing the process window of the photolithography process used to form the mask opening, and facilitating the thinning process of the exposed fin through the mask opening.
The material of the fin 110 includes silicon, silicon germanium, or a iii-v semiconductor material. The material of the fin 110 depends on the channel conductivity type and performance requirements of the transistor. In this embodiment, the fin 110 is made of silicon.
As an example, the fin 110 and the substrate 100 are integrally formed. Accordingly, the material of the fin 110 is the same as that of the substrate 100, and the material of the fin 110 is silicon.
In this embodiment, the substrate further includes an isolation layer 101 on the substrate 100 at a side of the fin 110, where a top of the isolation layer 101 is lower than a top of the fin 110, and the isolation layer 101 covers a portion of a sidewall of the fin 110.
The isolation layer 101 is used to achieve isolation between different device regions. Specifically, the isolation layer 101 is a shallow trench isolation structure.
The material of the isolation layer 101 is an insulating material. For example, the material of the isolation layer 101 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, and silicon oxycarbonitride. As an example, the material of the isolation layer 101 is silicon oxide.
In the step of forming the fin 110, a fin mask layer is used as an etching mask, and therefore, before forming the isolation layer 101, a fin mask layer (not shown) is formed on top of the fin 110.
As an example, the fin mask layer is removed during the process of forming the isolation layer 101.
Specifically, the step of forming the isolation layer 101 includes: forming an isolation material layer (not shown) on the substrate 100 at the side of the fin 110, wherein the isolation material layer covers the fin mask layer; performing planarization (e.g., chemical mechanical polishing) on the isolation material layer with the top of the fin mask layer as a stop position; removing the fin mask layer after the planarization treatment; and after the fin mask layer is removed, etching back the residual isolation material layer with partial thickness to form an isolation layer.
In other embodiments, according to the process flow of forming the isolation layer, in the step of providing the substrate, a fin mask layer is formed on top of the fin, that is, after the isolation layer is formed, the fin mask layer is remained. Correspondingly, in the process of forming the isolation layer, after flattening the isolation material layer, the fin mask layer is reserved.
Referring to fig. 8 to 12, fig. 8 (a) is a top view of the first device region, fig. 8 (B) is a cross-sectional view along the AA1 direction of fig. 8 (a), fig. 9 is a top view of the second device region, fig. 10 (a) is a cross-sectional view along the BB1 direction of fig. 9, fig. 10 (B) is a cross-sectional view along the CC1 direction of fig. 9, fig. 11 is a top view of the second device region, fig. 12 (a) is a cross-sectional view along the BB1 direction of fig. 11, fig. 12 (B) is a cross-sectional view along the CC1 direction of fig. 11, and in the second device region 100B, the fin portion 110 of the channel region 10a is subjected to a thinning process for reducing the width of the fin portion 110 of the channel region 10 a.
The width of the fin 110 is referred to herein as: the lateral dimension of the fin 110 is along a direction parallel to the surface of the substrate 100 and perpendicular to the direction in which the fin 110 extends.
Further, as shown in fig. 11, fig. 11 shows a sidewall profile of the fin 110 of the channel region 10a before the thinning process by using a dotted line.
When the device operating voltage of the first device region 100A is smaller than the device operating voltage of the second device region 100B and the gate structure is formed subsequently, the gate dielectric layer thickness of the second device region 100B is correspondingly larger than the gate dielectric layer thickness of the first device region 100A, so that the width of the fin portion 110 of the channel region 10A is reduced in the second device region 100B to increase the space between the fin portions 110 of adjacent channel regions 10A, and therefore, when the gate dielectric layer thickness of the second device region 100B is larger than the gate dielectric layer thickness of the first device region 100A, the process window for forming the gate structure in the gate opening of the second device region 100B subsequently is increased, thereby improving the coverage capability or filling capability of the gate structure between the fin portions 110, further being beneficial to improving the formation quality of the gate structure and correspondingly improving the performance of the semiconductor structure.
In this embodiment, the isolation layer 101 is formed on the substrate 100, so in the second device region 100B, the fin portion 110 of the 10a exposed by the isolation layer 101 is thinned.
Compared with the scheme of performing the thinning treatment before forming the isolation layer, in this embodiment, the aspect ratio of the space enclosed by the fin portion 110 exposed from the isolation layer 101 and the isolation layer 101 is smaller, which is favorable for reducing the process difficulty of the thinning treatment and improving the process effect of the thinning treatment, so that the width of the fin portion 110 of the channel region 10a after the thinning treatment is favorable for precisely controlling.
It should be noted that, in the thinning process, only the width of the fin portion 110 of the channel region 10a exposed by the isolation layer 101 is reduced, and the fin portion 110 covered by the isolation layer 101 maintains the initial width due to the protection of the isolation layer 101, which is beneficial to ensuring the mechanical strength of the entire fin portion 110.
It should be noted that, only the fin portion 110 of the channel region 10a is thinned, and the fin portion 110 of the non-channel region 10b is not thinned, so that the fin portion 110 of the non-channel region 10b maintains the initial width. And subsequently, forming source-drain doped layers in the fin portions 110 at two sides of the pseudo gate structure, wherein the source-drain doped layers are correspondingly formed in the fin portions 110 of the non-channel region 10b, and the influence on the source-drain doped layers is correspondingly reduced because the width of the fin portions 110 of the non-channel region 10b is not reduced, so that the formation quality and the formation volume of the source-drain doped layers are favorably ensured, and the performance of the source-drain doped layers is further ensured.
In addition, at this time, only the isolation layer 101 and the fin portion 110 are formed on the substrate 100, and fewer components are formed on the substrate 100, so that compared with a scheme of performing thinning treatment on the fin portion of the channel region through the gate opening after removing the dummy gate structure to form the gate opening, the thinning treatment is performed before forming the dummy gate structure, which is beneficial to reducing the process complexity of the thinning treatment (for example, the difficulty of forming the shielding layer for defining the thinning treatment region is lower).
Moreover, before the dummy gate structure is formed, the fin portion 110 of the channel region 10a is thinned, so that the modification to the existing process is small and the process compatibility is high.
Specifically, in the second device region 100B, the step of thinning the fin 110 of the channel region 10a includes: as shown in fig. 8 to 10, a shielding layer 200 is formed on the substrate 100 to cover the fin 110, a mask opening 210 located in the second device region 100B is formed in the shielding layer 200, and the mask opening 210 exposes the fin 110 of the channel region 10 a; as shown in fig. 11 to 12, the fin portion 110 exposed by the mask opening 210 is thinned by using the shielding layer 200 as a mask.
The shielding layer 200 may be any material that can be used as a mask, and the material of the shielding layer 200 is selected as follows: the fin portion 110 and the shielding layer 200 have an etching selectivity ratio, and the process of removing the shielding layer 200 has less damage to the fin portion 110 and the substrate 100.
Only the isolation layer 101 and the fin 110 are formed on the substrate 100, which correspondingly increases the flexibility in selecting the material of the shielding layer 200. As an example, the material of the shielding layer 200 is photoresist.
In other embodiments, the shielding layer may also include an anti-reflective coating layer, and a photoresist layer on top of the anti-reflective coating layer, or the shielding layer may include a filler layer, an anti-reflective coating layer on top of the filler layer, and a photoresist layer on top of the anti-reflective coating layer, or the shielding layer may include a spin-on-oxide layer, and a photoresist layer on top of the spin-on-oxide layer. Wherein, the material of the anti-reflection coating may include silicon-containing anti-reflection coating (Si-ARC) material, and the material of the filling layer may be spin-on carbon (SOC).
As is clear from the foregoing description, the second pitch is at least twice as large as the first pitch, and therefore, the opening size of the mask openings 210 is larger, and the distance between the adjacent mask openings 210 is also larger, which increases the process window of the photolithography process used in forming the mask openings 210.
In this embodiment, an etching process is used to thin the sidewalls of the fin portion 110 of the channel region 10 a.
When the etching selectivity of the etching process to the fin 110 and the isolation layer 101 is too small, the isolation layer 101 is easily damaged during the thinning process, so that the thickness of the isolation layer 101 is reduced, and the flatness of the top surface of the isolation layer 101 is reduced, which not only easily reduces the electrical isolation effect of the isolation layer 101, but also affects the effective height of the fin 110 of the channel region 10a, thereby adversely affecting the performance of the semiconductor structure. For this reason, in this embodiment, the etching process has an etching selectivity ratio of the fin 110 to the isolation layer 101 of greater than 5:1.
The effective height of the fin 110 refers to: the height of the fin 110 covered by the gate structure.
Specifically, the etching process includes one or both of a dry etching process and a wet etching process.
It should be noted that, by adjusting the etching parameters, the etching process can meet the process requirement with respect to the etching selection ratio of the fin portion 110 to the isolation layer 101. Moreover, when the dry etching process is adopted, by adjusting the etching parameters, the ratio of the longitudinal etching rate to the transverse etching rate can be adjusted, so that the sidewall of the fin portion 110 of the channel region 10a is thinned.
In the step of thinning the fin 110 of the channel region 10a, the single-side thinning amount d (as shown in fig. 12 (a)) of the fin 110 is not too small or too large. If the single-side thinning amount d of the fin portion 110 is too small, the effect of increasing the space between the fin portions 110 of the adjacent channel regions 10a is not good, so that the effect of increasing the process window for forming the gate structure in the second device region 100B is not good; if the single-side thinning amount d of the fin portion 110 is too large, the width of the effective fin portion of the channel region 10a is easily caused to be too small, which not only easily causes the electrical performance of the device to be offset, but also easily reduces the mechanical strength of the effective fin portion of the channel region 10a, and increases the probability of deformation of the effective fin portion of the channel region 10 a. For this reason, in the step of thinning the fin 110 of the channel region 10a in the second device region 100B, the single-side thinning amount d of the fin 110 is 1 nm to 3 nm. For example, the single-sided thinning d of the fin 110 is 1.5 nm, 2 nm or 2.5 nm. The fin exposed from the isolation layer 101 serves as an effective fin.
In this embodiment, the thinning of the fin portion 110 of the channel region 10a further includes removing the shielding layer 200, so as to prepare for a subsequent process.
It should be noted that, compared to the height of the fin 110, the single-sided thinning d of the fin 110 is smaller, so, even if the height of the fin 110 is reduced due to the exposure of the top of the fin 110 to the thinning environment during the thinning process, the height of the fin 110 is reduced, and the influence of the height of the fin 110 on the device performance is smaller.
In other embodiments, when the fin mask layer is formed on the top of the fin, the fin mask layer may protect the top of the fin during the thinning process, thereby facilitating reduction of the influence on the height of the fin. Correspondingly, in this embodiment, after the fin portion of the channel region is thinned, removing the fin portion mask layer is further included, so as to prepare for a subsequent process.
Referring to fig. 13 to 19, fig. 13 (a) is a top view of the first device region, fig. 13 (b) is a top view of fig. 13 (a) along the direction AA1, fig. 14 is a top view of the second device region, fig. 15 (a) is a cross-sectional view of fig. 14 along the direction BB1, fig. 15 (b) is a cross-sectional view of fig. 14 along the direction CC1, fig. 16 is a top view of the first device region, fig. 17 (a) is a cross-sectional view of fig. 16 along the direction AA1, fig. 17 (b) is a cross-sectional view of fig. 16 along the direction DD1, fig. 18 is a top view of the second device region, fig. 19 (a) is a cross-sectional view of fig. 18 along the direction BB1, fig. 19 (b) is a cross-sectional view of fig. 18 along the direction BB1, after the fin 110 of the channel region 10a is thinned, a dummy gate structure 320 is formed on the substrate, the dummy gate structure 320 spans the channel region 10a portion 110 and covers a portion of the top and a portion of the sidewall of the channel region 10a, the dummy gate structure 320 includes an oxide layer 300 and a gate layer 300.
The step of forming the dummy gate structure 320 will be described in detail with reference to the accompanying drawings.
Referring to fig. 13 to 15 in combination, a gate oxide layer 300 is formed on the surface of the fin portion 110 exposed by the isolation layer 101.
The gate oxide 300 is used as a portion of the gate dielectric layer of the second device region 100B. In addition, when the dummy gate layer 310 is removed later, the gate oxide layer 300 can act as an etching stop layer, thereby reducing damage to the fin 110.
Compared with the scheme that the dummy gate layer is removed to form the gate opening and then the thinning treatment is performed through the gate opening, in this embodiment, before the gate oxide layer 300 is formed, the thinning treatment is performed on the fin portion 110 of the channel region 10a in the second device region 100B, so that the gate oxide layer 300 of the second device region 100B does not need to be removed later, thereby simplifying the process steps, reducing the probability of damage to the fin portion 110 of the second device region 100B, and having high compatibility with the current process.
In this embodiment, an in-situ steam generation (in-situ stream generation, ISSG) oxidation process is adopted to form the gate oxide layer 300 on the surface of the fin portion 110, so that the density and thickness uniformity of the gate oxide layer 300 are improved.
In this embodiment, the material of the fin portion 110 is silicon, the gate oxide layer 300 is formed by oxidizing the fin portion 110, and the material of the gate oxide layer 300 is silicon oxide.
As shown in fig. 15, after the gate oxide layer 300 is formed in the second device region 100B, compared to the fin 110 that is not subjected to the thinning process, the remaining space between the fin 110 subjected to the thinning process is larger, and the subsequent gate structure is also formed between the adjacent fin 110, so that the process window for forming the gate structure in the second device region 100B is larger.
In this embodiment, a part of the fin portion 110 is used as the bottom fin portion, the remaining fin portion 110 is used as the effective fin portion, and the isolation layer 101 covers the sidewall of the bottom fin portion and exposes the effective fin portion. In the second device region 100B, the gate oxide layer 300 covers the top of the bottom fin exposed by the effective fin, so as to reduce the influence of the bottom fin on the device performance.
Referring to fig. 16 to 19 in combination, a dummy gate layer 310 is formed on the gate oxide layer 300 across the fin 110 of the channel region 10 a.
The dummy gate layer 310 is used to occupy a space for a subsequently formed gate structure, and the dummy gate layer 310 and the gate oxide layer 300 form a dummy gate structure 320.
In this embodiment, the material of the dummy gate layer 310 is amorphous silicon. Amorphous silicon is easily removed, and the process of removing amorphous silicon has less loss to the isolation layer 101. In other embodiments, the material of the dummy gate layer may be polysilicon or amorphous carbon, or other suitable materials.
In this embodiment, the material layer corresponding to the dummy gate layer 310 is patterned by an etching process, so as to form the dummy gate layer 310.
As an example, after the material layer corresponding to the dummy gate layer 310 is patterned by an etching process, the gate oxide layer 300 exposed by the dummy gate layer 310 is remained.
In this embodiment, along the extending direction of the fin portion 110, the width of the dummy gate layer 310 of the second device region 100B is greater than the width of the dummy gate layer 310 of the first device region 100A.
Referring to fig. 20 to 23, fig. 20 is a top view of a first device region, fig. 21 (a) is a cross-sectional view of fig. 20 along the AA1 direction, fig. 21 (b) is a cross-sectional view of fig. 20 along the DD1 direction, fig. 22 is a top view of a second device region, fig. 23 (a) is a cross-sectional view of fig. 22 along the BB1 direction, and fig. 23 (b) is a cross-sectional view of fig. 22 along the CC1 direction, source and drain doped layers 330 are formed in the fin portions 110 on both sides of the dummy gate layer 310.
The source-drain doped layer 330 is used as a source or drain region of the formed transistor.
Specifically, the fin portions 110 at two sides of the dummy gate layer 310 are etched, after forming a groove in the fin portion 110, the source-drain doped layer 330 is formed in the groove through an epitaxial process.
The doping type of the source/drain doping layer 330 is the same as the channel conductivity type of the corresponding transistor. When the transistor is a PMOS transistor, the material of the source-drain doped layer 330 includes silicon germanium doped with P-type ions, including B, ga or In. When the transistor is an NMOS transistor, the material of the source-drain doped layer 330 includes silicon or silicon carbide doped with N-type ions including P, as or Sb.
It should be noted that, before forming the source-drain doped layer 330, the forming method further includes: a sidewall (not shown) is formed on the sidewall of the dummy gate layer 310.
The side walls are used for protecting the side walls of the dummy gate layer 310 and the side walls of the gate structure formed later, and also for defining the formation positions of the source/drain doped layers 330. The description of the side wall is not repeated here.
It should be further noted that, according to the process requirement, after the side wall is formed, the gate oxide layer 300 exposed from the side wall may be removed, or the gate oxide layer 300 exposed from the side wall may be retained. Correspondingly, when the gate oxide layer 300 exposed from the sidewall is reserved, the fin portions 110 at two sides of the dummy gate layer 310 are etched, and in the step of forming the grooves in the fin portions 110, the gate oxide layer 300 at two sides of the dummy gate layer 310 is also etched.
Referring to fig. 24 to 25, fig. 24 (a) is a top view of a first device region, fig. 24 (b) is a cross-sectional view of fig. 24 (a) along the AA1 direction, fig. 25 (a) is a top view of a second device region, and fig. 25 (b) is a cross-sectional view of fig. 25 (a) along the CC1 direction, an interlayer dielectric layer 102 is formed on the substrate 100 to cover the source/drain doped layer 330, the interlayer dielectric layer 102 covering the sidewalls of the dummy gate layer 310 and exposing the top of the dummy gate layer 310.
The interlayer dielectric layer 102 is used to achieve electrical isolation between adjacent devices, and the interlayer dielectric layer 102 is also used to define the dimensions and locations of subsequently formed gate structures.
The interlayer dielectric layer 102 is made of an insulating material. In this embodiment, the material of the interlayer dielectric layer 102 is silicon oxide. In other embodiments, the material of the interlayer dielectric layer may be another dielectric material such as silicon nitride or silicon oxynitride.
Specifically, after forming an interlayer dielectric material layer covering the dummy gate layer 310, a planarization process (for example, a chemical mechanical polishing process) is performed on the interlayer dielectric material layer until the top of the dummy gate layer 310 is exposed, and the remaining interlayer dielectric material layer is used as the interlayer dielectric layer 102.
Referring to fig. 26 to 33, fig. 26 is a top view of a first device region, fig. 27 (a) is a cross-sectional view of fig. 26 along the AA1 direction, fig. 27 (B) is a cross-sectional view of fig. 26 along the DD1 direction, fig. 28 is a top view of a second device region, fig. 29 (a) is a cross-sectional view of fig. 28 along the BB1 direction, fig. 29 (B) is a cross-sectional view of fig. 28 along the CC1 direction, fig. 30 is a top view of a first device region, fig. 31 (a) is a cross-sectional view of fig. 30 along the AA1 direction, fig. 31 (B) is a cross-sectional view of fig. 30 along the DD1 direction, fig. 32 is a cross-sectional view of fig. 32 along the BB1 direction, fig. 33 (B) is a cross-sectional view of fig. 32 along the CC1 direction, a dummy gate structure 320 of the first device region 100A, and a dummy gate layer 310 of the second device region 100B are removed, and a gate opening 350 is formed in the interlayer dielectric layer 102.
The gate opening 350 is used to provide a spatial location for the subsequent formation of a gate structure.
Referring to fig. 26 to 29 in combination, the dummy gate layer 310 of the first device region 100A and the second device region 100B is removed, and a gate opening 350 is formed in the interlayer dielectric layer 102.
Specifically, one or both of a dry etching process and a wet etching process may be used to remove the dummy gate layer 310. In the process of removing the dummy gate layer 310, the top of the gate oxide layer 300 is used as an etching stop position, so as to reduce damage to the fin 110 in the gate opening 350.
Referring to fig. 30 to 33, after removing the dummy gate layer 310, the gate oxide layer 300 exposed by the gate opening 350 of the first device region 100A is removed, so as to expose the surface of the fin portion 110 of the channel region 10A.
As is clear from the foregoing description, the larger the operating voltage of the device, the larger the corresponding thickness of the gate dielectric layer, and the device operating voltage of the first device region 100A is smaller than the device operating voltage of the second device region 100B, so that the gate oxide layer 300 of the first device region 100A is removed, so that the gate dielectric layer with a smaller thickness is formed in the second device region 100B later.
Specifically, taking the masking layer 200 (as shown in fig. 8 to 10) used in the foregoing thinning process as the first masking layer as an example, the step of removing the gate oxide layer 300 exposed by the gate opening 350 of the first device region 100A includes: forming a second shielding layer 340 in the second device region 100B, where the second shielding layer 340 covers the interlayer dielectric layer 102 and fills the gate opening 350; etching to remove the gate oxide layer 300 in the gate opening 350 of the first device region 100A by using the second shielding layer 340 as a mask; the second blocking layer 340 is removed.
The second shielding layer 340 may be made of any material that can be used as a mask. As an example, the material of the second shielding layer 340 is photoresist.
As an example, a dry etching process may be used to remove the gate oxide layer 300 exposed by the gate opening 350 of the first device region 100A, so as to improve the sidewall flatness of the gate opening 350 after removing the gate oxide layer 300.
Referring to fig. 34 to 37, fig. 34 is a top view of the first device region, fig. 35 (a) is a cross-sectional view of fig. 34 along the AA1 direction, fig. 35 (b) is a cross-sectional view of fig. 34 along the DD1 direction, fig. 36 is a top view of the second device region, fig. 37 (a) is a cross-sectional view of fig. 36 along the BB1 direction, and fig. 37 (b) is a cross-sectional view of fig. 36 along the CC1 direction, a gate structure 450 is formed in the gate opening 350.
The gate structure 450 and the gate oxide 300 under the gate structure 450 are commonly used to control the on or off of a channel.
In this embodiment, the gate structure 450 is a metal gate structure. Thus, the gate structure 450 includes a high-k gate dielectric layer 410, and a gate electrode layer 400 overlying the high-k gate dielectric layer 410.
In the first device region 100A, the high-k gate dielectric layer 410 is used as a gate dielectric layer, and in the second device region 100B, the high-k gate dielectric layer 410 and the gate oxide layer 300 are used together as a gate dielectric layer, so that the gate dielectric layer thickness of the second device region 100B is greater than the gate dielectric layer thickness of the first device region 100A.
The gate dielectric layer is used to isolate the gate electrode layer 400 from the channel.
The material of the high-k gate dielectric layer 410 is a high-k dielectric material, where the high-k dielectric material refers to a dielectric material having a relative dielectric constant greater than that of silicon oxide. Specifically, the material of the high-k gate dielectric layer 410 may be selected from HfO 2 、ZrO 2 HfSiO, hfSiON, hfTaO, hfTiO, hfZrO or Al 2 O 3 Etc. As an example, the material of the high-k gate dielectric layer 410 is HfO 2 。
The gate electrode layer 400 is used to electrically draw out the gate structure 450. The material of the gate electrode layer 400 includes one or more of TiN, taN, ta, ti, tiAl, W, al, tiSiN and TiAlC.
As can be seen from the foregoing description, in the gate opening 350 of the second device region 100B, the remaining space between the fins 110 is larger, so that the process window for forming the gate electrode layer 400 is increased, and the coverage or filling capability of the gate electrode layer 400 between the adjacent fins 110 is further improved.
As an example, the gate electrode layer 400 includes a work function layer and an electrode layer covering the work function layer. In other embodiments, the gate electrode layer may also include only a work function layer. Wherein the work function layer is used to adjust the operating voltage of the formed transistor. It will be appreciated that the material, thickness and number of layers of the work function layer may be different for each device region depending on the performance requirements of the transistors for the different device regions.
It should be noted that, in this embodiment, the gate dielectric layer of the first device region 100A only includes the high-k gate dielectric layer 410, and the gate dielectric layer of the second device region 100B includes the gate oxide layer 300 and the high-k gate dielectric layer 410 covering the gate oxide layer 300, so that the thickness of the gate dielectric layer of the second device region 100B is greater than that of the gate dielectric layer of the first device region 100A, so as to meet different requirements of the device operating voltages of the first device region 100A and the second device region 100B.
In another embodiment, before forming the high-k gate dielectric layer, taking the gate oxide layer exposed by the gate opening of the second device region as the first gate oxide layer as an example, the method may further include: and forming a second gate oxide layer on the surface of the fin part exposed by the gate opening in the first device region. Wherein, the second gate oxide thickness is less than the first gate oxide thickness because the device operating voltage of the first device region is less than the device operating voltage of the second device region.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (17)

1. A semiconductor structure, comprising:
the substrate comprises a first device region and a second device region, wherein the device working voltage of the first device region is smaller than that of the second device region;
the fin parts are respectively positioned on the substrates of the first device region and the second device region, the fin parts comprise a channel region and non-channel regions positioned at two sides of the channel region along the extending direction of the fin parts, part of the fin parts with the height being used as bottom fin parts, the fin parts with the rest heights being used as effective fin parts, the effective fin parts are positioned at the tops of the bottom fin parts, wherein the side walls of the effective fin parts of the channel region in the second device region are retracted inwards relative to the side walls of the fin parts of the non-channel regions at the same side, the width of the effective fin parts of the channel region in the second device region is smaller than the width of the fin parts of the non-channel region, and the width of the effective fin parts of the channel region in the first device region is larger than the width of the effective fin parts of the channel region in the second device region.
The isolation layer is positioned on the substrate at the side part of the fin part, covers the side wall of the bottom fin part and exposes the effective fin part;
the grid structure is positioned on the isolation layer and spans the effective fin part, and comprises a grid dielectric layer covering the top and the side wall of the effective fin part of the channel region and a grid electrode layer covering the grid dielectric layer, and the thickness of the grid dielectric layer of the second device region is larger than that of the first device region;
the side walls are positioned at two sides of the grid structure and cover the side walls of the grid structure;
the source-drain doped layer is positioned in the effective fin parts at two sides of the grid structure and is positioned at one side of the side wall far away from the grid structure.
2. The semiconductor structure of claim 1, in which in the second device region, an effective fin sidewall of the channel region is recessed relative to a bottom fin sidewall of the channel region on the same side.
3. The semiconductor structure of claim 1, in which an effective fin sidewall of the channel region is recessed 1 nanometer to 3 nanometers relative to a fin sidewall of the non-channel region on the same side.
4. The semiconductor structure of claim 1, wherein adjacent gate structures in the first device region have a first pitch and adjacent gate structures in the second device region have a second pitch along an extension direction of the fin, the second pitch being at least twice the first pitch.
5. The semiconductor structure of claim 1, wherein the material of the gate dielectric layer comprises HfO 2 、ZrO 2 、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、Al 2 O 3 、SiO 2 And La (La) 2 O 3 One or more of the following;
the material of the gate electrode layer includes one or more of TiN, taN, ta, ti, tiAl, W, al, tiSiN and TiAlC.
6. The semiconductor structure of claim 1, wherein the material of the substrate comprises silicon, germanium, silicon carbide, gallium arsenide, indium gallium, silicon on insulator, or germanium on insulator.
7. The semiconductor structure of claim 1, wherein a material of the fin comprises silicon, silicon germanium, or a iii-v semiconductor material.
8. The semiconductor structure of claim 1, wherein a material of the isolation layer comprises one or more of silicon oxide, silicon nitride, silicon oxynitride, and silicon oxycarbonitride.
9. The semiconductor structure of claim 1, wherein the first device region is for forming a core device and the second device region is for forming a high voltage device or for forming an input/output device.
10. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a first device region and a second device region, the device working voltage of the first device region is smaller than that of the second device region, and the fin comprises a channel region along the extending direction of the fin;
in the second device region, thinning the fin part of the channel region to reduce the width of the fin part of the channel region;
after thinning the fin part of the channel region, forming a pseudo gate structure on the substrate, wherein the pseudo gate structure spans the fin part of the channel region and covers part of the top and part of the side wall of the fin part of the channel region, and the pseudo gate structure comprises a gate oxide layer and a pseudo gate layer covering the gate oxide layer;
forming source-drain doping layers in fin parts on two sides of the pseudo gate layer;
Forming an interlayer dielectric layer covering the source-drain doped layer on the substrate, wherein the interlayer dielectric layer covers the side wall of the pseudo gate layer and exposes the top of the pseudo gate layer;
removing the pseudo gate structure of the first device region and the pseudo gate layer of the second device region, and forming a gate opening in the interlayer dielectric layer;
a gate structure is formed in the gate opening.
11. The method of claim 10, wherein in the step of providing a base, the base further comprises an isolation layer on the substrate at a side of the fin, the isolation layer covering a portion of a sidewall of the fin;
and in the second device region, thinning the fin part of the channel region exposed by the isolation layer.
12. The method of claim 11, wherein in the step of providing a substrate, a fin mask layer is formed on top of the fin;
and after thinning the fin part of the channel region, removing the mask layer of the fin part before forming the pseudo gate structure on the substrate.
13. The method of claim 11, wherein the fin portion of the channel region is thinned using an etching process, the etching process comprising one or both of a dry etching process and a wet etching process.
14. The method of claim 11, wherein the fin portion of the channel region is thinned by an etching process, the etching process having an etch selectivity to the fin portion and the isolation layer greater than 5:1.
15. The method of forming a semiconductor structure of claim 10, wherein thinning the fin of the channel region comprises: forming a shielding layer covering the fin part on the substrate, wherein a mask opening positioned in the second device region is formed in the shielding layer, and the mask opening exposes the fin part of the channel region;
and thinning the fin part exposed from the mask opening by taking the shielding layer as a mask.
16. The method of claim 10, wherein in the step of thinning the fin portion of the channel region, a single-sided thinning amount of the fin portion is 1 nm to 3 nm.
17. The method of forming a semiconductor structure of claim 10, wherein adjacent ones of the channel regions in the first device region have a first pitch and adjacent ones of the channel regions in the second device region have a second pitch along an extension direction of the fin, the second pitch being at least twice the first pitch.
CN202111258439.0A 2021-10-27 2021-10-27 Semiconductor structure and forming method thereof Pending CN116031259A (en)

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