CN115440705A - 集成采样结构的垂直型半导体结构及其制作方法 - Google Patents
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Abstract
本发明提供了一种集成采样结构的垂直型半导体结构及其制作方法,集成采样结构的垂直型半导体结构包括:垂直型半导体结构原胞、采样原胞、控制电极、第一电极、第二电极及采样电极。根据本发明的实施例,一则,采样电极可对第一电极与第二电极之间的电压差进行实时采样;采样原胞的第一/二P型扩散区与第二N型基区之间都形成PN结,该PN结形成了阻挡采样电极端电子发射的势垒,因而,将采样电极的电压信号输入到保护电路,保护电路在同时判断垂直型半导体结构原胞处于打开状态时,可安全快速检测垂直型半导体结构是否处于退饱和状态。二则,在采样电极与第一电极之间串联采样电阻,采样电极正电压会增大该势垒高度,可保证采样原胞稳定工作。
Description
技术领域
本发明涉及半导体器件技术领域,尤其涉及一种集成采样结构的垂直型半导体结构及其制作方法。
背景技术
垂直型半导体结构,例如IGBT(Insulated Gate Bipolar Transistor,绝缘栅双极型晶体管)不同于平面型半导体结构,通过垂直于衬底的沟道,可有效提升载流子浓度,降低通态压降和提升电流密度,目前逐渐成为占主导地位的功率器件。IGBT是由BJT(双极型三极管)和MOS(绝缘栅型场效应管)组成的复合全控型电压驱动式功率半导体器件,结合了MOS电压控制和BJT电导调制电流的特性,具有输入阻抗高、开关损耗小、速度快、电压驱动功率小等特点,广泛地应用于电力输变送、高速列车牵引、工业驱动、清洁能源等诸多领域。
垂直型半导体结构因自身具有高电压大电流的特点,在应用过程中会面临短路的情况,即同时承受高电压大电流,器件会在微秒级时间内因发热烧毁。
当前相关短路保护常用方案有退饱和检测方法和利用霍尔电流传感器检测沟道电流并实施保护。例如,IGBT的退饱和检测方法是对IGBT的VCE电压进行直接采样,利用IGBT在短路时的退饱和特性检测其是否处于短路状态;霍尔电流传感器是利用IGBT短路时时电流会远远超过IGBT正常工作电流来判断其是否处于短路状态。
霍尔电流传感器具有延时较高,体积大的劣势;而退饱和检测方法,外围电路需对高于几百伏的强电进行采样,需要相应的高压二极管及其他防止高电压直接进入驱动的保护措施,外围电路成本较高。
发明内容
本发明的发明目的是提供一种集成采样结构的垂直型半导体结构及其制作方法,以解决相关技术中的问题。
为实现上述目的,本发明的第一方面提供一种集成采样结构的垂直型半导体结构,包括:
垂直型半导体结构原胞,包括:第一N型基区、伸入所述第一N型基区内的P型阱区、自所述P型阱区伸入所述第一N型基区的控制区、位于所述P型阱区上部的P型欧姆接触区与N型源区,所述N型源区位于所述P型欧姆接触区的两侧,以及位于所述第一N型基区下方的第一N型缓冲层;
采样原胞,包括:第二N型基区、伸入所述第二N型基区内的第一P型扩散区与第二P型扩散区,所述第一P型扩散区与所述第二P型扩散区之间形成电子通道、位于所述电子通道上部的N型欧姆接触区,以及位于第二N型基区下方的第二N型缓冲层;
控制电极,连接于所述垂直型半导体结构原胞的控制区;
第一电极,连接于所述垂直型半导体结构原胞的P型欧姆接触区与N型源区,以及所述采样原胞的第一P型扩散区与第二P型扩散区;
第二电极,连接于所述垂直型半导体结构原胞的第一N型缓冲层与所述采样原胞的第二N型缓冲层;
采样电极,连接于所述采样原胞的N型欧姆接触区。
可选地,所述垂直型半导体结构为IGBT,所述第一电极为发射极;所述IGBT原胞还包括:位于所述第一N型缓冲层下方的第一P型集电区,所述采样原胞还包括:位于所述第二N型缓冲层下方的第二P型集电区;所述第二电极为集电极,连接于所述IGBT半导体结构原胞的第一P型集电区与所述采样原胞的第二P型集电区。
可选地,所述垂直型半导体结构为VDMOS,所述第一电极为源极,所述第二电极为漏极。
可选地,所述集成采样结构的垂直型半导体结构还包括:采样电阻,连接于所述采样电极与所述第一电极之间。
可选地,所述垂直型半导体结构原胞具有并联的多个,所述采样原胞具有并联的多个。
可选地,所述第二N型基区内具有第一扩散阻挡区与第二扩散阻挡区,所述第一扩散阻挡区与所述第二扩散阻挡区分别邻接所述电子通道;所述第一P型扩散区位于所述第一扩散阻挡区远离所述电子通道的一侧,所述第二P型扩散区位于所述第二扩散阻挡区远离所述电子通道的一侧。
可选地,所述第一扩散阻挡区与所述第二扩散阻挡区包括:导电材料区与位于所述导电材料区的侧壁的绝缘材料层。
可选地,所述导电材料区与所述第一电极电连接。
可选地,所述第一扩散阻挡区与所述第二扩散阻挡区包括:绝缘材料区与位于所述绝缘材料区的侧壁的绝缘材料层。
本发明的第二方面提供一种集成采样结构的垂直型半导体结构的制作方法,包括:
提供半导体衬底,所述半导体衬底包括N型基区,所述N型基区包括第一N型基区与第二N型基区,所述第一N型基区用于形成垂直型半导体结构原胞,所述第二N型基区用于形成采样原胞;在所述第一N型基区形成第一沟槽,在所述第一沟槽内形成控制区;
在所述第一N型基区内形成P型阱区,所述P型阱区伸入所述第一N型基区的深度小于所述第一沟槽的深度;在所述第二N型基区内形成第一P型扩散区与第二P型扩散区,所述第一P型扩散区与所述第二P型扩散区之间形成电子通道;
在所述P型阱区的上部形成P型欧姆接触区与N型源区,所述N型源区位于所述P型欧姆接触区的两侧;在所述电子通道的上部形成N型欧姆接触区;
在所述第一N型基区下方形成第一N型缓冲层;在所述第二N型基区下方形成第二N型缓冲层;
在所述控制区上形成控制电极;在所述P型欧姆接触区、所述N型源区、所述第一P型扩散区以及所述第二P型扩散区上形成第一电极;在所述N型欧姆接触区上形成采样电极;在所述第一N型缓冲层与所述第二N型缓冲层上形成第二电极。
可选地,在所述P型阱区的上部形成N型源区与在所述电子通道的上部形成N型欧姆接触区在同一工序中进行;和/或
在所述第一N型基区下方形成第一N型缓冲层与在所述第二N型基区下方形成第二N型缓冲层在同一工序中进行;和/或
在所述控制区上形成控制电极,在所述P型欧姆接触区、所述N型源区、所述第一P型扩散区以及所述第二P型扩散区上形成第一电极,在所述N型欧姆接触区上形成采样电极在同一工序中进行。
可选地,所述垂直型半导体结构为IGBT,所述第一电极为发射极;
所述制作方法还包括:在所述第一N型缓冲层下方形成第一P型集电区,同时在所述第二N型缓冲层下方形成第二P型集电区;
所述第二电极为集电极,连接于所述IGBT半导体结构原胞的第一P型集电区与所述采样原胞的第二P型集电区。
可选地,所述垂直型半导体结构为VDMOS,所述第一电极为源极,所述第二电极为漏极。
可选地,在所述第二N型基区内形成第一P型扩散区与第二P型扩散区步骤前,在所述第二N型基区内分别形成第一扩散阻挡区与第二扩散阻挡区,所述第一扩散阻挡区与所述第二扩散阻挡区分别邻接所述电子通道。
可选地,在所述第二N型基区内分别形成第一扩散阻挡区与第二扩散阻挡区包括:在所述第二N型基区形成第二沟槽与第三沟槽,在所述第二沟槽内形成第一扩散阻挡区,在所述第三沟槽内形成第二扩散阻挡区。
可选地,在所述第一N型基区形成第一沟槽与在所述第二N型基区形成第二沟槽与第三沟槽在同一工序中进行;在所述第一沟槽内形成控制区、在所述第二沟槽内形成第一扩散阻挡区,以及在所述第三沟槽内形成第二扩散阻挡区在同一工序中进行。
与现有技术相比,本发明的有益效果在于:
一则,采样电极可以对第一电极与第二电极之间的电压差进行实时采样;采样原胞的第一P型扩散区与第二N型基区之间,以及第二P型扩散区与第二N型基区之间都形成PN结,该PN结形成了阻挡采样电极端电子发射的势垒,因而,将采样电极的电压信号输入到保护电路可代替直接对VCE强电进行采样,保护电路在同时判断垂直型半导体结构原胞处于打开状态时,可安全快速检测垂直型半导体结构是否处于退饱和状态,另外,简化了外围电路。二则,采样原胞中,在采样电极与第一电极之间串联采样电阻可将电流信号转化为电压信号,当采样电极与第一电极之间的电压差较大时,该电压差为正值,电子通道内具有较高势垒,势垒会阻碍电子发射,使电子通道电流变小,从而降低采样电极与第一电极之间的电压差;采样电极与第一电极之间的电压差降低后,电子通道内势垒降低,电子通道电流变大,从而增大采样电极与第一电极之间的电压差,如此负反馈作用下,使采样电极端电流不会急剧增大,采样原胞功率不会过大而烧坏,从而不会因为引入采样原胞而造成垂直型半导体结构集成结构性能可靠性降低,可保证采样原胞稳定工作。
附图说明
图1是本发明第一实施例的集成采样结构的IGBT的截面结构示意图;
图2是图1的集成采样结构的IGBT的电路图;
图3为对照实验的采样电流随发射极与集电极之间电压差变化关系曲线图;
图4是图1的集成采样结构的IGBT的制作方法的流程图;
图5至图8是图4流程对应的中间结构示意图;
图9是本发明第二实施例的集成采样结构的IGBT的截面结构示意图;
图10是本发明第三实施例的集成采样结构的VDMOS的截面结构示意图。
为方便理解本发明,以下列出本发明中出现的所有附图标记:
集成采样结构的IGBT1、2 IGBT原胞11
第一N型基区110 P型阱区111
控制区112 P型欧姆接触区113
N型源区114 第一N型缓冲层115
第一P型集电区116 采样原胞12
第二N型基区120 第一P型扩散区121
第二P型扩散区122 电子通道123
N型欧姆接触区124 第二N型缓冲层125
第二P型集电区126 发射极13
集电极14 采样电极15
半导体衬底10 N型基区100
层间绝缘层16 第一扩散阻挡区127
第二扩散阻挡区128 源极17
漏极18 集成采样结构的VDMOS3
VDMOS原胞19
具体实施方式
为使本发明的上述目的、特征和优点能够更为明显易懂,下面结合附图对本发明的具体实施例做详细的说明。
图1是本发明第一实施例的集成采样结构的IGBT的截面结构示意图。
参照图1所示,集成采样结构的IGBT1,包括:
IGBT原胞11,包括:第一N型基区110、伸入第一N型基区110内的P型阱区111、自P型阱区111伸入第一N型基区110的控制区112、位于P型阱区111上部的P型欧姆接触区113与N型源区114,N型源区114位于P型欧姆接触区113的两侧、位于第一N型基区110下方的第一N型缓冲层115,以及位于第一N型缓冲层115下方的第一P型集电区116;
采样原胞12,包括:第二N型基区120、伸入第二N型基区120内的第一P型扩散区121与第二P型扩散区122,第一P型扩散区121与第二P型扩散区122之间形成电子通道123、位于电子通道123上部的N型欧姆接触区124、位于第二N型基区120下方的第二N型缓冲层125,以及位于第二N型缓冲层125下方的第二P型集电区126;
控制电极(未图示),连接于IGBT原胞11的控制区112;
发射极13,连接于IGBT原胞11的P型欧姆接触区113与N型源区114,以及采样原胞12的第一P型扩散区121与第二P型扩散区122;
集电极14,连接于IGBT原胞11的第一P型集电区116与采样原胞12的第二P型集电区126;
采样电极15,连接于采样原胞12的N型欧姆接触区124。
本实施例中,IGBT原胞11的控制区112可以包括栅极区以及位于栅极区侧壁的栅极绝缘层。控制电极为栅极,连接于栅极区。
IGBT原胞11的第一N型基区110与采样原胞12的第二N型基区120可以连接在一起。IGBT原胞11的第一N型缓冲层115与采样原胞12的第二N型缓冲层125可以连接在一起。IGBT原胞11的第一P型集电区116与采样原胞12的第二P型集电区126可以连接在一起。
IGBT原胞11的控制区112、P型欧姆接触区113与N型源区114,以及采样原胞12的第一P型扩散区121与第二P型扩散区122,第一P型扩散区121、第二P型扩散区122与N型欧姆接触区124上可以设置层间绝缘层16,发射极13、集电极14以及采样电极15设置在层间绝缘层16上,并通过层间绝缘层16内的开口分别对应连接于P型欧姆接触区113与N型源区114,以及第一P型扩散区121与第二P型扩散区122;第一P型集电区116与第二P型集电区126;N型欧姆接触区124。
图2是图1的集成采样结构的IGBT的电路图。参照图2所示,IGBT的工作过程如下:驱动电路向IGBT原胞11的控制区112施加开启电压后,IGBT原胞11的N型源区114与第一N型缓冲层115之间形成电子沟道,集电极14的电压高于发射极13的电压,从而IGBT原胞11导通,处于打开状态。第一P型集电区116向第一N型缓冲层115内注入空穴,进行导电调制,以降低器件的通态电压。
采样结构的工作过程如下:采样原胞12的第一P型扩散区121与第二P型扩散区122的电位都与发射极13的电位相同,集电极14的电压高于发射极13的电压,电子通道123导通。由于第一P型扩散区121第二N型基区120之间,以及第二P型扩散区122与第二N型基区120之间都形成PN结,该PN结形成了阻挡采样电极15电子发射的势垒,因而,电子通道123的电流较小,采样电极15的电压信号较小。将采样电极15的电压信号输入到保护电路,当保护电路检测到该电压信号大于预设电压,同时判断IGBT原胞11具有导通电流时,可判断IGBT原胞11处于退饱和状态,此时,可断开保护电路。
上述采样结构工作过程中,参照图2所示,在采样电极15与发射极13之间串联采样电阻,可将电流信号转化为电压信号。当采样电极15与发射极13之间的电压差较大时,该电压差为正值,电子通道123内具有较高势垒,势垒会阻碍电子发射,使电子通道123的电流变小,从而降低采样电极15与发射极13之间的电压差;采样电极15与发射极13之间的电压差降低后,电子通道123内势垒降低,电子通道123的电流变大,从而增大采样电极15与发射极13之间的电压差,如此形成负反馈。在上述负反馈作用下,采样电极15的电流不会急剧增大,采样原胞12功率不会过大而烧坏,从而不会因为引入采样原胞12而造成IGBT集成结构性能可靠性降低。
为验证上述结论,本发明进行了对照实验。图3为对照实验的采样电流随发射极与集电极之间电压差变化关系曲线图。样品1为采样电极15与发射极13之间的电压差恒为0V,样品2为采样电极15与发射极13之间的电压差恒为负aV,样品3为采样电极15与发射极13之间的电压差恒为负bV,0<a<b,样品4为采样电极15与发射极13之间串联采样电阻。
参照图3可以看出,样品1、2、3的采样电流都会呈指数级急剧增大。样品4的采样电流不会急剧增大。
图3中,母线电压为电路的额定工作电压。
一个可选方案中,集成采样结构的IGBT1可以包括采样电阻,采样电阻连接于采样电极15与发射极13之间。其它可选方案中,采样电阻也可以设置在外围电路中。
本实施例中,IGBT原胞11与采样原胞12分别具有一个,换言之,采样原胞12检测一个IGBT原胞11是否处于退饱和状态。其它实施例中,IGBT原胞11可以具有并联的多个,采样原胞12也可以具有并联的多个,以增大IGBT原胞11是否处于退饱和状态检测时的采样电流,提高检测精准度。
本发明一实施例还提供了图1的集成采样结构的IGBT的制作方法。图4是制作方法的流程图。图5至图8是图4流程对应的中间结构示意图。
首先,参照图4的步骤S1与图5所示,提供半导体衬底10,半导体衬底10包括N型基区100,N型基区100包括第一N型基区110与第二N型基区120,第一N型基区110用于形成IGBT原胞11,第二N型基区120用于形成采样原胞12;在第一N型基区110形成第一沟槽,在第一沟槽内形成控制区112。
第一沟槽可采用干法刻蚀形成。本实施例中,控制区112可以包括栅极区以及位于栅极区侧壁的栅极绝缘层。栅极绝缘层可以通过热氧化半导体衬底10形成,栅极区的材料可以为掺杂多晶硅,通过化学气相沉积法形成。
接着,参照图4的步骤S2与图6所示,在第一N型基区110内形成P型阱区111,P型阱区111伸入第一N型基区110的深度小于第一沟槽的深度;在第二N型基区120内形成第一P型扩散区121与第二P型扩散区122,第一P型扩散区121与第二P型扩散区122之间形成电子通道123。
P型阱区111、第一P型扩散区121与第二P型扩散区122都可以采用离子注入法形成。本实施例中,P型阱区111的深度小于第一P型扩散区121与第二P型扩散区122的深度,因而,可以先形成第一P型扩散区121与第二P型扩散区122,再形成P型阱区111。
之后,参照图4的步骤S3与图7所示,在P型阱区111的上部形成P型欧姆接触区113与N型源区114,N型源区114位于P型欧姆接触区113的两侧;在电子通道123的上部形成N型欧姆接触区124。
P型欧姆接触区113、N型源区114、N型欧姆接触区124都可以采用离子注入法形成。P型欧姆接触区113为P型离子重掺杂,N型源区114与N型欧姆接触区124为N型离子重掺杂。因而,N型源区114与N型欧姆接触区124可以在同一工序中形成。
接着,参照图4的步骤S4与图8所示,在第一N型基区110下方依次形成第一N型缓冲层115与第一P型集电区116;在第二N型基区120下方依次形成第二N型缓冲层125与第二P型集电区126。
第一N型缓冲层115、第二N型缓冲层125、第一P型集电区116与第二P型集电区126都可以采用离子注入法形成。第一N型缓冲层115与第二N型缓冲层125为N型离子重掺杂。第一P型集电区116与第二P型集电区126为P型离子重掺杂。因而,第一N型缓冲层115与第二N型缓冲层125可以在同一工序中形成。第一P型集电区116与第二P型集电区126可以在同一工序中形成。
之后,参照图4的步骤S5与图1所示,在控制区112上形成控制电极;在P型欧姆接触区113、N型源区114、第一P型扩散区121以及第二P型扩散区122上形成发射极13;在N型欧姆接触区124上形成采样电极15;在第一P型集电区116与第二P型集电区126上形成集电极14。
图1所示截面上,显示了发射极13,控制电极可以设置在其它截面上。换言之,控制电极的设置位置可与发射极13的设置位置错开。
IGBT原胞11的控制区112、P型欧姆接触区113与N型源区114,以及采样原胞12的第一P型扩散区121与第二P型扩散区122,第一P型扩散区121、第二P型扩散区122与N型欧姆接触区124上可以设置层间绝缘层16。层间绝缘层16内具有若干暴露待电连接区域的开口。
控制电极、发射极13、集电极14以及采样电极15的材料可以为金属,例如铜或铝。控制电极、发射极13以及采样电极15制作在半导体衬底10的同一侧,因而可以在同一工序中形成。
发射极13、集电极14以及采样电极15设置在层间绝缘层16上
图9是本发明第二实施例的集成采样结构的IGBT的截面结构示意图。参照图9,该集成采样结构的IGBT2与图1中的集成采样结构的IGBT1大致相同,区别仅在于:第二N型基区120内具有第一扩散阻挡区127与第二扩散阻挡区128,第一扩散阻挡区127与第二扩散阻挡区128分别邻接电子通道123;第一P型扩散区121位于第一扩散阻挡区127远离电子通道123的一侧,第二P型扩散区122位于第二扩散阻挡区128远离电子通道123的一侧。
第一扩散阻挡区127与第二扩散阻挡区128可防止第一P型扩散区121与第二P型扩散区122闭合电子通道123。
本实施例中,第一扩散阻挡区127与第二扩散阻挡区128可以包括:导电材料区与位于导电材料区的侧壁的绝缘材料层。
对应地,集成采样结构的IGBT2的制作方法与图4中的集成采样结构的IGBT1的制作方法大致相同,区别仅在于:步骤S2,在第二N型基区120内形成第一P型扩散区121与第二P型扩散区122步骤前,在第二N型基区120内分别形成第一扩散阻挡区127与第二扩散阻挡区128,第一扩散阻挡区127与第二扩散阻挡区128分别邻接电子通道123。具体地,可以包括:在第二N型基区120形成第二沟槽与第三沟槽,在第二沟槽内形成第一扩散阻挡区127,在第三沟槽内形成第二扩散阻挡区128。
第二沟槽与第三沟槽可以与步骤S1中的第一沟槽在同一工序中开设。分别在第一沟槽、第二沟槽与第三沟槽内填充导电材料在同一工序中进行。
第一扩散阻挡区127与第二扩散阻挡区128可以接固定电位,上述固定电位不可过大,以防止击穿层间绝缘层16。例如,第一扩散阻挡区127与第二扩散阻挡区128都连接至发射极13。
其它实施例中,第一扩散阻挡区127与第二扩散阻挡区128也可以包括:绝缘材料区与位于绝缘材料区的侧壁的绝缘材料层。
图10是本发明第三实施例的集成采样结构的VDMOS的截面结构示意图。参照图10,该集成采样结构的VDMOS3与图1、图9中的集成采样结构的IGBT1、2大致相同,区别仅在于:省略第一P型集电区116与第二P型集电区126;发射极13替换为源极17,集电极14替换为漏极18,漏极18连接于第一N型缓冲层115与第二N型缓冲层125。此外,IGBT原胞11为VDMOS原胞19。
虽然本发明披露如上,但本发明并非限定于此。任何本领域技术人员,在不脱离本发明的精神和范围内,均可作各种更动与修改,因此本发明的保护范围应当以权利要求所限定的范围为准。
Claims (16)
1.一种集成采样结构的垂直型半导体结构,其特征在于,包括:
垂直型半导体结构原胞,包括:第一N型基区、伸入所述第一N型基区内的P型阱区、自所述P型阱区伸入所述第一N型基区的控制区、位于所述P型阱区上部的P型欧姆接触区与N型源区,所述N型源区位于所述P型欧姆接触区的两侧,以及位于所述第一N型基区下方的第一N型缓冲层;
采样原胞,包括:第二N型基区、伸入所述第二N型基区内的第一P型扩散区与第二P型扩散区,所述第一P型扩散区与所述第二P型扩散区之间形成电子通道、位于所述电子通道上部的N型欧姆接触区,以及位于第二N型基区下方的第二N型缓冲层;
控制电极,连接于所述垂直型半导体结构原胞的控制区;
第一电极,连接于所述垂直型半导体结构原胞的P型欧姆接触区与N型源区,以及所述采样原胞的第一P型扩散区与第二P型扩散区;
第二电极,连接于所述垂直型半导体结构原胞的第一N型缓冲层与所述采样原胞的第二N型缓冲层;
采样电极,连接于所述采样原胞的N型欧姆接触区。
2.根据权利要求1所述的集成采样结构的垂直型半导体结构,其特征在于,所述垂直型半导体结构为IGBT,所述第一电极为发射极;所述IGBT原胞还包括:位于所述第一N型缓冲层下方的第一P型集电区,所述采样原胞还包括:位于所述第二N型缓冲层下方的第二P型集电区;所述第二电极为集电极,连接于所述IGBT半导体结构原胞的第一P型集电区与所述采样原胞的第二P型集电区。
3.根据权利要求1所述的集成采样结构的垂直型半导体结构,其特征在于,所述垂直型半导体结构为VDMOS,所述第一电极为源极,所述第二电极为漏极。
4.根据权利要求1所述的集成采样结构的垂直型半导体结构,其特征在于,还包括:采样电阻,连接于所述采样电极与所述第一电极之间。
5.根据权利要求1所述的集成采样结构的垂直型半导体结构,其特征在于,所述垂直型半导体结构原胞具有并联的多个,所述采样原胞具有并联的多个。
6.根据权利要求1至5任一项所述的集成采样结构的垂直型半导体结构,其特征在于,所述第二N型基区内具有第一扩散阻挡区与第二扩散阻挡区,所述第一扩散阻挡区与所述第二扩散阻挡区分别邻接所述电子通道;所述第一P型扩散区位于所述第一扩散阻挡区远离所述电子通道的一侧,所述第二P型扩散区位于所述第二扩散阻挡区远离所述电子通道的一侧。
7.根据权利要求6所述的集成采样结构的垂直型半导体结构,其特征在于,所述第一扩散阻挡区与所述第二扩散阻挡区包括:导电材料区与位于所述导电材料区的侧壁的绝缘材料层。
8.根据权利要求7所述的集成采样结构的垂直型半导体结构,其特征在于,所述导电材料区与所述第一电极电连接。
9.根据权利要求6所述的集成采样结构的垂直型半导体结构,其特征在于,所述第一扩散阻挡区与所述第二扩散阻挡区包括:绝缘材料区与位于所述绝缘材料区的侧壁的绝缘材料层。
10.一种集成采样结构的垂直型半导体结构的制作方法,其特征在于,包括:
提供半导体衬底,所述半导体衬底包括N型基区,所述N型基区包括第一N型基区与第二N型基区,所述第一N型基区用于形成垂直型半导体结构原胞,所述第二N型基区用于形成采样原胞;在所述第一N型基区形成第一沟槽,在所述第一沟槽内形成控制区;
在所述第一N型基区内形成P型阱区,所述P型阱区伸入所述第一N型基区的深度小于所述第一沟槽的深度;在所述第二N型基区内形成第一P型扩散区与第二P型扩散区,所述第一P型扩散区与所述第二P型扩散区之间形成电子通道;
在所述P型阱区的上部形成P型欧姆接触区与N型源区,所述N型源区位于所述P型欧姆接触区的两侧;在所述电子通道的上部形成N型欧姆接触区;
在所述第一N型基区下方形成第一N型缓冲层;在所述第二N型基区下方形成第二N型缓冲层;
在所述控制区上形成控制电极;在所述P型欧姆接触区、所述N型源区、所述第一P型扩散区以及所述第二P型扩散区上形成第一电极;在所述N型欧姆接触区上形成采样电极;在所述第一N型缓冲层与所述第二N型缓冲层上形成第二电极。
11.根据权利要求10所述的集成采样结构的垂直型半导体结构的制作方法,其特征在于,在所述P型阱区的上部形成N型源区与在所述电子通道的上部形成N型欧姆接触区在同一工序中进行;和/或
在所述第一N型基区下方形成第一N型缓冲层与在所述第二N型基区下方形成第二N型缓冲层在同一工序中进行;和/或
在所述控制区上形成控制电极,在所述P型欧姆接触区、所述N型源区、所述第一P型扩散区以及所述第二P型扩散区上形成第一电极,在所述N型欧姆接触区上形成采样电极在同一工序中进行。
12.根据权利要求10所述的集成采样结构的垂直型半导体结构的制作方法,其特征在于,所述垂直型半导体结构为IGBT,所述第一电极为发射极;
所述制作方法还包括:在所述第一N型缓冲层下方形成第一P型集电区,同时在所述第二N型缓冲层下方形成第二P型集电区;
所述第二电极为集电极,连接于所述IGBT半导体结构原胞的第一P型集电区与所述采样原胞的第二P型集电区。
13.根据权利要求10所述的集成采样结构的垂直型半导体结构的制作方法,其特征在于,所述垂直型半导体结构为VDMOS,所述第一电极为源极,所述第二电极为漏极。
14.根据权利要求10所述的集成采样结构的垂直型半导体结构的制作方法,其特征在于,在所述第二N型基区内形成第一P型扩散区与第二P型扩散区步骤前,在所述第二N型基区内分别形成第一扩散阻挡区与第二扩散阻挡区,所述第一扩散阻挡区与所述第二扩散阻挡区分别邻接所述电子通道。
15.根据权利要求14所述的集成采样结构的垂直型半导体结构的制作方法,其特征在于,在所述第二N型基区内分别形成第一扩散阻挡区与第二扩散阻挡区包括:在所述第二N型基区形成第二沟槽与第三沟槽,在所述第二沟槽内形成第一扩散阻挡区,在所述第三沟槽内形成第二扩散阻挡区。
16.根据权利要求15所述的集成采样结构的垂直型半导体结构的制作方法,其特征在于,在所述第一N型基区形成第一沟槽与在所述第二N型基区形成第二沟槽与第三沟槽在同一工序中进行;在所述第一沟槽内形成控制区、在所述第二沟槽内形成第一扩散阻挡区,以及在所述第三沟槽内形成第二扩散阻挡区在同一工序中进行。
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