CN115410928A - 正装mos芯片及隔离耐压球焊芯片堆叠结构的制备方法 - Google Patents

正装mos芯片及隔离耐压球焊芯片堆叠结构的制备方法 Download PDF

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CN115410928A
CN115410928A CN202211225712.4A CN202211225712A CN115410928A CN 115410928 A CN115410928 A CN 115410928A CN 202211225712 A CN202211225712 A CN 202211225712A CN 115410928 A CN115410928 A CN 115410928A
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resistant ball
ball bonding
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殷炯
田立方
李世平
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Jiangsu Huachuang Micro System Co ltd
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Abstract

本发明公开了一种正装MOS芯片及隔离耐压球焊芯片堆叠结构的制备方法，包括以下步骤：S1、采用框架材料制备基板层；S2、在基板层的基岛的正面基岛上正装MOS功率芯片；S3、安装金属片；S4、对安装隔离耐压球焊芯片的位置处进行点底填胶；S5、安装隔离耐压球焊芯片；S6、隔离耐压球焊芯片与金属片之间焊线进行电气连接；S7、塑封料包覆正装MOS芯片及隔离耐压球焊芯片堆叠结构。优点，本发明方法，可以有效的减小封装尺寸，提升MOS功率芯片大电性能及散热性能；本发明方法中，用底填胶将金属片和隔离耐压球焊芯片隔离开，再用塑封料进行保护结构，防止隔离耐压球焊芯片侧边和金属片有漏电。

Description

正装MOS芯片及隔离耐压球焊芯片堆叠结构的制备方法
技术领域
本发明涉及正装MOS芯片及隔离耐压球焊芯片堆叠结构的制备方法。
背景技术
目前MOS功率芯片与多颗隔离耐压芯片为平铺结构，这就导致整体封装尺寸非常大；另其中MOS芯片一般为正装球焊，电性能不佳。
MOS功率芯片3与隔离耐压芯片5，目前已有的封装技术为Side by Side平铺结构，主要用树脂或灌封胶进行隔离（树脂或灌封胶的耐压值很高，可以抗高电压击穿导致漏电）；封装示意图如图1所示。
如图1所示，目前已有的技术为隔离耐压芯片MOS芯片保持安全距离分开，导致封装尺寸特别大。为了减小封装尺寸，通过本专利可以有效的减小封装尺寸降低封装成本及提高PCB板的利用率，且可以让MOS芯片有更优的电性能。
发明内容
本发明提出一种正装MOS芯片及隔离耐压球焊芯片堆叠结构的制备方法，该方法中的正装MOS芯片及隔离耐压球焊芯片堆叠结构，适用于一种特殊结构，底下是MOS功率芯片，MOS功率芯片背面接铜面进行散热。
采取的技术方案如下：一种正装MOS芯片及隔离耐压球焊芯片堆叠结构的制备方法，包括如下步骤：
S1、采用框架材料制备基板层；
S2、在基板层的基岛的正面基岛上正装MOS功率芯片；
S3、安装金属片，对芯片功能进行输出；
S4、对安装隔离耐压球焊芯片的位置处进行点底填胶；
S5、隔离耐压球焊芯片安装在点底填胶的位置处，底填胶隔离开金属片与隔离耐压球焊芯片；
S6、隔离耐压球焊芯片与金属片之间焊线进行电气连接；
S7、塑封料包覆所述正装MOS芯片及隔离耐压球焊芯片堆叠结构。
对本发明技术方案的进一步优选，金属片的两端之间存在高度差，金属片的低端设置在基板层的功能管脚上，金属片的高端与MOS功率芯片的铜柱连接。
对本发明技术方案的进一步优选，S3中金属片用锡膏贴装在功能管脚和MOS功率芯片的铜柱上。
本发明与现有技术相比的有益效果是：
本发明方法中的正装MOS芯片及隔离耐压球焊芯片堆叠结构，可以有效的减小封装尺寸，提升MOS功率芯片大电性能及散热性能；本发明方法中，用底填胶将金属片和隔离耐压球焊芯片隔离开，再用塑封料进行保护结构，防止隔离耐压球焊芯片侧边和金属片有漏电。
附图说明
图1为现有技术中MOS功率芯片与隔离耐压芯片的平铺结构示意图。
图2为实施例1方法的步骤S1的基板层的示意图。
图3为实施例1方法的步骤S2的MOS功率芯片安装到基板层的示意图。
图4为实施例1方法的步骤S3的金属片安装的示意图。
图5为实施例1方法的步骤S4的对需要安装的隔离耐压球焊芯片的位置处进行点底填胶的示意图。
图6为实施例1方法的步骤5的安装的隔离耐压球焊芯片的示意图。
图7为实施例1方法的步骤6焊线进行电气连接的示意图。
图8为实施例1方法的步骤S7的塑封料封装后的示意图。
图9为金属片的俯视图。
具体实施方式
下面对本发明技术方案进行详细说明，但是本发明的保护范围不局限于所述实施例。
为使本发明的内容更加明显易懂，以下结合附图1-图9和具体实施方式做进一步的描述。
实施例1
如图6所示，本实施例一种正装MOS芯片及隔离耐压球焊芯片堆叠结构的制备方法，包括以下步骤：
S1、采用框架材料制备基板层；
S2、在基板层的基岛1的正面基岛上正装MOS功率芯片3；
S3、安装金属片4，对芯片功能进行输出；
S4、对安装隔离耐压球焊芯片5的位置处进行点底填胶6；
S5、隔离耐压球焊芯片5安装在点底填胶6的位置处，底填胶6隔离开金属片4与隔离耐压球焊芯片5；
S6、隔离耐压球焊芯片5与金属片4之间焊线进行电气连接；
S7、塑封料7包覆正装MOS芯片及隔离耐压球焊芯片堆叠结构。
本发明方法中的正装MOS芯片及隔离耐压球焊芯片堆叠结构，适用于一种特殊结构，底下是MOS功率芯片，MOS功率芯片背面接铜面进行散热。
本实施例的方法中形成的正装MOS芯片及隔离耐压球焊芯片堆叠结构，包括基板层、MOS功率芯片3、金属片4、隔离耐压球焊芯片5、底填胶6和塑封料7。MOS功率芯片3装在基岛1的正面基岛上；金属片4两端之间存在高度差，金属片4的低端设置在功能管脚2上，金属片4的高端与MOS功率芯片3的铜柱连接；隔离耐压球焊芯片5通过底填胶6设置在基板层上，隔离耐压球焊芯片5与金属片4之间焊线进行电气连接；塑封料7包覆MOS功率芯片及多颗隔离耐压球焊芯片堆叠结构。
如图3所示，本实施例中提及的MOS功率芯片3为已知芯片，MOS功率芯片3为带Bumping的MOS功率芯片，正装在基岛1的正面基岛上，MOS功率芯片3背面接铜面进行散热。带Bumping的MOS功率芯片用装片胶安装在基岛1的正面基岛上。
如图4所示，本实施例的方法中，金属片4两端之间存在高度差，金属片4的低端设置在功能管脚2上，金属片4的高端与MOS功率芯片3的铜柱31连接；安装金属片4，对芯片功能进行输出。金属片4用锡膏贴连接功能管脚2和MOS功率芯片3的铜柱31，实现电气连接。
本实施例的金属片4，可根据底层带铜柱(Bumping)的MOS功率芯片进行定制化设计，用金属片4连接铜柱和功能脚位进行芯片功能输出。
本实施例中的金属片4为定制加工的金属片，此金属片具备如下优点：
1.定制化批量加工，表面可以进行电镀及粗化（粗化可以改善后期与塑封料的结合）处理，对于球焊芯片可以进行打线。
2.定制金属片可以按MOS功率芯片尺寸进行定制化作“通孔”设计，利于塑封时塑封料填充整个结构。
如图4所示，本实施例的金属片4，整体呈Z字形，金属片4的高端和低端均设有水平面，Z字形的金属片4能有效地避让焊线，方便安装，同时可以和MOS功率芯片的Bumping进行连接导通。金属片4的高端和低端的水平面设置，能有效地进行芯片的连接。
如图9所示，本实施例的金属片4的板面上竖直开设多个通孔，通孔的设置，利于塑封时塑封料填充整个结构。
如图4和9所示，本实施例的金属片4可以在特定区域进行电镀，本实施例中，金属片4上与MOS功率芯片的铜柱连接处进行表面电镀处理，对于球焊芯片可以进行打线。金属片4表面粗化处理，粗化可以改善后期与塑封料的结合。
如图5和6所示，金属片4安装完成后，对需要安装的隔离耐压球焊芯片5的位置处进行点底填胶6，用底填胶6将金属片4和隔离耐压球焊芯片5隔离开，最后再用塑封料7进行保护结构，且防止隔离耐压球焊芯片5侧边和金属片有漏电。隔离耐压球焊芯片5设置在底填胶6上，通过底填胶6设置在基板层上，隔离耐压球焊芯片5与金属片4之间焊线8进行电气连接；最后塑封料7包覆MOS功率芯片及多颗隔离耐压球焊芯片堆叠结构。
本实施例中，对需要安装的隔离耐压球焊芯片5的位置处进行点底填胶6，是用Underfill技术进行底填胶填充，并固化底填胶。用Underfill技术进行底填胶填充为本技术领域内的已知技术，本领域技术人员已知。
如图7所示，S6中隔离耐压球焊芯片5与金属片4之间焊线8进行电气连接；本实施例的金属片4设计成Z字形，可以避让焊线，同时可以和MOS功率芯片的Bumping进行连接导通。
如图8所示，塑封料8包覆正装MOS芯片及隔离耐压球焊芯片堆叠结构进行保护结构，且防止隔离耐压球焊芯片5侧边和金属片有漏电。
本实施例提出的MOS功率芯片及多颗隔离耐压球焊芯片堆叠结构，可以有效的减小封装尺寸，提升MOS功率芯片大电性能及散热性能，属于半导体封装技术领域。
以上实施例仅为说明本发明的技术思想，不能以此限定本发明的保护范围，凡是按照本发明提出的技术思想，在技术方案基础上所做的任何改动，均落入本发明保护范围之内。

Claims (3)

1.一种正装MOS芯片及隔离耐压球焊芯片堆叠结构的制备方法，其特征在于：包括以下步骤：
S1、采用框架材料制备基板层；
S2、在基板层的基岛（1）的正面基岛上正装MOS功率芯片（3）；
S3、安装金属片（4），对芯片功能进行输出；
S4、对安装隔离耐压球焊芯片（5）的位置处进行点底填胶（6）；
S5、隔离耐压球焊芯片（5）安装在点底填胶（6）的位置处，底填胶（6）隔离开金属片（4）与隔离耐压球焊芯片（5）；
S6、隔离耐压球焊芯片（5）与金属片（4）之间焊线进行电气连接；
S7、塑封料（7）包覆所述正装MOS芯片及隔离耐压球焊芯片堆叠结构。
2.根据权利要求1所述的一种倒装芯片与底层芯片的堆叠结构，其特征在于：金属片（4）的两端之间存在高度差，金属片（4）的低端设置在基板层的功能管脚（2）上，金属片（4）的高端与MOS功率芯片（3）的铜柱（31）连接。
3.根据权利要求2所述的一种倒装芯片与底层芯片的堆叠结构，其特征在于：S3中金属片（4）用锡膏贴装在功能管脚（2）和MOS功率芯片（3）的铜柱（31）上。
CN202211225712.4A 2022-10-09 2022-10-09 正装mos芯片及隔离耐压球焊芯片堆叠结构的制备方法 Pending CN115410928A (zh)

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