CN115332262A - Method for increasing floating gate thickness of stacked capacitor region - Google Patents
Method for increasing floating gate thickness of stacked capacitor region Download PDFInfo
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- CN115332262A CN115332262A CN202211044941.6A CN202211044941A CN115332262A CN 115332262 A CN115332262 A CN 115332262A CN 202211044941 A CN202211044941 A CN 202211044941A CN 115332262 A CN115332262 A CN 115332262A
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- oxide film
- silicon oxide
- floating gate
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- 238000000034 method Methods 0.000 title claims abstract description 53
- 239000003990 capacitor Substances 0.000 title claims abstract description 23
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 42
- 230000002093 peripheral effect Effects 0.000 claims abstract description 34
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 34
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 27
- 239000004065 semiconductor Substances 0.000 claims abstract description 25
- 229920005591 polysilicon Polymers 0.000 claims abstract description 20
- 238000002955 isolation Methods 0.000 claims abstract description 19
- 238000005498 polishing Methods 0.000 claims abstract description 14
- 239000000126 substance Substances 0.000 claims abstract description 13
- 230000001413 cellular effect Effects 0.000 claims abstract description 9
- 238000007517 polishing process Methods 0.000 claims abstract description 5
- 230000008569 process Effects 0.000 claims description 22
- 229920002120 photoresistant polymer Polymers 0.000 claims description 17
- 239000000758 substrate Substances 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 6
- 238000001312 dry etching Methods 0.000 claims description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 3
- 230000007547 defect Effects 0.000 abstract description 4
- 239000010408 film Substances 0.000 description 22
- 235000012239 silicon dioxide Nutrition 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 239000002784 hot electron Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical group [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
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- Semiconductor Integrated Circuits (AREA)
Abstract
The invention provides a method for increasing the thickness of a floating gate in a laminated capacitance area, which comprises the following steps: providing a semiconductor structure, wherein the semiconductor structure comprises a cell area and a peripheral area, the cell area and the peripheral area are both provided with shallow trench isolation structures, and the area between adjacent shallow trench isolation structures in the peripheral area is a laminated capacitor area; forming a polycrystalline silicon layer on the surface of the semiconductor structure; forming a silicon oxide film on the surface of the polycrystalline silicon layer; removing the silicon oxide film formed in the cellular region; and polishing through a chemical mechanical polishing process to planarize the polysilicon layer of the cell region and the peripheral region. The invention solves the problem that the prior chemical mechanical polishing method causes defects in a cellular region and a peripheral region.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a method for improving the thickness of a floating gate in a laminated capacitor area.
Background
The floating gate is a feature of flash memory (flash) and is not connected to any part within the silicon dioxide enclosure. Under normal conditions, the floating gate is not charged, and the flash memory is in a non-conducting state; when an external power supply is changed, a large number of electrons flow from a source electrode to a drain electrode to form large current, a large number of hot electrons are generated, and partial hot electrons can reach a silicon dioxide layer between a substrate and a floating gate.
In Nor flash, the polysilicon layer used to form the floating gate needs to be planarized by Chemical Mechanical Polishing (CMP) after deposition. The pattern dependence of the CMP process itself (different CMP rates for areas with different pattern sizes) is an important factor in the process non-uniformity and smaller process window. The insufficient operation of the chemical mechanical polishing process may cause polysilicon residue on the shallow trench isolation structure of the cell region (cell region) (as shown in fig. 1); excessive operation of the cmp process may cause dishing of the stacked capacitor region (the region between adjacent sti structures) in the peripheral region (Peri region) (as shown in fig. 1), thereby resulting in a low floating gate thickness of the stacked capacitor region and risk of silicide bridging with the active region.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, the present invention provides a method for increasing the thickness of the floating gate in the stacked capacitor region, which is used to solve the problem of the defects in the cell region and the peripheral region caused by the conventional chemical mechanical polishing method.
To achieve the above and other related objects, the present invention provides a method for increasing the thickness of a floating gate in a stacked capacitor region, the method comprising:
providing a semiconductor structure, wherein the semiconductor structure comprises a cell area and a peripheral area, the cell area and the peripheral area are both provided with shallow trench isolation structures, and the area between adjacent shallow trench isolation structures in the peripheral area is a laminated capacitor area;
forming a polycrystalline silicon layer on the surface of the semiconductor structure;
forming a silicon oxide film on the surface of the polycrystalline silicon layer;
removing the silicon oxide film formed in the cellular region;
and polishing through a chemical mechanical polishing process to planarize the polysilicon layer of the cell region and the peripheral region.
Optionally, the thickness of the silicon oxide film is larger than
Optionally, the semiconductor structure includes a semiconductor substrate and an oxide layer formed on a surface of the semiconductor substrate.
Optionally, the polysilicon layer is formed by a furnace process.
Alternatively, the silicon oxide film is formed by an LPCVD process.
Optionally, the method of removing the silicon oxide film formed on the cell region includes:
forming photoresist on the surface of the silicon oxide film, and defining the cell area and the peripheral area by the photoresist;
removing the photoresist on the surface of the silicon oxide film in the cellular area;
and removing the silicon oxide film in the cellular area by using an etching process.
Optionally, the etching process includes dry etching or wet etching.
Optionally, the photoresist is a negative photoresist.
Optionally, the density of the shallow trench isolation structures of the cell region is greater than the density of the shallow trench isolation structures of the peripheral region.
As described above, in the method for increasing the floating gate thickness of the stacked capacitor area of the present invention, silicon oxide is formed on the surface of the polysilicon layer in the peripheral area, so as to reduce the difference in the polishing rate between the peripheral area and the cell area during the chemical mechanical polishing, increase the process window, remove the polysilicon residue on the shallow trench isolation structure in the cell area, and increase the floating gate thickness of the stacked capacitor area.
Drawings
Fig. 1 is a schematic view showing defects caused by a conventional chemical mechanical polishing method.
FIG. 2 is a flow chart of a method for increasing the floating gate thickness of the stacked capacitor region according to the present invention.
FIGS. 3-7 are schematic cross-sectional views illustrating the process of retaining the silicon oxide film formed in the peripheral region according to the present invention.
FIG. 8 is a schematic diagram of a device structure after chemical mechanical polishing according to the present invention.
Description of the reference numerals
10. Semiconductor structure
11. Semiconductor substrate
12. Oxide layer
20. Shallow trench isolation structure
30. Polycrystalline silicon layer
40. Silicon oxide film
50. Photoresist
Detailed Description
The following embodiments of the present invention are provided by way of specific examples, and other advantages and effects of the present invention will be readily apparent to those skilled in the art from the disclosure herein. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1 to 8. It should be noted that the drawings provided in the present embodiment are only for schematically illustrating the basic idea of the present invention, and although the drawings only show the components related to the present invention and are not drawn according to the number, shape and size of the components in actual implementation, the form, quantity and proportion of each component in actual implementation may be arbitrarily changed, and the layout of the components may be more complicated.
As shown in fig. 2, the present embodiment provides a method for increasing the thickness of a floating gate in a stacked capacitor region, the method comprising:
providing a semiconductor structure 10, wherein the semiconductor structure comprises a cell area A (cell area) and a peripheral area B (Peri area), the cell area A and the peripheral area B are both provided with shallow trench isolation structures 20, and the area between adjacent shallow trench isolation structures 20 of the peripheral area B is a stacked capacitor area C;
forming a polysilicon layer 30 on the surface of the semiconductor structure 10;
forming a silicon oxide film 40 on the surface of the polysilicon layer 30;
removing the silicon oxide film 40 formed in the cell region a;
the polysilicon layer 30 of the cell region a and the peripheral region B is polished by a chemical mechanical polishing process to be planarized.
In this embodiment, when performing Chemical Mechanical Polishing (CMP), the high selection ratio of the polysilicon layer 30 and the silicon oxide film 40 reduces the difference between the polishing rates of the cell region a with the polysilicon layer 30 and the peripheral region B with the polysilicon layer 30 and the silicon oxide film 40 during CMP, thereby increasing the process window, removing the polysilicon residue on the shallow trench isolation structure 20 of the cell region a, and increasing the thickness of the floating gate of the stacked capacitor region C of the peripheral region B.
Specifically, the thickness of the silicon oxide film 40 is larger than
Optionally, in this embodiment, the silicon oxide film 40 is a silicon dioxide film.
Specifically, the silicon oxide film 40 is obtained by an LPCVD process. The silicon dioxide thin film is obtained by preparation using a TEOS (tetraethyl orthosilicate) process or an HTO (high temperature oxidation) process in this example.
Specifically, the semiconductor structure 10 includes a semiconductor substrate 11 and an oxide layer 12 formed on a surface of the semiconductor substrate 11. In this embodiment, the semiconductor substrate 11 is a silicon substrate, and the material of the oxide layer 12 includes, but is not limited to, silicon oxide.
Specifically, the polysilicon layer 30 is formed by a furnace process.
Specifically, the method for removing the silicon oxide film 40 formed in the cell region a includes: forming a photoresist 50 on the surface of the silicon oxide film 40, and defining the cell region a and the peripheral region B by the photoresist; removing the photoresist 50 on the surface of the silicon oxide film 40 in the cell area a; and removing the silicon oxide film 40 in the cellular area A by using an etching process.
As an example, the photoresist is a negative photoresist. In this embodiment, the cell region a and the peripheral region B are defined by combining the CRS reticle and the negative photoresist, so that a new mask is not added, thereby saving the cost.
By way of example, the etching process includes dry etching or wet etching.
Specifically, the density of the shallow trench isolation structures 20 in the cell region a is greater than the density of the shallow trench isolation structures 20 in the peripheral region B.
The following table shows experimental data obtained by the method provided in this embodiment and experimental data obtained by the conventional method, and it can be seen from the table that the floating gate formed in the cell region has the same thickness (both are
) The floating gate formed in the peripheral region according to the method provided by the present embodiment has an increased thickness
On the other hand, BSL in the table indicates the conventional method (control group), and the method provided in the present example (experimental group) is shown after improvement. Therefore, the method provided by the embodiment can effectively improve the floating gate thickness (namely the polysilicon layer thickness) of the laminated capacitor region.
TABLE 1
In summary, in the method for increasing the floating gate thickness of the stacked capacitor region of the present invention, silicon oxide is formed on the surface of the polysilicon layer in the peripheral region to reduce the difference in the polishing rate between the peripheral region and the cell region during the chemical mechanical polishing, increase the process window, remove the polysilicon residue on the shallow trench isolation structure in the cell region, and increase the floating gate thickness of the stacked capacitor region. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (9)
1. A method for increasing the thickness of a floating gate in a stacked capacitor region, the method comprising:
providing a semiconductor structure, wherein the semiconductor structure comprises a cell area and a peripheral area, the cell area and the peripheral area are both provided with shallow trench isolation structures, and the area between adjacent shallow trench isolation structures in the peripheral area is a laminated capacitor area;
forming a polycrystalline silicon layer on the surface of the semiconductor structure;
forming a silicon oxide film on the surface of the polycrystalline silicon layer;
removing the silicon oxide film formed in the cellular region;
and polishing through a chemical mechanical polishing process to planarize the polysilicon layer of the cell region and the peripheral region.
2. According to the claimsThe method for increasing the thickness of the floating gate in the stacked capacitor area of claim 1, wherein the thickness of the silicon oxide film is greater than that of the floating gate in the stacked capacitor area
3. The method as claimed in claim 1, wherein the semiconductor structure comprises a semiconductor substrate and an oxide layer formed on a surface of the semiconductor substrate.
4. The method of claim 1, wherein the polysilicon layer is formed by a furnace process.
5. The method of claim 1, wherein the silicon oxide film is formed by an LPCVD process.
6. The method of claim 1, wherein the removing the silicon oxide film formed on the cell region comprises:
forming photoresist on the surface of the silicon oxide film, and defining the cell area and the peripheral area by the photoresist;
removing the photoresist on the surface of the silicon oxide film in the cellular area;
and removing the silicon oxide film in the cellular area by using an etching process.
7. The method for increasing the thickness of the floating gate in the stacked capacitor region as claimed in claim 6, wherein the etching process comprises dry etching or wet etching.
8. The method of claim 6, wherein the photoresist is a negative photoresist.
9. The method as claimed in claim 1, wherein the density of the shallow trench isolation structures in the cell region is greater than the density of the shallow trench isolation structures in the peripheral region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211044941.6A CN115332262A (en) | 2022-08-29 | 2022-08-29 | Method for increasing floating gate thickness of stacked capacitor region |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211044941.6A CN115332262A (en) | 2022-08-29 | 2022-08-29 | Method for increasing floating gate thickness of stacked capacitor region |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN115332262A true CN115332262A (en) | 2022-11-11 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211044941.6A Pending CN115332262A (en) | 2022-08-29 | 2022-08-29 | Method for increasing floating gate thickness of stacked capacitor region |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115332262A (en) |
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2022
- 2022-08-29 CN CN202211044941.6A patent/CN115332262A/en active Pending
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