CN113206094B

CN113206094B - Method for manufacturing semiconductor element

Info

Publication number: CN113206094B
Application number: CN202010078697.XA
Authority: CN
Inventors: 邱云松; 邵红旭; 孔德锦; 欧阳锦坚; 谈文毅
Original assignee: United Semi Integrated Circuit Manufacture Xiamen Co ltd
Current assignee: United Semi Integrated Circuit Manufacture Xiamen Co ltd
Priority date: 2020-02-03
Filing date: 2020-02-03
Publication date: 2022-07-29
Anticipated expiration: 2040-02-03
Also published as: CN113206094A

Abstract

The invention discloses a method for manufacturing a semiconductor element, which comprises the following steps: providing a substrate, forming a floating gate material layer on the substrate, performing a planarization step to reduce a thickness of the floating gate material layer, performing an ion doping step on the floating gate material layer after the planarization step, and performing an etching step to remove a portion of the floating gate material layer and form a floating gate (floating gate), wherein no annealing (annealing) step is performed on the floating gate material layer after the floating gate material layer is formed and before the floating gate is formed.

Description

Method for manufacturing semiconductor element

Technical Field

The present invention relates to a method of manufacturing a semiconductor element, and more particularly, to a method of manufacturing a flash memory.

Background

A flash memory (flash memory) is a non-volatile memory that can store data in the memory even if an external power source is turned off. Recently, since flash memories are rewritable and erasable, they have been widely used in the manufacture of electronic products, such as mobile phones, digital cameras, video players, Personal Digital Assistants (PDAs), or systems on a chip (SOCs).

In order to meet the requirements of low power consumption, fast response, low cost, and high integration of electronic products, a process of integrating different semiconductor elements having various electrical properties and functions is a trend of the current semiconductor process. For example, flash memory cells in the flash memory array region and metal oxide semiconductor transistors in the logic circuit region may be fabricated in the same chip.

However, in fabricating a floating gate in a flash memory device, the steps include, in order, depositing a material layer (e.g., polysilicon), ion doping the material layer, annealing the material layer to diffuse the doped ions into the bulk material layer, and then planarizing the material layer (e.g., chemical mechanical polishing, CMP) to reduce the thickness of the material layer to a desired thickness. The above-mentioned fabrication process is a commonly used step in fabricating floating gates at present. However, there is still room for adjustment and improvement in the above steps in order to reduce the manufacturing cost.

Disclosure of Invention

The invention provides a method for manufacturing a semiconductor element, which comprises the following steps: providing a substrate, forming a floating gate material layer on the substrate, performing a planarization step to reduce a thickness of the floating gate material layer, performing an ion doping step on the floating gate material layer after the planarization step, and performing an etching step to remove a portion of the floating gate material layer and form a floating gate (floating gate), wherein no annealing (annealing) step is performed on the floating gate material layer after the floating gate material layer is formed and before the floating gate is formed.

According to the manufacturing method of the semiconductor element provided by the invention, the partial manufacturing process sequence before the floating grid is manufactured is adjusted. Specifically, the floating gate material layer is first planarized to reduce its thickness and then ion-doped, so that the doped ions can be directly distributed in the floating gate material layer due to the reduced thickness of the floating gate material layer, and the annealing step of the existing step to make the ions generate diffusion and uniform distribution effects can be omitted. Therefore, the invention achieves the effect of simplifying the manufacturing process.

Drawings

Fig. 1 to 4 are schematic views of a method for manufacturing a semiconductor device according to a preferred embodiment of the present invention.

Description of the main elements

12 base

14 element region

16 logical area

18 gate oxide layer

34 shallow trench isolation

36 doped region

38 layer of floating gate material

38' floating gate

40: gate structure

P1 planarization step

P2 ion doping step

P3 etching step

T1 thickness

T2 thickness

Detailed Description

In order to make the present invention more comprehensible to those skilled in the art, preferred embodiments of the present invention are described in detail below with reference to the accompanying drawings.

For convenience of explanation, the drawings are only schematic to facilitate understanding of the present invention, and the detailed proportions thereof may be adjusted according to design requirements. The relative positions of elements in the figures described herein are understood by those skilled in the art to refer to relative positions of objects and thus all parts may be turned over to present the same elements, all falling within the scope of the present disclosure and all described herein.

Referring to fig. 1 to 4, fig. 1 to 4 show a method of manufacturing a semiconductor device according to a preferred embodiment of the present invention. As shown in fig. 1, a substrate 12 is provided, wherein the substrate 12 includes an element region 14 and a logic region 16 defined thereon. In some embodiments, the device region 14 may also be referred to as a memory region, so that a flash memory (flash memory) is formed in the device region 14 in a subsequent step. The logic region 16 may include transistor structures in subsequent processes to control the flash memory. But the invention is not limited thereto.

Substrate 12 may be comprised of silicon, gallium arsenide, a silicon-on-insulator (SOI) layer, an epitaxial layer, a silicon germanium layer, or other semiconductor material, and a gate oxide layer 18 is formed over element region 14 and logic region 16 of substrate 12.

In addition, a plurality of Shallow Trench Isolations (STIs) 34 and doped regions 36 are formed in the logic region 16. In the present embodiment, the doped region 36 is located between two adjacent shallow trench isolations 34, and the top surface of each shallow trench isolation 34 is higher than the top surface of the substrate 12. The doped regions 36 include p-type and/or n-type wells for fabricating metal oxide semiconductor transistors and/or high voltage p-type and high voltage n-type wells for fabricating high voltage metal oxide semiconductor transistors. It should be noted, however, that the number and layout of the shallow trench isolations 34 and the doped regions 36 is not limited to that shown in fig. 1. It is also within the scope of the present invention that any doped region with corresponding shallow trench isolation may be formed in the substrate 12 of the logic region 16 depending on the design of the product.

Next, a layer of floating gate material 38 is deposited over the logic region 16 and the device region 14, wherein the layer of floating gate material 38 preferably covers all of the shallow trench isolation 34 and the doped region 36 in the logic region 16 and the device region 14. Preferably, in subsequent steps, the layer 38 of floating gate material is used to form the floating gates in the flash memory devices. For example, after ion doping, patterning, etc., a floating gate (not shown) is formed in the device region 14. A dielectric layer (e.g., an ONO dielectric layer) and a Control Gate (CG) are formed on the floating gate, which is not described herein since the structure of the flash memory is known in the art.

In the present embodiment, the floating gate material layer 38 is made of polysilicon, for example, and the thickness of the floating gate material layer 38 is preferably more than 4000 angstroms in order to stabilize and compact the structure. That is, the thickness T1 as shown in FIG. 1 is preferably greater than 4000 angstroms. According to some embodiments of the present invention, the floating gate material layer 38 may be formed by Chemical Vapor Deposition (CVD), Low Pressure Chemical Vapor Deposition (LPCVD), or Plasma Enhanced Chemical Vapor Deposition (PECVD), but the present invention is not limited thereto. A layer of floating gate material 38 is deposited overlying the logic region 16 and the device region 14, and overlying the top of the shallow trench isolation 34.

Next, as shown in fig. 2, a planarization step P1 is performed on the floating gate material layer 38 to reduce the thickness of the floating gate material layer 38. The planarization step P1 is, for example, but not limited to, Chemical Mechanical Polishing (CMP). After the planarization step P1 is completed, the thickness of the floating gate material layer 38 is reduced from T1 to T2, wherein the thickness T2 is preferably less than 740 angstroms in this embodiment, but the invention is not limited thereto, and the above parameters are only examples of the embodiment, and the actual parameters can be adjusted according to the manufacturing process requirements.

It should be noted that the slurry used in the cmp process includes chemical agents, such as ph buffers, oxidants, surfactants, etc., and abrasives, such as silica, alumina, zirconia, etc. According to a preferred embodiment of the present invention, the abrasive used in the chemical mechanical polishing process is greater than 13%, and the removal rate of the chemical mechanical polishing process is less than 30 a/s, but the present invention is not limited thereto.

Next, as shown in fig. 3, an ion doping step P2 is performed on the reduced thickness floating gate material layer 38, such as doping boron, phosphorus, arsenic, carbon, and hydrogen plasma, as required. After ion doping step P2 is completed, the doped ions should be uniformly distributed within floating gate material layer 38.

In a subsequent step, the floating gate material layer 38 is patterned, for example, as shown in fig. 4, an etching step P3 is performed to leave a portion of the floating gate material layer 38 only in the device region 14, while the remaining floating gate material layer 38 in the device region 14 is removed, and the remaining floating gate material layer 38 can be defined as a floating gate 38'. Then, material layers such as an ONO dielectric layer and a select gate are formed over the floating gate, and further description of the fabrication of these elements is omitted here for brevity. In addition, during the etching step P3, the floating gate material layer 38 may be etched in the logic region 16, and the floating gate material layer 38 remaining in the logic region 16 is defined as the gate structure 40. After the etching step P3, the height of the top surface of the shallow trench isolation 34 is higher than the top surface of the substrate 12.

It is noted that in the steps of the present invention, no anneal (anneal) step is required between the deposition of the layer of floating gate material 38 and the completion of the fabrication of the floating gate 38'. Since the thickness of the floating gate material layer 38 is reduced by the planarization step, the ions doped in the floating gate material layer 38 have less space for movement and are uniformly distributed.

In other embodiments of the present invention, the sequence of the etching step P3 shown in fig. 4 can be adjusted, for example, after the planarization step P1 (as shown in fig. 2), the etching step P3 is performed first, and then the ion doping step P2 is performed, which also falls within the scope of the present invention.

The conventional steps of fabricating the floating gate include sequentially depositing a material layer (e.g., polysilicon), doping ions into the material layer, annealing to uniformly diffuse the ions in the material layer, and then performing a planarization step to reduce the thickness of the material layer. Unlike the conventional floating gate fabrication process, the present invention adjusts the sequence of the fabrication process, and after the material layer (i.e., the floating gate material layer 38 shown in fig. 1) is deposited, a planarization step P1 is preferably performed to reduce the thickness of the floating gate material layer 38 (e.g., from 4000 angstroms to 740 angstroms), and then an ion doping step P2 is performed on the floating gate material layer 38, wherein the doped ions are uniformly distributed in the floating gate material layer 38 after the ion doping step P2. Therefore, the annealing step can be omitted, and the manufacturing process cost is further reduced.

In summary, according to the method for manufacturing a semiconductor device of the present invention, a part of the manufacturing process sequence before the floating gate is manufactured is adjusted. Specifically, the floating gate material layer is first planarized to reduce its thickness and then ion-doped, so that the doped ions can be directly distributed in the floating gate material layer due to the reduced thickness of the floating gate material layer, and the annealing step of the existing step to make the ions generate diffusion and uniform distribution effects can be omitted. Therefore, the invention achieves the effect of simplifying the manufacturing process.

The above description is only a preferred embodiment of the present invention, and all equivalent changes and modifications made by the claims of the present invention should be covered by the present invention.

Claims

1. A method for fabricating a semiconductor device includes:

providing a substrate;

forming a floating gate material layer on the substrate;

performing a planarization step to reduce the thickness of the floating gate material layer;

performing an ion doping step on the floating gate material layer after the planarization step; and

an etching step is performed to remove a portion of the floating gate material layer and form a floating gate, wherein no annealing step is performed on the floating gate material layer after the floating gate material layer is formed and before the floating gate is formed,

wherein a thickness of the layer of floating gate material is less than 740 angstroms after the planarizing step.

2. The method of claim 1, wherein a thickness of said layer of floating gate material is greater than 4000 angstroms prior to said planarizing step.

3. The method of claim 1, wherein the substrate comprises a logic region and a device region, and the floating gate is only located in the device region.

4. The method of claim 3 further comprising providing a plurality of shallow trench isolation structures in said substrate within said logic region.

5. The method of claim 4, further comprising at least one doped region in said substrate in said logic region and between two adjacent STI structures.

6. The method of claim 4, wherein the top surface of each shallow trench isolation structure is higher than a top surface of the substrate.

7. The method of claim 1, further comprising forming an oxide layer between the substrate and the floating gate material layer.