CN111180450A - Semiconductor device, manufacturing method thereof and electronic device - Google Patents
Semiconductor device, manufacturing method thereof and electronic device Download PDFInfo
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- CN111180450A CN111180450A CN201811340112.6A CN201811340112A CN111180450A CN 111180450 A CN111180450 A CN 111180450A CN 201811340112 A CN201811340112 A CN 201811340112A CN 111180450 A CN111180450 A CN 111180450A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 74
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 23
- 239000010410 layer Substances 0.000 claims abstract description 192
- 239000000463 material Substances 0.000 claims abstract description 93
- 238000007667 floating Methods 0.000 claims abstract description 66
- 238000000034 method Methods 0.000 claims abstract description 55
- 238000002955 isolation Methods 0.000 claims abstract description 41
- 239000011241 protective layer Substances 0.000 claims abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 29
- 238000005530 etching Methods 0.000 claims abstract description 19
- 238000000059 patterning Methods 0.000 claims abstract description 8
- 230000001590 oxidative effect Effects 0.000 claims abstract description 5
- 230000003647 oxidation Effects 0.000 claims description 15
- 238000007254 oxidation reaction Methods 0.000 claims description 15
- 230000015654 memory Effects 0.000 claims description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
- 229920005591 polysilicon Polymers 0.000 claims description 6
- 238000004151 rapid thermal annealing Methods 0.000 claims description 2
- 238000000151 deposition Methods 0.000 abstract description 4
- 238000002360 preparation method Methods 0.000 abstract description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 239000012212 insulator Substances 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 238000000407 epitaxy Methods 0.000 description 4
- 238000003860 storage Methods 0.000 description 4
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 3
- 229910052732 germanium Inorganic materials 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000011049 filling Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000002344 surface layer Substances 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- 229910003811 SiGeC Inorganic materials 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000001534 heteroepitaxy Methods 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 239000013067 intermediate product Substances 0.000 description 1
- 238000004943 liquid phase epitaxy Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910003465 moissanite Inorganic materials 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- 238000005389 semiconductor device fabrication Methods 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
Abstract
The invention provides a semiconductor device, a manufacturing method thereof and an electronic device. The method comprises the following steps: providing a semiconductor substrate, and forming a floating gate material layer, an isolation insulating layer, a control gate material layer and a mask layer on the semiconductor substrate; patterning the mask layer and the control gate material layer to form a plurality of control gates which are mutually spaced; oxidizing the side wall of the control gate to form a protective layer on the side wall of the control gate; and etching the isolation insulating layer and the floating gate material layer by taking the control gate as a mask to form a floating gate. According to the preparation method of the semiconductor device, after the control gate is formed and before the floating gate material layer is etched, the protection layer is not formed through a deposition method, but the exposed side wall of the control gate is oxidized to form the protection layer, so that the side wall of the control gate is protected from being damaged in the subsequent process of etching the floating gate material layer, and meanwhile, electric leakage between the control gates can be avoided.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor device, a manufacturing method thereof and an electronic device.
Background
With the development of semiconductor process technology, flash memories (flash memories) with faster access speed have been developed for memory devices. Flash memory has the characteristics of being capable of storing, reading and erasing information for many times, and the stored information does not disappear after power failure, so flash memory has become a nonvolatile memory widely used in personal computers and electronic devices. NAND flash memories are widely used in the field where read/write requirements are high due to their large storage capacity and relatively high performance. Recently, the capacity of NAND flash memory chips has reached 2GB, and the size has rapidly increased. Solid state disks based on NAND flash memory chips have been developed and used as storage devices in portable computers. Therefore, in recent years, NAND flash memories are widely used as storage devices in embedded systems, and also as storage devices in personal computer systems.
In the NAND preparation process, a stack of a floating gate material layer and a control gate material layer is formed firstly, and the floating gate material layer and the control gate material layer are patterned in sequence, after a control gate is formed on the patterned control gate material layer, the side wall of the control gate is damaged in the process of patterning the control gate material layer, and the performance and yield of a device are affected. In addition, how to avoid the leakage between the control gates also becomes a problem to be solved.
Therefore, it is necessary to provide a new manufacturing method to solve the above problems.
Disclosure of Invention
In this summary, concepts in a simplified form are introduced that are further described in the detailed description. This summary of the invention is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
In order to overcome the problems existing at present, the invention provides a manufacturing method of a semiconductor device, which comprises the following steps:
providing a semiconductor substrate, and forming a floating gate material layer, an isolation insulating layer, a control gate material layer and a mask layer on the semiconductor substrate;
patterning the mask layer and the control gate material layer to form a plurality of control gates which are mutually spaced;
oxidizing the side wall of the control gate to form a protective layer on the side wall of the control gate;
and etching the isolation insulating layer and the floating gate material layer by taking the control gate as a mask to form a floating gate.
Optionally, the protective layer is formed by a SPA oxidation process or a rapid thermal anneal oxidation process.
Optionally, the control gate material layer uses silicon or polysilicon.
Optionally, the protective layer is not formed on the isolation insulating layer.
Optionally, a strip-shaped floating gate material layer is formed on the semiconductor substrate, and the mask layer and the control gate material layer are patterned to form a plurality of control gates spaced from each other in an extending direction of the strip-shaped floating gate material layer.
Optionally, an isolation structure located between the floating gate material layers is further formed in the semiconductor substrate to isolate adjacent strip-shaped floating gate material layers.
Optionally, the protective layer is removed simultaneously with or after etching the isolation insulating layer and the floating gate material layer.
Optionally, the semiconductor device is a NAND memory cell.
The invention also provides a semiconductor device, which is prepared by the method.
The invention also provides an electronic device comprising the semiconductor device.
According to the preparation method of the semiconductor device, after the control gate is formed and before the floating gate material layer is etched, the protection layer is not formed through a deposition method, but the exposed side wall of the control gate is oxidized to form the protection layer, so that the side wall of the control gate is protected from being damaged in the subsequent process of etching the floating gate material layer, the obtained control gate has a good outline, meanwhile, the electric leakage between the control gates can be avoided, and the performance and the yield of the semiconductor device are further improved.
Still another aspect of the present invention provides a semiconductor device manufactured by the above method and an electronic apparatus including the above semiconductor device.
The semiconductor device and the electronic device provided by the invention have similar advantages due to the preparation by the method.
Drawings
The following drawings of the invention are included to provide a further understanding of the invention. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
In the drawings:
FIG. 1 shows a flow chart of steps of a method of fabricating a semiconductor device according to an embodiment of the invention;
FIGS. 2A-2C are schematic cross-sectional views of a semiconductor device obtained by a method of fabricating the device;
fig. 3 is a schematic diagram of an electronic device according to an embodiment of the invention.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.
It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity to indicate like elements throughout.
It will be understood that when an element or layer is referred to as being "on" …, "adjacent to …," "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on …," "directly adjacent to …," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatial relationship terms such as "under …", "under …", "below", "under …", "above …", "above", and the like, may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below …" and "below …" can encompass both an orientation of up and down. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
At present, in the NAND manufacturing process, a stack of a floating gate material layer and a control gate material layer is formed first, and patterning is performed on the floating gate material layer and the control gate material layer in sequence, after a control gate is formed on the patterned control gate material layer, the side wall of the control gate is damaged in the process of patterning the control gate material layer, and the performance and yield of a device are affected. In order to solve this problem, the applicant has tried to deposit a protective layer on the sidewalls of the exposed polysilicon, but as the device size is reduced, the spacing between the control gates becomes smaller, and there is another problem that leakage occurs between the control gates after the protective layer is deposited on the sidewalls of the control gates.
In order to solve the problems in the prior art, the invention provides a manufacturing method of a semiconductor device, which is used for manufacturing a NAND flash memory.
As shown in fig. 1, the method includes:
step S1: providing a semiconductor substrate, and forming a floating gate material layer, an isolation insulating layer, a control gate material layer and a mask layer on the semiconductor substrate;
step S2: patterning the mask layer and the control gate material layer to form a plurality of control gates which are mutually spaced;
step S3: oxidizing the side wall of the control gate to form a protective layer on the side wall of the control gate;
step S4: and etching the isolation insulating layer and the floating gate material layer by taking the control gate as a mask to form a floating gate.
After the control gate is formed and before the floating gate material layer is etched, a protective layer is not formed by a deposition method, but the exposed side wall of the control gate is oxidized to form the protective layer, so that the side wall of the control gate is protected from being damaged in the subsequent process of etching the floating gate material layer, the obtained control gate has a good profile, meanwhile, the electric leakage between the control gates can be avoided, and the performance and the yield of the semiconductor device are further improved.
In the following description, for purposes of explanation, specific details are set forth in order to provide a thorough understanding of the present invention. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.
A method for manufacturing a semiconductor device according to an embodiment of the present invention will be described in detail with reference to fig. 2A to 2C.
Firstly, as shown in fig. 2A, a semiconductor substrate 200 is provided, a plurality of floating gate material layers 201 are formed on the semiconductor substrate 200, and shallow trench isolation structures 202 extending downward into the semiconductor substrate 200 are formed between adjacent floating gate material layers 201, as shown in fig. 2A.
Wherein the semiconductor substrate 200 may be at least one of the following materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-silicon-germanium (S-SiGeOI), silicon-on-insulator-silicon-germanium (SiGeOI), and germanium-on-insulator (GeOI), among others.
In one example, the method of forming the floating gate material layer 201 and the shallow trench isolation structure 202 includes the following steps a1 to a 4:
and step A1 is carried out, and a floating gate material layer and a mask layer are formed on the semiconductor substrate.
Specifically, a floating gate material layer is formed on the semiconductor substrate, and the floating gate material layer may be a polysilicon layer to form a floating gate structure in a subsequent step.
The mask layer can be a hard mask layer, such as SiN, so that the floating gate material layer is protected from being damaged in the process of forming the shallow trench.
And step A2, patterning the mask layer, the floating gate material layer and the semiconductor substrate to form a plurality of strip-shaped floating gate material layers which are isolated from each other and shallow trenches positioned between the strip-shaped floating gates.
Specifically, a dry etching process is performed to sequentially etch the hard mask layer, the floating gate material layer, and the semiconductor substrate 200 to form shallow trenches. Specifically, a photoresist layer with a pattern may be formed on the hard mask layer, the hard mask layer is dry etched using the photoresist layer as a mask to transfer the pattern to the hard mask layer, the floating gate material layer and the semiconductor substrate 200 are etched using the photoresist layer and the hard mask layer as masks to form a trench, and strip-shaped floating gate material layers 201 separated from each other by a shallow trench are formed in the floating gate material layer.
The number of floating gate structures is not limited to a certain range of values.
Step a3 is performed to fill an isolation material in the trench to form a shallow trench isolation structure.
Specifically, an isolation material may be formed on the hard mask layer and in the trench, where the isolation material may be silicon oxide, silicon oxynitride, and/or other existing low-k materials; and performing a chemical mechanical polishing process and stopping on the hard mask layer to form the shallow trench isolation structure.
Finally, step a4 is performed to remove the hard mask layer. The method of removing the remaining hard mask layer may be a wet etching process, and since the etchant for removing the hard mask layer is well known in the art, it will not be described in detail.
Removing the oxide layer and the nitride layer results in a pattern with shallow trench isolation structures, optionally further comprising well and threshold voltage adjustments to the pattern.
In another embodiment of the present invention, a method for forming an STI (shallow trench isolation) illustratively includes the steps of: forming a pad oxide layer, illustratively a silicon dioxide layer, on the semiconductor substrate by thermal oxidation to a thickness of
As a stress buffer layer for a subsequent silicon nitride layer; since the semiconductor device fabrication method of the present embodiment is used to fabricate the peripheral region of the NAND device, a floating gate material layer is also formed over the pad oxide layer, which is formed by conventional CVD (chemical vapor deposition) to a thickness of
A hard mask layer is then formed on the floating gate material layer, an exemplary hard mask layer being a silicon nitride layer formed by a CVD process to a thickness of
Protecting the active region in the subsequent STI isolation material filling, and serving as a barrier layer of the subsequent CMP; etching the hard mask layer to form a pattern corresponding to the STI structure, and then etching the grid material layer, the pad oxide layer (pad oxide) and the semiconductor substrate by taking the hard mask layer as a mask to form a groove; forming a liner oxide layer on the side wall and the bottom of the trench, illustratively forming the liner oxide layer through a high-temperature oxide layer as a generation layer in subsequent isolation layer filling; the trench is filled with an isolation material, such as silicon oxide, and then planarization is performed to remove the portion of the isolation material above the hard mask layer to form a shallow trench isolation structure. And then, removing the hard mask layer. Illustratively, in this embodiment, the hard mask layer is removed by a wet etching process, such as by a solution of phosphoric acid of suitable concentrationAnd removing the hard mask layer by using the solution.
Next, as shown in fig. 2A and 2B, an isolation insulating layer 204, a control gate material layer 205, and a mask layer 206 are formed on the strip-shaped floating gate material layer;
the isolation insulating layer 204 may be a commonly used oxide or a stack of oxides, preferably ONO (oxide-nitride-oxide structure insulating gate dielectric).
The control gate material layer 205 may be a conventional semiconductor material layer, such as silicon or polysilicon, and is preferably polysilicon in one embodiment of the present invention.
The polycrystalline silicon can be selected from reduced pressure epitaxy, low temperature epitaxy, selective epitaxy, liquid phase epitaxy, heteroepitaxy and molecular beam epitaxy, and the selective epitaxy is preferred in the invention.
The mask layer is a hard mask layer (nitride hard mask layer), the hard mask layer can be one or more of oxide, nitride (SiN, BN and SiCN), in one embodiment of the invention, the hard mask layer is made of oxide and can be formed by a deposition method or an epitaxial method, preferably a Chemical Vapor Deposition (CVD) method or Selective Epitaxial Growth (SEG), and the thickness of the mask layer is 50-1000 angstroms.
Next, with continued reference to fig. 2A, the control gate material layer and the mask layer are patterned to form a plurality of control gates spaced apart from each other.
Specifically, the control gate material layer and the mask layer are patterned in this step, so as to form a plurality of control gates spaced from each other in the extending direction of the strip-shaped floating gate material layer.
As an alternative implementation, in another embodiment of the present invention, the control gate material layer and the mask layer are patterned to form a square control gate, and an array of control gates spaced from each other is formed in the extending direction of the strip-shaped floating gate material layer and in a direction perpendicular to the extending direction of the strip-shaped floating gate material layer.
Wherein, in this step, the control gate material layer and the mask layer may be etched using dry etching or wet etching, and the isolation insulating layer 204 is used as a stop layer. Alternatively, the control gate material layer and the mask layer may be etched by a method having a larger etching selectivity with respect to the isolation insulating layer 204.
Next, as shown in fig. 2B, the sidewalls of the control gate are oxidized to form a protection layer 207 on the sidewalls of the control gate to cover the sidewalls of the control gate.
Specifically, the protective layer is formed by an SPA (slot planenantenna) oxidation process or a thermal oxidation method.
For example, in the SPA process, an oxygen-containing plasma may be generated at a process temperature of 300 to 500 ℃ and a microwave power of 1000 to 4000W to treat the surface layer of the sidewalls of the control gate, so that the surface layer of the sidewalls of the control gate is converted into an oxide of silicon, such as silicon dioxide. The process time is determined according to the thickness of the oxide layer of silicon to be formed, and illustratively, in the present embodiment, H is used in a ratio of 1% to 50%2/O2Gas to generate the oxygen-containing plasma, the SPA oxidizing process time being between 10s and 300s, the formed oxide layer 206.
Illustratively, the protective layer may also be formed by a thermal oxidation method, such as furnace oxidation, rapid thermal annealing oxidation (RTO), in-situ steam oxidation (ISSG), and the like. In an embodiment of the present invention, a rapid thermal anneal oxidation (RTO) is selected to deposit a protective layer 207 on the sidewalls of the control gate.
The method of forming the protective layer is not limited to the above two examples, and other methods may be used.
After a protective layer is formed on the side wall of the control gate, the side wall of the control gate is covered in a subsequent etching process so as to prevent the side wall of the control gate from being damaged in the etching process and keep a good profile of the control gate. In addition, because the protective layer is formed by an oxidation method, the gap between the control gates cannot be reduced, and electric leakage between the control gates can be further avoided.
Wherein the protective layer includes but is not limited to an oxide, and when the protective layer is selected from an oxide, the protective layer can be removed simultaneously when the isolation insulating layer and the floating gate material layer are etched later.
Optionally, in this step, the protective layer is not formed on the isolation insulating layer.
Next, as shown in fig. 2C, the isolation insulating layer and the floating gate material layer are etched using the control gate as a mask to form a floating gate.
Optionally, the protective layer is removed simultaneously with or after etching the isolation insulating layer and the floating gate material layer.
Further, at least part of the hard mask layer and/or the isolation oxide in the shallow trench isolation structure is removed while or after the isolation insulating layer and the floating gate material layer are etched.
In this step, the isolation insulating layer and the floating gate material layer exposed between the control gates are etched using the control gates as masks to form floating gates.
And in the etching process, the side wall of the control gate is covered by the protective layer, so that the side wall of the control gate cannot be damaged. Leakage between the control gates can be further avoided.
Now, the process steps performed by the method according to the embodiment of the present invention are completed, and it is understood that the method for manufacturing a semiconductor device according to the embodiment of the present invention may include not only the above steps, but also other required steps before, during, or after the above steps, such as etching of the control gate/floating gate of the peripheral region, and manufacturing of a NAND device memory region (cell), which are included in the scope of the manufacturing method of the present embodiment.
It can be understood that, in the manufacturing method of the semiconductor device provided by the present invention, after the control gate is formed and before the floating gate material layer is etched, the protection layer is formed on the exposed sidewall of the control gate to protect the sidewall of the control gate from being damaged in the subsequent process of etching the floating gate material layer, so that the obtained control gate has a good profile. In addition, the protective layer is formed by an oxidation method, so that the gap between the control gates cannot be reduced, the electric leakage between the control gates can be further avoided, and the performance and the yield of the semiconductor device are further improved.
In addition, the invention also provides a semiconductor device.
The semiconductor device includes:
a semiconductor substrate;
a floating gate, an isolation insulating layer and a control gate on the semiconductor substrate.
Wherein the semiconductor substrate may be at least one of the following materials: si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, or other III/V compound semiconductors, and also includes multilayer structures of these semiconductors, or silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-germanium (S-SiGeOI), silicon-on-insulator-germanium (SiGeOI), and germanium-on-insulator (GeOI). Devices, such as NMOS and/or PMOS, etc., may be formed on the semiconductor substrate. Also, a conductive member may be formed in the semiconductor substrate, and the conductive member may be a gate, a source, or a drain of a transistor, a metal interconnection structure electrically connected to the transistor, or the like. In this embodiment, the constituent material of the semiconductor substrate is monocrystalline silicon.
The semiconductor device of the embodiment is prepared by the method, and the protective layer is formed on the side wall of the control gate in the process of etching the floating gate so as to prevent the side wall of the control gate from being damaged, so that the control gate has a better profile. In addition, the protective layer is formed by an oxidation method, so that the gap between the control gates cannot be reduced, the electric leakage between the control gates can be further avoided, and the performance and the yield of the semiconductor device are further improved.
Yet another embodiment of the present invention provides an electronic device including the above-mentioned embodiments
The semiconductor device and an electronic component connected with the semiconductor device.
The electronic component may be any electronic component such as a discrete device and an integrated circuit.
The electronic device of this embodiment may be any electronic product or device such as a mobile phone, a tablet computer, a notebook computer, a netbook, a game machine, a television, a VCD, a DVD, a navigator, a camera, a video camera, a voice pen, an MP3, an MP4, and a PSP, and may also be any intermediate product including the semiconductor device.
Wherein figure 3 shows an example of a handset. The exterior of the cellular phone 300 is provided with a display portion 302, operation buttons 303, an external connection port 304, a speaker 305, a microphone 306, and the like, which are included in a housing 301.
The electronic device of the embodiment of the invention also has similar advantages due to the fact that the electronic device comprises the semiconductor device.
The present invention has been illustrated by the above embodiments, but it should be understood that the above embodiments are for illustrative and descriptive purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications may be made in accordance with the teachings of the present invention, which variations and modifications are within the scope of the present invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.
Claims (10)
1. A method for manufacturing a semiconductor device, comprising the steps of:
providing a semiconductor substrate, and forming a floating gate material layer, an isolation insulating layer, a control gate material layer and a mask layer on the semiconductor substrate;
patterning the mask layer and the control gate material layer to form a plurality of control gates which are mutually spaced;
oxidizing the side wall of the control gate to form a protective layer on the side wall of the control gate;
and etching the isolation insulating layer and the floating gate material layer by taking the control gate as a mask to form a floating gate.
2. The method of manufacturing a semiconductor device according to claim 1, wherein the protective layer is formed by an SPA oxidation process or a rapid thermal annealing oxidation process.
3. The method of manufacturing a semiconductor device according to claim 1, wherein the control gate material layer is formed using silicon or polysilicon.
4. The method for manufacturing a semiconductor device according to claim 1, wherein the protective layer is not formed on the insulating isolation layer.
5. The method of claim 1, wherein a strip-shaped floating gate material layer is formed on the semiconductor substrate, and the mask layer and the control gate material layer are patterned to form a plurality of control gates spaced from each other in an extending direction of the strip-shaped floating gate material layer.
6. The method of manufacturing a semiconductor device according to claim 5, wherein an isolation structure is further formed in the semiconductor substrate between the floating gate material layers to isolate adjacent ones of the strip-shaped floating gate material layers.
7. The method for manufacturing a semiconductor device according to claim 1, wherein the protective layer is removed simultaneously with or after etching the isolation insulating layer and the floating gate material layer.
8. The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is a NAND memory cell.
9. A semiconductor device, characterized in that it is produced by a method according to one of claims 1 to 8.
10. An electronic device comprising the semiconductor device according to claim 9.
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