CN115298819B - 包括衬底以及与衬底耦合的高密度互连集成器件的封装件 - Google Patents

包括衬底以及与衬底耦合的高密度互连集成器件的封装件

Info

Publication number
CN115298819B
CN115298819B CN202180021997.7A CN202180021997A CN115298819B CN 115298819 B CN115298819 B CN 115298819B CN 202180021997 A CN202180021997 A CN 202180021997A CN 115298819 B CN115298819 B CN 115298819B
Authority
CN
China
Prior art keywords
integrated device
substrate
interconnect
interconnects
integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202180021997.7A
Other languages
English (en)
Chinese (zh)
Other versions
CN115298819A (zh
Inventor
R·莱尼
L-S·翁
C·D·佩恩特
E·D·福隆达
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qualcomm Inc
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of CN115298819A publication Critical patent/CN115298819A/zh
Application granted granted Critical
Publication of CN115298819B publication Critical patent/CN115298819B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/401—Package configurations characterised by multiple insulating or insulated package substrates, interposers or RDLs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H10W72/252—Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/381—Auxiliary members
    • H10W72/387—Flow barriers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/22—Configurations of stacked chips the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Combinations Of Printed Boards (AREA)
  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
CN202180021997.7A 2020-03-23 2021-03-18 包括衬底以及与衬底耦合的高密度互连集成器件的封装件 Active CN115298819B (zh)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US202062993544P 2020-03-23 2020-03-23
US62/993,544 2020-03-23
US17/017,361 US11605594B2 (en) 2020-03-23 2020-09-10 Package comprising a substrate and a high-density interconnect integrated device coupled to the substrate
US17/017,361 2020-09-10
PCT/US2021/023035 WO2021194857A1 (en) 2020-03-23 2021-03-18 Package comprising a substrate and a high-density interconnect integrated device coupled to the substrate

Publications (2)

Publication Number Publication Date
CN115298819A CN115298819A (zh) 2022-11-04
CN115298819B true CN115298819B (zh) 2025-08-22

Family

ID=77748271

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202180021997.7A Active CN115298819B (zh) 2020-03-23 2021-03-18 包括衬底以及与衬底耦合的高密度互连集成器件的封装件

Country Status (8)

Country Link
US (1) US11605594B2 (enExample)
EP (1) EP4128347A1 (enExample)
JP (2) JP7791095B2 (enExample)
KR (1) KR20220157959A (enExample)
CN (1) CN115298819B (enExample)
BR (1) BR112022018379A2 (enExample)
PH (1) PH12022551934A1 (enExample)
WO (1) WO2021194857A1 (enExample)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI738525B (zh) * 2020-09-24 2021-09-01 矽品精密工業股份有限公司 電子封裝件及其製法
US11658123B2 (en) * 2020-09-25 2023-05-23 Advanced Micro Devices, Inc. Hybrid bridged fanout chiplet connectivity

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0438080U (enExample) * 1990-07-30 1992-03-31
JPH05110024A (ja) * 1991-10-18 1993-04-30 Sharp Corp 半導体装置及びその製造方法
JPH1051147A (ja) * 1996-07-29 1998-02-20 Oki Electric Ind Co Ltd 分岐配線部品および配線構造
WO2006011320A1 (ja) * 2004-07-30 2006-02-02 Murata Manufacturing Co., Ltd. 複合型電子部品及びその製造方法
US7969009B2 (en) * 2008-06-30 2011-06-28 Qualcomm Incorporated Through silicon via bridge interconnect
US9059179B2 (en) 2011-12-28 2015-06-16 Broadcom Corporation Semiconductor package with a bridge interposer
US9831170B2 (en) * 2011-12-30 2017-11-28 Deca Technologies, Inc. Fully molded miniaturized semiconductor module
US9250403B2 (en) * 2013-04-26 2016-02-02 Oracle International Corporation Hybrid-integrated photonic chip package with an interposer
US9230936B2 (en) * 2014-03-04 2016-01-05 Qualcomm Incorporated Integrated device comprising high density interconnects and redistribution layers
US9666559B2 (en) 2014-09-05 2017-05-30 Invensas Corporation Multichip modules and methods of fabrication
US9368450B1 (en) * 2015-08-21 2016-06-14 Qualcomm Incorporated Integrated device package comprising bridge in litho-etchable layer
US20170092594A1 (en) * 2015-09-25 2017-03-30 Qualcomm Incorporated Low profile package with passive device
US9761533B2 (en) 2015-10-16 2017-09-12 Xilinx, Inc. Interposer-less stack die interconnect
US9799616B2 (en) 2016-03-08 2017-10-24 Dyi-chung Hu Package substrate with double sided fine line RDL
WO2017164810A1 (en) 2016-03-21 2017-09-28 Agency For Science, Technology And Research Semiconductor package and method of forming the same
WO2017171738A1 (en) * 2016-03-30 2017-10-05 Intel Corporation Hybrid microelectronic substrates
US10510721B2 (en) 2017-08-11 2019-12-17 Advanced Micro Devices, Inc. Molded chip combination
DE112017008327T5 (de) 2017-12-29 2020-10-08 Intel Corporation Mikroelektronische anordnungen
US10580738B2 (en) 2018-03-20 2020-03-03 International Business Machines Corporation Direct bonded heterogeneous integration packaging structures
US11869842B2 (en) * 2019-07-24 2024-01-09 Intel Corporation Scalable high speed high bandwidth IO signaling package architecture and method of making
US11289453B2 (en) * 2020-02-27 2022-03-29 Qualcomm Incorporated Package comprising a substrate and a high-density interconnect structure coupled to the substrate

Also Published As

Publication number Publication date
US20210296246A1 (en) 2021-09-23
US11605594B2 (en) 2023-03-14
EP4128347A1 (en) 2023-02-08
JP2025166172A (ja) 2025-11-05
TW202141711A (zh) 2021-11-01
CN115298819A (zh) 2022-11-04
KR20220157959A (ko) 2022-11-29
JP7791095B2 (ja) 2025-12-23
JP2023519145A (ja) 2023-05-10
PH12022551934A1 (en) 2023-11-29
BR112022018379A2 (pt) 2022-11-08
WO2021194857A1 (en) 2021-09-30

Similar Documents

Publication Publication Date Title
CN115210867B (zh) 包括衬底和与其耦接的高密度互连结构的半导体封装
US20220149005A1 (en) Package comprising a substrate and a high-density interconnect integrated device
JP2025166172A (ja) 基板と基板に結合された高密度相互接続集積デバイスとを含むパッケージ
JP7765480B2 (ja) 対角ルーティング用に構成された基板および相互接続デバイスを備えるパッケージ
CN116868336A (zh) 具有包括焊盘上焊盘互连件的衬底的封装件
TWI891783B (zh) 包括嵌入在核心層中的高密度互連部分的基板
US20250070086A1 (en) Package-on-package device including redistribution die
TWI922462B (zh) 包括基板以及耦合至基板的高密度互連整合元件的封裝
US20240363513A1 (en) Package comprising a package substrate that includes an encapsulated portion with interconnection portion blocks
US20240105568A1 (en) Package comprising a substrate with interconnects
CN116783706A (zh) 具有包括外围互连件的衬底的封装件
CN121844761A (zh) 包括具有互连块的基板的封装件
CN121002663A (zh) 包括包含具有互连部分块的包封部分的封装基板的封装件

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant