CN115241161A - Capacitor forming method - Google Patents

Capacitor forming method Download PDF

Info

Publication number
CN115241161A
CN115241161A CN202210916400.1A CN202210916400A CN115241161A CN 115241161 A CN115241161 A CN 115241161A CN 202210916400 A CN202210916400 A CN 202210916400A CN 115241161 A CN115241161 A CN 115241161A
Authority
CN
China
Prior art keywords
electrode layer
opening
layer
forming
patterned
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202210916400.1A
Other languages
Chinese (zh)
Inventor
辛春艳
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fengfeixin Shanghai Technology Co ltd
Original Assignee
Fengfeixin Shanghai Technology Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fengfeixin Shanghai Technology Co ltd filed Critical Fengfeixin Shanghai Technology Co ltd
Priority to CN202210916400.1A priority Critical patent/CN115241161A/en
Publication of CN115241161A publication Critical patent/CN115241161A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/642—Capacitive arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

The application provides a method for forming a capacitor, which comprises the following steps: providing a semiconductor substrate, wherein a plurality of grooves are formed in the semiconductor substrate, a first electrode layer, a second electrode layer, a third electrode layer and a fourth electrode layer which are used for filling the grooves are sequentially formed in the grooves and on the surface of the semiconductor substrate, and a plurality of first openings which expose the second electrode layer are formed in the third electrode layer and the fourth electrode layer between adjacent grooves; and forming a second opening which exposes the first electrode layer in the second electrode layer exposed by the first opening, and simultaneously forming a third opening which exposes the third electrode layer in the fourth electrode layer. The application provides a capacitor forming method, a combination of a mode of etching two or more electrode layers by one-time photoetching and a mode of etching a single electrode layer by one-time photoetching can reduce the times of photoetching process but realize connection of all electrode layers, simplify the process and save the cost.

Description

Capacitor forming method
Technical Field
The present application relates to the field of semiconductor technologies, and in particular, to a method for forming a capacitor.
Background
With the continuous reduction of the size and the continuous improvement of the integration level of the semiconductor device, the performance of the capacitor needs to be improved, that is, the charge storage capacity of the capacitor is increased on the premise of reducing the area of the capacitor. It is well known that deep trench capacitor devices greatly reduce the area occupied by the capacitor. However, to further increase the capacitance of the capacitor, more electrode layers need to be formed, increasing the total area of the electrode layers.
However, as the number of electrode layers increases, more photolithography processes are required to form contact structures for electrically connecting different electrode layers in subsequent processes, which makes the process complicated and the cost higher. Therefore, there is a need to provide more efficient and reliable solutions.
Disclosure of Invention
The application provides a capacitor forming method which can reduce the times of photoetching process, simplify the process and save the cost.
One aspect of the present application provides a method of forming a capacitor, including: providing a semiconductor substrate, wherein a plurality of grooves are formed in the semiconductor substrate, a first electrode layer, a second electrode layer, a third electrode layer and a fourth electrode layer which are used for filling the grooves are sequentially formed in the grooves and on the surface of the semiconductor substrate, and a plurality of first openings which expose the second electrode layer are formed in the third electrode layer and the fourth electrode layer between adjacent grooves; forming a second opening in the second electrode layer exposed by the first opening to expose the first electrode layer, and simultaneously forming a third opening in the fourth electrode layer to expose the third electrode layer; forming a dielectric layer covering the first electrode layer, the second electrode layer, the third electrode layer and the fourth electrode layer on the semiconductor substrate; and forming a contact structure which penetrates through the dielectric layer and is respectively and electrically connected with the first electrode layer, the second electrode layer, the third electrode layer and the fourth electrode layer in the dielectric layer.
In some embodiments of the present application, a method of forming a number of first openings in a third electrode layer and a fourth electrode layer between adjacent trenches to expose the second electrode layer includes: providing a semiconductor substrate, wherein a plurality of grooves are formed in the semiconductor substrate, and a first electrode layer, a second electrode layer, a third electrode layer and a fourth electrode layer which are filled in the grooves and the surface of the semiconductor substrate are sequentially formed in the grooves and the surface of the semiconductor substrate; forming a patterned first photoresist layer on the surface of the fourth electrode layer, wherein the patterned first photoresist layer defines the position of the first opening; etching the fourth electrode layer and the third electrode layer by using the patterned first photoresist layer as a mask to form the first opening; and removing the patterned first photoresist layer.
In some embodiments of the present application, a method of forming a second opening exposing the first electrode layer in the second electrode layer exposed by the first opening, and simultaneously forming a third opening exposing the third electrode layer in the fourth electrode layer includes: forming a second patterned photoresist layer on the surface of the second electrode layer exposed by the first opening and the surface of the fourth electrode layer, wherein the second patterned photoresist layer defines the positions of the second opening and the third opening; simultaneously etching the second electrode layer exposed by the first opening and the fourth electrode layer by using the patterned second photoresist layer as a mask to form a second opening and a third opening; and removing the patterned second photoresist layer.
In some embodiments of the present application, the patterned second photoresist layer includes a fourth opening and a fifth opening, wherein the fourth opening defines a position of the second opening, and the fifth opening defines a position of the third opening.
In some embodiments of the present application, the patterned second photoresist layer includes a sixth opening located at a boundary of the first opening while defining positions of the second opening and the third opening.
In some embodiments of the present application, a first insulating layer is further formed between the first electrode layer and the second electrode layer; a second insulating layer is further formed between the second electrode layer and the third electrode layer; and a third insulating layer is formed between the third electrode layer and the fourth electrode layer.
Another aspect of the present application provides a method of forming a capacitor, including: providing a semiconductor substrate, wherein a plurality of grooves are formed in the semiconductor substrate, a first electrode layer, a second electrode layer, a third electrode layer and a fourth electrode layer which are used for filling the grooves are sequentially formed in the grooves and on the surface of the semiconductor substrate, and a plurality of first openings which expose the third electrode layer are formed in the fourth electrode layer between the adjacent grooves; forming a second opening exposing the first electrode layer in the third electrode layer and the second electrode layer at the bottom of the first opening, and simultaneously forming a third opening exposing the second electrode layer in the fourth electrode layer and the third electrode layer; forming a dielectric layer covering the first electrode layer, the second electrode layer, the third electrode layer and the fourth electrode layer on the semiconductor substrate; and forming a contact structure which penetrates through the dielectric layer and is respectively and electrically connected with the first electrode layer, the second electrode layer, the third electrode layer and the fourth electrode layer in the dielectric layer.
In some embodiments of the present application, a method of forming a number of first openings in a fourth electrode layer between adjacent trenches exposing the third electrode layer comprises: providing a semiconductor substrate, wherein a plurality of grooves are formed in the semiconductor substrate, and a first electrode layer, a second electrode layer, a third electrode layer and a fourth electrode layer which are filled in the grooves are sequentially formed in the grooves and on the surface of the semiconductor substrate; forming a patterned first photoresist layer on the surface of the fourth electrode layer, wherein the patterned first photoresist layer defines the position of the first opening; etching the fourth electrode layer by using the patterned first photoresist layer as a mask to form the first opening; and removing the patterned first photoresist layer.
In some embodiments of the present application, a method of forming a second opening in the third electrode layer and the second electrode layer at the bottom of the first opening to expose the first electrode layer, and simultaneously forming a third opening in the fourth electrode layer and the third electrode layer to expose the second electrode layer, includes: forming a second patterned photoresist layer on the surface of the third electrode layer exposed by the first opening and the surface of the fourth electrode layer, wherein the second patterned photoresist layer defines the positions of the second opening and the third opening; simultaneously etching the third electrode layer and the second electrode layer at the bottom of the first opening and the fourth electrode layer and the third electrode layer by taking the patterned second photoresist layer as a mask to form a second opening and a third opening; and removing the patterned second photoresist layer.
In some embodiments of the present application, the patterned second photoresist layer includes a fourth opening and a fifth opening, wherein the fourth opening defines a position of the second opening, and the fifth opening defines a position of the third opening.
In some embodiments of the present application, the patterned second photoresist layer includes a sixth opening located at a boundary of the first opening while defining positions of the second opening and the third opening.
In some embodiments of the present application, a first insulating layer is further formed between the first electrode layer and the second electrode layer; a second insulating layer is further formed between the second electrode layer and the third electrode layer; and a third insulating layer is formed between the third electrode layer and the fourth electrode layer.
The application provides a capacitor forming method, which can reduce the times of photoetching processes, simplify the processes and save the cost by adjusting the photoetching process combination when different electrode layers are etched.
Drawings
The following drawings describe in detail exemplary embodiments disclosed in the present application. Wherein like reference numerals represent similar structures throughout the several views of the drawings. Those of ordinary skill in the art will understand that the present embodiments are non-limiting, exemplary embodiments and that the accompanying drawings are for illustrative and descriptive purposes only and are not intended to limit the scope of the present application, as other embodiments may equally fulfill the inventive intent of the present application. It should be understood that the drawings are not to scale. Wherein:
FIGS. 1-6 are schematic structural diagrams of steps in a method of forming some capacitors;
FIG. 7 is a flow chart of a method of forming a capacitor according to some embodiments of the present application;
fig. 8-19 are schematic structural views of steps in a method of forming a capacitor according to some embodiments of the present application;
FIG. 20 is a flow chart of a method of forming a capacitor according to some embodiments of the present application;
fig. 21 to 32 are schematic structural diagrams of steps in a method for forming a capacitor according to other embodiments of the present application.
Detailed Description
The following description is presented to enable any person skilled in the art to make and use the present disclosure, and is provided in the context of a particular application and its requirements. Various modifications to the disclosed embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present application. Thus, the present application is not limited to the embodiments shown, but is to be accorded the widest scope consistent with the claims.
The technical solution of the present invention will be described in detail below with reference to the embodiments and the accompanying drawings.
Fig. 1 to 6 are schematic structural views of steps in a method for forming some capacitors.
Referring to fig. 1, a semiconductor substrate 100 is provided, a plurality of trenches 101 are formed in the semiconductor substrate 100, and a first electrode layer 110, a second electrode layer 120, a third electrode layer 130 and a fourth electrode layer 140 are sequentially formed in the plurality of trenches 101 and on a surface of the semiconductor substrate 100 to fill up the plurality of trenches 101.
A first insulating layer (not shown) is further formed between the first electrode layer 110 and the second electrode layer 120; a second insulating layer (not shown) is further formed between the second electrode layer 120 and the third electrode layer 130; a third insulating layer (not shown) is further formed between the third electrode layer 130 and the fourth electrode layer 140.
Referring to fig. 2, a first opening 151 exposing the third electrode layer 130 is formed in the fourth electrode layer 140 between the adjacent trenches 101 using a photolithography process.
Referring to fig. 3, a second opening 152 exposing the second electrode layer 120 is formed in the third electrode layer 130 exposed by the first opening 151 using a photolithography process.
Referring to fig. 4, a third opening 153 exposing the first electrode layer 110 is formed in the second electrode layer 120 exposed by the second opening 152 using a photolithography process.
Referring to fig. 5, a dielectric layer 160 covering the first electrode layer 110, the second electrode layer 120, the third electrode layer 130, and the fourth electrode layer 140 is formed on the semiconductor substrate 100.
Referring to fig. 6, a contact structure 170 penetrating the dielectric layer 160 and electrically connecting the first electrode layer 110, the second electrode layer 120, the third electrode layer 130 and the fourth electrode layer 140 is formed in the dielectric layer 160.
In the processes shown in fig. 1 to 6, the first opening 151, the second opening 152, and the third opening 153 are sequentially formed one by one, and thus a three-step photolithography process is required. However, the number of times of photolithography required in this manner is large, which leads to a complicated process, and in the semiconductor process, the photolithography process itself is a process with higher cost and higher difficulty, and the number of times of photolithography process leads to higher cost.
In view of the above problems, the present application provides a method for forming a capacitor, which can reduce the number of times of a photolithography process, simplify the process, and save the cost by adjusting the photolithography process combination when etching different electrode layers.
Fig. 7 is a flow chart of a method of forming a capacitor according to some embodiments of the present application.
Some embodiments of the present application provide a method of forming a capacitor, as described with reference to fig. 7, including:
step S1: providing a semiconductor substrate, wherein a plurality of grooves are formed in the semiconductor substrate, a first electrode layer, a second electrode layer, a third electrode layer and a fourth electrode layer which are used for filling the grooves are sequentially formed in the grooves and on the surface of the semiconductor substrate, and a plurality of first openings which expose the second electrode layer are formed in the third electrode layer and the fourth electrode layer between adjacent grooves;
step S2: forming a second opening in the second electrode layer exposed by the first opening to expose the first electrode layer, and simultaneously forming a third opening in the fourth electrode layer to expose the third electrode layer;
and step S3: forming a dielectric layer covering the first electrode layer, the second electrode layer, the third electrode layer and the fourth electrode layer on the semiconductor substrate;
and step S4: and forming a contact structure which penetrates through the dielectric layer and is respectively and electrically connected with the first electrode layer, the second electrode layer, the third electrode layer and the fourth electrode layer in the dielectric layer.
Fig. 8 to 16 are schematic structural diagrams of steps in a capacitor forming method according to some embodiments of the present application. A method for forming a capacitor according to some embodiments of the present application will be described in detail below with reference to the accompanying drawings.
Referring to fig. 7 and 8 to 11, in step S1, a semiconductor substrate 200 is provided, a plurality of trenches 201 are formed in the semiconductor substrate 200, a first electrode layer 210, a second electrode layer 220, a third electrode layer 230 and a fourth electrode layer 240 are sequentially formed in the plurality of trenches 201 and on the surface of the semiconductor substrate 200, the plurality of trenches 201 are filled with the first electrode layer 210, the second electrode layer 220, the third electrode layer 230 and the fourth electrode layer 240, and a plurality of first openings 261 exposing the second electrode layer 220 are formed in the third electrode layer 230 and the fourth electrode layer 240 between adjacent trenches 201.
Referring to fig. 8, a semiconductor substrate 200 is provided, a plurality of trenches 201 are formed in the semiconductor substrate 200, and a first electrode layer 210, a second electrode layer 220, a third electrode layer 230, and a fourth electrode layer 240 are sequentially formed in the plurality of trenches 201 and on the surface of the semiconductor substrate 200 to fill up the plurality of trenches 201.
In some embodiments of the present application, the material of the semiconductor substrate 200 includes (i) an elemental semiconductor, such as silicon or germanium; (ii) A compound semiconductor such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, or the like; (iii) Alloy semiconductors such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide, or gallium indium phosphide, or the like; or (iv) combinations of the foregoing. In addition, the semiconductor substrate 200 may be doped (e.g., a P-type substrate or an N-type substrate). In some embodiments of the present application, the semiconductor substrate 200 may be doped with a P-type dopant (e.g., boron, indium, aluminum, or gallium) or an N-type dopant (e.g., phosphorus or arsenic).
In some embodiments of the present application, the materials of the first electrode layer 210, the second electrode layer 220, the third electrode layer 230, and the fourth electrode layer 240 include metals or metal compounds, such as aluminum, tungsten, and the like.
In some embodiments of the present application, a first insulating layer (not shown) is further formed between the first electrode layer 210 and the second electrode layer 220; a second insulating layer (not shown) is further formed between the second electrode layer 220 and the third electrode layer 230; a third insulating layer (not shown) is further formed between the third electrode layer 230 and the fourth electrode layer 240. The thicknesses of the first, second, and third insulating layers are thinner than the thicknesses of the first, second, third, and fourth electrode layers 210, 220, 230, and 240, and thus the first, second, and third insulating layers are not shown in the drawings for the sake of brevity. It will be understood by those skilled in the art that the first, second and third insulating layers are objectively present as a basic constituent structure of the deep trench capacitor.
In some embodiments of the present application, the material of the first insulating layer, the second insulating layer and the third insulating layer is an insulating dielectric material, such as silicon oxide or silicon nitride.
Referring to fig. 9, a patterned first photoresist layer 251 is formed on the surface of the fourth electrode layer 240, and the patterned first photoresist layer 251 defines the position of the first opening 261.
Referring to fig. 10, the fourth electrode layer 240 and the third electrode layer 230 are etched using the patterned first photoresist layer 251 as a mask to form the first opening 261.
Referring to fig. 11, the patterned first photoresist layer 251 is removed.
In some embodiments of the present application, the first opening 261 is not located in the middle of adjacent trenches 201, but is located near one of the adjacent trenches 201. This is to allow sufficient space for the subsequently formed third opening. The width of the first opening 261 cannot be too small, otherwise the space for subsequently forming the second opening is too small; the width of the first opening 261 cannot be too large, otherwise the space for subsequently forming the third opening is too small.
Referring to fig. 7 and 12 to 17, in step S2, a second opening 262 exposing the first electrode layer 210 is formed in the second electrode layer 220 exposed by the first opening 261, and a third opening 263 exposing the third electrode layer 230 is formed in the fourth electrode layer 240.
Referring to fig. 12, a patterned second photoresist layer 252 is formed on the surface of the second electrode layer 220 exposed by the first opening 261 and the surface of the fourth electrode layer 240, and the patterned second photoresist layer 252 defines the positions of the second opening 262 and the third opening 263.
In some embodiments of the present application, the patterned second photoresist layer 252 includes a fourth opening 264 and a fifth opening 265, wherein the fourth opening 264 defines the position of the second opening 262, and the fifth opening 265 defines the position of the third opening 263.
Referring to fig. 13, the second electrode layer 220 exposed by the first opening and the fourth electrode layer 240 are etched simultaneously by using the patterned second photoresist layer 252 as a mask to form the second opening 262 and the third opening 263.
Referring to fig. 14, the patterned second photoresist layer 252 is removed.
Referring to fig. 15 (fig. 15 is a subsequent view of fig. 11 in further embodiments), in further embodiments of the present application, the patterned second photoresist layer 252 includes sixth openings 266, the sixth openings 266 being located at the boundaries of the first openings and defining the positions of the second openings 262 and the third openings 263.
Referring to fig. 16, the second electrode layer 220 exposed by the first opening and the fourth electrode layer 240 are etched at the same time by using the patterned second photoresist layer 252 as a mask to form the second opening 262 and the third opening 263.
Referring to fig. 17, the patterned second photoresist layer 252 is removed.
In the technical solutions shown in fig. 15 to 17, the second opening 262 and the third opening 263 are simultaneously etched and formed only by the first opening and the sixth opening 266, so that the process difficulty can be simplified, and the etching dose can be saved.
Compared with the solutions shown in fig. 1 to fig. 6, in the solution of the present application, the first opening 261, the second opening 262, and the third opening 263 can be formed only by performing two photolithography processes using two photomasks (the patterned first photoresist layer 251 and the patterned second photoresist layer 252). The process is simplified, the photoetching steps are saved, and the cost is saved. The technical scheme of the application can also be continuously applied to a capacitor comprising more electrode layers, for example, five electrode layers, or a semiconductor substrate is also used as an electrode layer. And the opening of all the electrode layers can be made in a minimum of three times of photoetching and etching under the condition that the semiconductor substrate is also used as the electrode layer and the total electrode layer is five layers or six layers.
Specifically, in the technical solutions shown in fig. 1 to 6, the electrode layer is etched layer by layer, and only one electrode layer is etched and exposed by photolithography each time. Therefore, when the number of the electrode layers is n, n-1 etching is required to expose each electrode layer. For example, when the electrode layer is four layers, the etching needs to be performed three times; when the electrode layer is five layers, etching is needed for four times; when the electrode layer is six layers, etching is needed five times; when the electrode layer is seven layers, six times of etching are needed; when the electrode layer is eight layers, etching is needed for seven times; when the electrode layer is nine layers, eight times of etching are needed.
In the technical scheme of the application, the electrode layer is not etched layer by layer, and two electrode layers or multiple electrode layers are partially etched at one time by changing the photoetching pattern and the number of etching layers, so that the etching times required for exposing all the electrode layers can be reduced. Specifically, the applicant finds that the relationship between the etching times and the number of electrode layers in the technical scheme of the present application is 2 m > (n-1), where n is the total number of electrode layers, the number of times of photolithography (or etching) that can be used to extract the electrode layer from each electrode layer at a time through the contact hole is the smallest positive integer of m that satisfies the above inequality. For example, when the electrode layer is four layers,etching is required to be performed two to three times (minimum two etches); when the electrode layer is five layers, three to four times of etching is needed (the lowest three times of etching); when the electrode layer is six layers, three to five times of etching are needed (the minimum three times of etching); when the electrode layer is seven layers, three to six times of etching (the lowest three times of etching) are needed; when the electrode layer is eight layers, three to seven times of etching (the lowest three times of etching) are needed; when the electrode layer is nine layers, four to eight times of etching are required (the minimum four times of etching).
Referring to fig. 18 (fig. 18 is a diagram subsequent to fig. 17), in step S3, a dielectric layer 270 covering the first electrode layer 210, the second electrode layer 220, the third electrode layer 230, and the fourth electrode layer 240 is formed on the semiconductor substrate 200.
In some embodiments of the present application, the material of the dielectric layer 270 includes silicon oxide. The method for forming the dielectric layer 270 includes a chemical vapor deposition process or a physical vapor deposition process.
Referring to fig. 19, in step S4, a contact structure 280 penetrating through the dielectric layer 270 and electrically connected to the first electrode layer 210, the second electrode layer 220, the third electrode layer 230, and the fourth electrode layer 240 is formed in the dielectric layer 270.
In some embodiments of the present application, the material of the contact structure 280 is a metal material or a metal compound, such as tungsten, aluminum, cobalt, or the like. Methods of forming the contact structure 280 include a chemical vapor deposition process or a physical vapor deposition process, etc.
The application provides a capacitor forming method, which can reduce the times of photoetching processes, simplify the processes and save the cost by adjusting the photoetching process combination when different electrode layers are etched.
Fig. 20 is a flow chart of a method of forming a capacitor according to some embodiments of the present application.
Some embodiments of the present application further provide a method for forming a capacitor, which is described with reference to fig. 20, and includes:
step S10: providing a semiconductor substrate, wherein a plurality of grooves are formed in the semiconductor substrate, a first electrode layer, a second electrode layer, a third electrode layer and a fourth electrode layer which are used for filling the grooves are sequentially formed in the grooves and on the surface of the semiconductor substrate, and a plurality of first openings which expose the third electrode layer are formed in the fourth electrode layer between the adjacent grooves;
step S20: forming a second opening exposing the first electrode layer in the third electrode layer and the second electrode layer at the bottom of the first opening, while forming a third opening exposing the second electrode layer in the fourth electrode layer and the third electrode layer;
step S30: forming a dielectric layer covering the first electrode layer, the second electrode layer, the third electrode layer and the fourth electrode layer on the semiconductor substrate;
step S40: and forming a contact structure which penetrates through the dielectric layer and is respectively and electrically connected with the first electrode layer, the second electrode layer, the third electrode layer and the fourth electrode layer in the dielectric layer.
Fig. 21 to 32 are schematic structural diagrams of steps in a capacitor forming method according to other embodiments of the present application.
Referring to fig. 20 and fig. 21 to 24, in step S10, a semiconductor substrate 300 is provided, a plurality of trenches 301 are formed in the semiconductor substrate 300, a first electrode layer 310, a second electrode layer 320, a third electrode layer 330 and a fourth electrode layer 340 are sequentially formed in the plurality of trenches 301 and on the surface of the semiconductor substrate 300, the first electrode layer 310, the second electrode layer 320, the third electrode layer 330 and the fourth electrode layer 340 filling the plurality of trenches 301, wherein a plurality of first openings 361 exposing the third electrode layer 330 are formed in the fourth electrode layer 340 between adjacent trenches 301.
Referring to fig. 21, a semiconductor substrate 300 is provided, a plurality of trenches 301 are formed in the semiconductor substrate 300, and a first electrode layer 310, a second electrode layer 320, a third electrode layer 330 and a fourth electrode layer 340 are sequentially formed in the plurality of trenches 301 and on the surface of the semiconductor substrate 300 to fill up the plurality of trenches 301.
In some embodiments of the present application, the material of the semiconductor substrate 300 includes (i) elemental semiconductors such as silicon or germanium; (ii) A compound semiconductor such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, or the like; (iii) Alloy semiconductors such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide, or gallium indium phosphide, or the like; or (iv) combinations of the foregoing. In addition, the semiconductor substrate 300 may be doped (e.g., a P-type substrate or an N-type substrate). In some embodiments of the present application, the semiconductor substrate 300 may be doped with a P-type dopant (e.g., boron, indium, aluminum, or gallium) or an N-type dopant (e.g., phosphorus or arsenic).
In some embodiments of the present application, the materials of the first electrode layer 310, the second electrode layer 320, the third electrode layer 330 and the fourth electrode layer 340 include metals or metal compounds, such as aluminum, tungsten, and the like.
In some embodiments of the present application, a first insulating layer (not shown) is further formed between the first electrode layer 310 and the second electrode layer 320; a second insulating layer (not shown) is further formed between the second electrode layer 320 and the third electrode layer 330; a third insulating layer (not shown) is further formed between the third electrode layer 330 and the fourth electrode layer 340. The thicknesses of the first, second, and third insulating layers are thinner than the thicknesses of the first, second, third, and fourth electrode layers 310, 320, 330, and 340, and thus the first, second, and third insulating layers are not shown in the drawings for the sake of brevity. It will be understood by those skilled in the art that the first, second and third insulating layers are objectively present as a basic constituent structure of the deep trench capacitor.
In some embodiments of the present application, the material of the first insulating layer, the second insulating layer and the third insulating layer is an insulating dielectric material, such as silicon oxide or silicon nitride.
Referring to fig. 22, a patterned first photoresist layer 351 is formed on the surface of the fourth electrode layer 340, and the patterned first photoresist layer 351 defines the position of the first opening 361.
Referring to fig. 23, the fourth electrode layer 340 is etched using the patterned first photoresist layer 351 as a mask to form the first opening 361.
Referring to fig. 24, the patterned first photoresist layer 351 is removed.
In some embodiments of the present application, the first opening 361 is not located in the middle of the adjacent trenches 301, but is located near one of the adjacent trenches 301. This is to allow sufficient space for the third opening to be formed later. The width of the first opening 361 cannot be too small, otherwise the space for subsequently forming a second opening is too small; the width of the first opening 361 cannot be too large, otherwise the space for forming the third opening later is too small.
Referring to fig. 20 and 25 to 30, in step S20, a second opening 362 exposing the first electrode layer 310 is formed in the third electrode layer 330 and the second electrode layer 320 at the bottom of the first opening 361, and a third opening 363 exposing the second electrode layer 320 is formed in the fourth electrode layer 340 and the third electrode layer 330.
Referring to fig. 25, a patterned second photoresist layer 352 is formed on the surface of the third electrode layer 330 exposed by the first opening and the surface of the fourth electrode layer 340, and the patterned second photoresist layer 352 defines the positions of the second opening 362 and the third opening 363.
In some embodiments of the present application, the patterned second photoresist layer 352 includes a fourth opening 364 and a fifth opening 365, wherein the fourth opening 364 defines the position of the second opening 362, and the fifth opening 365 defines the position of the third opening 363.
Referring to fig. 26, the third electrode layer 330 and the second electrode layer 320 at the bottom of the first opening, and the fourth electrode layer 340 and the third electrode layer 330 are etched at the same time by using the patterned second photoresist layer 352 as a mask to form the second opening 362 and the third opening 363.
Referring to fig. 27, the patterned second photoresist layer 352 is removed.
Referring to FIG. 28 (FIG. 28 is a continuation of FIG. 24 in other embodiments), in other embodiments of the present application, the patterned second photoresist layer 352 includes sixth openings 366, the sixth openings 366 being located at the boundary of the first openings and defining the positions of the second openings 362 and the third openings 363.
Referring to fig. 29, the third electrode layer 330 and the second electrode layer 320 at the bottom of the first opening, and the fourth electrode layer 340 and the third electrode layer 330 are etched at the same time by using the patterned second photoresist layer 352 as a mask to form the second opening 362 and the third opening 363.
Referring to fig. 30, the patterned second photoresist layer 352 is removed.
In the technical solutions shown in fig. 28 to fig. 30, the second opening 362 and the third opening 363 are simultaneously etched by using only the first opening and the sixth opening 366, so that the process difficulty can be simplified, and the etching dosage can be saved.
Compared with the solutions shown in fig. 1 to fig. 6, in the solution of the present application, the first opening 361, the second opening 362, and the third opening 363 can be formed by performing the photolithography process twice with only two masks (the patterned first photoresist layer 351 and the patterned second photoresist layer 352). The process is simplified, the photoetching steps are saved, and the cost is saved. The technical solution of the present application can also be continuously applied to a capacitor including more electrode layers, for example, five electrode layers, or a semiconductor substrate serving as an electrode layer. And the opening of all the electrode layers can be made in a minimum of three times of photoetching and etching under the condition that the semiconductor substrate is also used as the electrode layer and the total electrode layer is five layers or six layers.
Specifically, in the technical solutions shown in fig. 1 to 6, the electrode layer is etched layer by layer, and only one electrode layer is etched and exposed by photolithography each time. Therefore, when the number of the electrode layers is n, n-1 etching is required to expose each electrode layer. For example, when the electrode layer is four, three times of etching is needed; when the electrode layer is five layers, etching is needed for four times; when the electrode layer is six layers, etching is needed five times; when the electrode layer is seven layers, six times of etching is needed; when the electrode layer is eight layers, etching is needed for seven times; when the electrode layer is nine layers, eight times of etching are needed.
In the technical scheme of the application, the electrode layer is not etched layer by layer, and partial etching is carried out once by changing the photoetching pattern and the etching layer numberEtching two or more electrode layers can reduce the number of etching times required to expose all electrode layers. Specifically, the applicant finds that the relationship between the etching times and the number of electrode layers in the technical scheme of the present application is 2 m > (n-1), where n is the total number of electrode layers, the number of times of photolithography (or etching) that can be used to extract the electrode layer from each electrode layer at a time through the contact hole is the smallest positive integer of m that satisfies the above inequality. For example, when the electrode layer is four layers, the etching needs to be performed twice to three times (the minimum two times of etching); when the electrode layer is five layers, three to four times of etching is needed (the lowest three times of etching); when the electrode layer is six layers, three to five times of etching are needed (the minimum three times of etching); when the electrode layer is seven layers, three to six times of etching (the lowest three times of etching) are needed; when the electrode layer is eight layers, three to seven times of etching (the lowest three times of etching) are needed; when the electrode layer is nine layers, four to eight times of etching are required (the minimum four times of etching).
Referring to fig. 31 (fig. 31 is a diagram subsequent to fig. 30), in step S30, a dielectric layer 370 covering the first electrode layer 310, the second electrode layer 320, the third electrode layer 330, and the fourth electrode layer 340 is formed on the semiconductor substrate 300.
In some embodiments of the present application, the material of the dielectric layer 370 includes silicon oxide. The method for forming the dielectric layer 370 includes a chemical vapor deposition process or a physical vapor deposition process.
Referring to fig. 32, in step S40, a contact structure 380 penetrating through the dielectric layer 370 and electrically connected to the first electrode layer 310, the second electrode layer 320, the third electrode layer 330 and the fourth electrode layer 340 is formed in the dielectric layer 370.
In some embodiments of the present application, the material of the contact structure 380 is a metal material or a metal compound, such as tungsten, aluminum, cobalt, or the like. Methods of forming the contact structure 380 include a chemical vapor deposition process or a physical vapor deposition process, etc.
According to the technical scheme, the photoetching process combination during etching of different electrode layers is adjusted, so that the times of the photoetching process can be reduced, the process is simplified, and the cost is saved. The main technical principle is that the etching of one electrode layer and one electrode layer is not carried out any more as in the conventional process, but a part of the electrode layer can be exposed simultaneously after etching through process adjustment, so that the times of the etching process are saved. In addition, the present application is only exemplified by a capacitor with four electrode layers. In fact, capacitors with a larger number of electrode layers may also be suitable for the technical principles of the present application, such as five-layer, 6-layer electrode layers, etc. Also, in some capacitors, the semiconductor substrate is also treated as an electrode layer, and in such a structure, the technical principle of the present application is also applicable.
The application provides a capacitor forming method, which can reduce the times of photoetching processes, simplify the processes and save the cost by adjusting the photoetching process combination when different electrode layers are etched.
In summary, after reading the present disclosure, those skilled in the art will appreciate that the foregoing may be presented by way of example only, and may not be limiting. Those skilled in the art will appreciate that the present application is intended to cover various reasonable variations, adaptations, and modifications of the embodiments described herein, although not explicitly described herein. Such alterations, modifications, and variations are intended to be within the spirit and scope of the exemplary embodiments of this application.
It is to be understood that the term "and/or" as used herein in this embodiment includes any and all combinations of one or more of the associated listed items. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may also be present.
Similarly, it will be understood that when an element such as a layer, region or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. In contrast, the term "directly" means that there are no intervening elements. It will be further understood that the terms "comprises," "comprising," "includes" or "including," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It will be further understood that, although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, a first element in some embodiments may be termed a second element in other embodiments without departing from the teachings of the present application. The same reference numerals or the same reference characters denote the same elements throughout the specification.
Further, the present specification describes example embodiments with reference to idealized example cross-sectional and/or plan and/or perspective views. Accordingly, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, example embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region shown as a rectangle will typically have rounded or curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of exemplary embodiments.

Claims (12)

1. A method of forming a capacitor, comprising:
providing a semiconductor substrate, wherein a plurality of grooves are formed in the semiconductor substrate, a first electrode layer, a second electrode layer, a third electrode layer and a fourth electrode layer which are used for filling the grooves are sequentially formed in the grooves and on the surface of the semiconductor substrate, and a plurality of first openings which expose the second electrode layer are formed in the third electrode layer and the fourth electrode layer between adjacent grooves;
forming a second opening in the second electrode layer exposed by the first opening to expose the first electrode layer, and simultaneously forming a third opening in the fourth electrode layer to expose the third electrode layer;
forming a dielectric layer covering the first electrode layer, the second electrode layer, the third electrode layer and the fourth electrode layer on the semiconductor substrate;
and forming a contact structure which penetrates through the dielectric layer and is respectively and electrically connected with the first electrode layer, the second electrode layer, the third electrode layer and the fourth electrode layer in the dielectric layer.
2. The method of claim 1, wherein forming a plurality of first openings in the third electrode layer and the fourth electrode layer between adjacent trenches to expose the second electrode layer comprises:
providing a semiconductor substrate, wherein a plurality of grooves are formed in the semiconductor substrate, and a first electrode layer, a second electrode layer, a third electrode layer and a fourth electrode layer which are filled in the grooves are sequentially formed in the grooves and on the surface of the semiconductor substrate;
forming a patterned first photoresist layer on the surface of the fourth electrode layer, wherein the patterned first photoresist layer defines the position of the first opening;
etching the fourth electrode layer and the third electrode layer by using the patterned first photoresist layer as a mask to form the first opening;
and removing the patterned first photoresist layer.
3. The method according to claim 1, wherein a method of forming a second opening which exposes the first electrode layer in the second electrode layer which is exposed by the first opening, and simultaneously forming a third opening which exposes the third electrode layer in the fourth electrode layer comprises:
forming a second patterned photoresist layer on the surface of the second electrode layer exposed by the first opening and the surface of the fourth electrode layer, wherein the second patterned photoresist layer defines the positions of the second opening and the third opening;
simultaneously etching the second electrode layer exposed by the first opening and the fourth electrode layer by using the patterned second photoresist layer as a mask to form a second opening and a third opening;
and removing the patterned second photoresist layer.
4. The method of claim 3, wherein the patterned second photoresist layer comprises a fourth opening and a fifth opening, wherein the fourth opening defines a location of the second opening and the fifth opening defines a location of the third opening.
5. The method of claim 3, wherein the patterned second photoresist layer includes a sixth opening at a boundary of the first opening defining locations of the second and third openings.
6. The method for forming a capacitor according to claim 1, wherein a first insulating layer is further formed between the first electrode layer and the second electrode layer; a second insulating layer is further formed between the second electrode layer and the third electrode layer; a third insulating layer is further formed between the third electrode layer and the fourth electrode layer.
7. A method of forming a capacitor, comprising:
providing a semiconductor substrate, wherein a plurality of grooves are formed in the semiconductor substrate, a first electrode layer, a second electrode layer, a third electrode layer and a fourth electrode layer which are used for filling the grooves are sequentially formed in the grooves and on the surface of the semiconductor substrate, and a plurality of first openings which expose the third electrode layer are formed in the fourth electrode layer between adjacent grooves;
forming a second opening exposing the first electrode layer in the third electrode layer and the second electrode layer at the bottom of the first opening, and simultaneously forming a third opening exposing the second electrode layer in the fourth electrode layer and the third electrode layer;
forming a dielectric layer covering the first electrode layer, the second electrode layer, the third electrode layer and the fourth electrode layer on the semiconductor substrate;
and forming a contact structure which penetrates through the dielectric layer and is respectively and electrically connected with the first electrode layer, the second electrode layer, the third electrode layer and the fourth electrode layer in the dielectric layer.
8. The method of claim 7, wherein forming a plurality of first openings in the fourth electrode layer between adjacent trenches to expose the third electrode layer comprises:
providing a semiconductor substrate, wherein a plurality of grooves are formed in the semiconductor substrate, and a first electrode layer, a second electrode layer, a third electrode layer and a fourth electrode layer which are filled in the grooves are sequentially formed in the grooves and on the surface of the semiconductor substrate;
forming a patterned first photoresist layer on the surface of the fourth electrode layer, wherein the patterned first photoresist layer defines the position of the first opening;
etching the fourth electrode layer by using the patterned first photoresist layer as a mask to form the first opening;
and removing the patterned first photoresist layer.
9. The method according to claim 7, wherein a method of forming a second opening which exposes the first electrode layer in the third electrode layer and the second electrode layer at a bottom of the first opening, and simultaneously forming a third opening which exposes the second electrode layer in the fourth electrode layer and the third electrode layer comprises:
forming a patterned second photoresist layer on the surface of the third electrode layer exposed by the first opening and the surface of the fourth electrode layer, wherein the patterned second photoresist layer defines the positions of the second opening and the third opening;
simultaneously etching the third electrode layer and the second electrode layer at the bottom of the first opening and the fourth electrode layer and the third electrode layer by taking the patterned second photoresist layer as a mask to form a second opening and a third opening;
and removing the patterned second photoresist layer.
10. The method of claim 9, wherein the patterned second photoresist layer comprises a fourth opening and a fifth opening, wherein the fourth opening defines a location of the second opening and the fifth opening defines a location of the third opening.
11. The method of claim 9, wherein the patterned second photoresist layer includes a sixth opening at a boundary of the first opening defining locations of the second and third openings.
12. The method for forming a capacitor according to claim 7, wherein a first insulating layer is further formed between the first electrode layer and the second electrode layer; a second insulating layer is further formed between the second electrode layer and the third electrode layer; and a third insulating layer is formed between the third electrode layer and the fourth electrode layer.
CN202210916400.1A 2022-08-01 2022-08-01 Capacitor forming method Pending CN115241161A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202210916400.1A CN115241161A (en) 2022-08-01 2022-08-01 Capacitor forming method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210916400.1A CN115241161A (en) 2022-08-01 2022-08-01 Capacitor forming method

Publications (1)

Publication Number Publication Date
CN115241161A true CN115241161A (en) 2022-10-25

Family

ID=83677373

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202210916400.1A Pending CN115241161A (en) 2022-08-01 2022-08-01 Capacitor forming method

Country Status (1)

Country Link
CN (1) CN115241161A (en)

Similar Documents

Publication Publication Date Title
US7078780B2 (en) Schottky barrier diode and method of making the same
TWI392080B (en) Semiconductor structure including trench capacitor and trench resistor
US7943476B2 (en) Stack capacitor in semiconductor device and method for fabricating the same including one electrode with greater surface area
US6306720B1 (en) Method for forming capacitor of mixed-mode device
CN113192892B (en) Semiconductor structure and preparation method thereof
CN110957320B (en) Semiconductor structure, memory structure and preparation method thereof
JP2000208434A (en) Patterning method of semiconductor element and semiconductor device
KR100564626B1 (en) Metal-insulator-metal capacitors having high capacitance and method for manufacturing the same
US11915968B2 (en) Semiconductor structure and method for manufacturing same
CN113506776A (en) Method for manufacturing semiconductor structure
US7576013B2 (en) Method of relieving wafer stress
CN115241161A (en) Capacitor forming method
CN114883491A (en) Semiconductor structure and forming method thereof
US11538811B2 (en) Dynamic random access memory and method of manufacturing the same
CN113130449B (en) Method for forming semiconductor structure
JP7263644B2 (en) Semiconductor device manufacturing method
CN112864154B (en) Method for forming semiconductor structure
KR100644526B1 (en) Method of fabricating embossing-typed capacitor
CN209045554U (en) Semiconductor structure and memory construction
CN112909169A (en) Semiconductor structure and method for manufacturing semiconductor structure
CN117545275B (en) Method for manufacturing semiconductor structure
KR100712491B1 (en) Fabrication method for semiconductor device having multi-resistors and high capacitive capacitor
US20240258439A1 (en) Schottky diode and method of fabrication thereof
US20240234145A9 (en) Method of manufacturing memory device using self-aligned double patterning (sadp)
CN109346510B (en) Semiconductor device and method of forming the same

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination