CN113506776A - Method for manufacturing semiconductor structure - Google Patents
Method for manufacturing semiconductor structure Download PDFInfo
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- CN113506776A CN113506776A CN202110785220.XA CN202110785220A CN113506776A CN 113506776 A CN113506776 A CN 113506776A CN 202110785220 A CN202110785220 A CN 202110785220A CN 113506776 A CN113506776 A CN 113506776A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/485—Bit line contacts
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
Abstract
The invention relates to a manufacturing method of a semiconductor structure, which comprises the following steps: providing a substrate, wherein the substrate comprises a substrate and a mask layer, a shallow trench isolation structure is formed in the substrate, the substrate is isolated by the shallow trench isolation structure into a plurality of active regions which are arranged at intervals, the mask layer is positioned on the substrate and comprises at least one film layer, the substrate is provided with a bit line contact original hole, and the bit line contact original hole extends into the active regions from the surface of the mask layer; filling a sacrificial mask in the bit line contact original hole; removing at least one layer of mask layer based on the sacrificial mask, wherein the rest bit lines contact the original holes to form bit line contact holes; removing the sacrificial mask; and forming a bit line contact material layer which fills the bit line contact holes and is used for forming a bit line contact structure. The method and the device can effectively reduce gaps among the bit line contact structures.
Description
Technical Field
The present disclosure relates to integrated circuit technologies, and more particularly, to a method for fabricating a semiconductor structure.
Background
As the line width of semiconductors gradually decreases, the corresponding size of the bit line contact structure of the memory device for connecting the bit line with the active region also gradually decreases. This results in the formation of a gap in the bit line contact structure formed based on conventional processes, thereby resulting in a device that is susceptible to failure.
Currently, the problem is usually solved by adjusting the concentration of the formation material (e.g. polysilicon) of the bit line contact structure or by ion implantation. Although the method can improve the gap problem to a certain extent, the gap phenomenon still occurs in the formed bit line contact structure.
Disclosure of Invention
In view of the above, it is necessary to provide a method for fabricating a semiconductor structure to solve the problem of the bit line contact structure in the prior art that has a gap.
To achieve the above object, in one aspect, the present invention provides 1 a method for fabricating a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a substrate and a mask layer, a shallow trench isolation structure is formed in the substrate and isolates a plurality of active regions which are arranged at intervals from the substrate, the mask layer is positioned on the substrate and comprises at least one film layer, the substrate is provided with a bit line contact original hole, and the bit line contact original hole extends into the active regions from the surface of the mask layer;
filling a sacrificial mask in the bit line contact original hole;
removing at least one layer of the mask layer based on the sacrificial mask, wherein the rest bit lines contact the original holes to form bit line contact holes;
removing the sacrificial mask;
and forming a bit line contact material layer which fills the bit line contact holes and is used for forming a bit line contact structure.
In one embodiment, the method for forming the substrate includes:
providing the substrate;
forming a mask material layer on the substrate;
patterning the mask material layer to form the mask layer, wherein an opening is formed in the mask layer, and the position and the shape of the bit line contacting the original hole are defined by the opening;
and etching based on the mask layer to form the bit line contact original hole.
In one of the embodiments, the first and second electrodes are,
before forming the mask material layer on the substrate, the method further comprises:
forming an isolation material layer on the substrate;
the etching based on the mask layer to form the bit line contact original hole comprises the following steps:
etching the isolation material layer based on the mask layer, wherein the rest isolation material layer forms an isolation layer;
and etching based on the mask layer and the isolation layer to form the bit line contact original hole.
In one of the embodiments, the first and second electrodes are,
the forming of the bit line contact material layer comprises:
forming a bit line contact material layer in the surface of the isolation layer and the bit line contact hole;
after the forming of the bit line contact material layer, the method further comprises:
and removing the bit line contact material layer on the surface of the isolation layer, wherein the rest bit line contact material layer forms a bit line contact structure.
In one embodiment, before forming the isolation material layer on the substrate, the method further includes:
forming an insulating material layer on the substrate;
the etching based on the mask layer and the isolation layer to form the bit line contact original hole comprises the following steps:
etching the insulating material layer based on the mask layer and the isolation layer, wherein the rest insulating material layer forms an insulating medium layer;
and etching the substrate based on the mask layer, the isolation layer and the insulating medium layer to form the bit line contact original hole.
In one embodiment, the insulating dielectric layer includes a first oxide layer.
In one embodiment, the isolation layer comprises a silicon nitride layer.
In one embodiment, the filling of the sacrificial mask in the bit line contact original holes comprises:
forming a sacrificial material layer on the surface of the mask layer and in the bit line contact original hole;
and removing the sacrificial material layer on the surface of the mask layer, wherein the rest sacrificial material layer forms the sacrificial mask.
In one embodiment, the forming a sacrificial material layer in the mask layer surface and the bit line contact primitive hole includes:
and depositing the sacrificial material layer on the surface of the mask layer and in the bit line contact original hole by a fluid chemical vapor deposition method.
In one embodiment, the material of the sacrificial mask is spin-on carbon.
In one embodiment, the semiconductor structure has a device region and a peripheral circuit region, the bit line contact original holes are formed in the device region, the mask layer is simultaneously formed in the device region and the peripheral circuit region,
removing at least one of the mask layers based on the sacrificial mask comprises:
and removing the part of at least one layer of the mask layer positioned in the device area on the basis of the sacrificial mask, and simultaneously reserving the part of the mask layer positioned in the peripheral circuit area.
In one embodiment, the mask layer includes a conductive layer and a protective dielectric layer, and the protective dielectric layer is located on the surface of the conductive layer.
In one embodiment, the conductive layer comprises a polysilicon layer.
In one embodiment, the protective dielectric layer includes a second oxide layer.
In one embodiment, the removing, based on the sacrificial mask, a portion of the at least one mask layer in the device region includes:
removing the part of the protective dielectric layer positioned in the device region;
and removing the part of the conductive layer, which is positioned in the device area.
In one embodiment, the removing the sacrificial mask includes:
the sacrificial mask is removed by an ashing process.
In the method for manufacturing the semiconductor structure, a sacrificial mask is formed at first. And then removing at least one layer of the mask layer based on the sacrificial mask, so that partial hole space of the bit line contact original hole corresponding to the partial mask layer does not exist any more, and the depth of a bit line contact hole formed by the residual bit line contact original hole is lower than that of the in-situ bit line contact original hole. The depth of the original hole of the in-situ line contact is reduced, and the depth-to-width ratio of the original hole is reduced, so that gaps can be effectively prevented from being generated when the bit line contact material layer is filled. Therefore, the method and the device can effectively reduce the gap problem in the bit line contact structure.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments or the conventional technologies of the present application, the drawings used in the descriptions of the embodiments or the conventional technologies will be briefly introduced below, it is obvious that the drawings in the following descriptions are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a flow chart of a method of fabricating a semiconductor structure provided in one embodiment;
fig. 2-7 are schematic cross-sectional views of structures obtained during fabrication of a semiconductor structure provided in one embodiment.
Description of reference numerals:
description of reference numerals: 100-substrate, 110-substrate, 111-active region, 120-mask layer, 121-conducting layer, 122-protective dielectric layer, 130-shallow trench isolation structure, 140-isolation layer, 150-insulating dielectric layer, 200-sacrificial mask and 301-bit line contact material layer.
Detailed Description
To facilitate an understanding of the present application, the present application will now be described more fully with reference to the accompanying drawings. Embodiments of the present application are set forth in the accompanying drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and/or sections, these elements, components, regions, layers, doping types and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or section from another element, component, region, layer, doping type or section. Thus, a first element, component, region, layer, doping type or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatial relational terms, such as "under," "below," "under," "over," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations) and the spatial descriptors used herein interpreted accordingly.
As used herein, the singular forms "a", "an" and "the" may include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises/comprising," "includes" or "including," etc., specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. Also, in this specification, the term "and/or" includes any and all combinations of the associated listed items.
Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention, such that variations from the shapes shown are to be expected, for example, due to manufacturing techniques and/or tolerances. Thus, embodiments of the invention should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing techniques.
As mentioned in the background, the bit line contact structure formed by the current process is prone to crack. In view of the foregoing, the present application provides a method for fabricating a semiconductor structure.
In one embodiment, referring to fig. 1, a method for fabricating a semiconductor structure is provided, which includes the steps of:
step S100, providing a substrate 100, where the substrate 100 includes a substrate 110 and a mask layer 120, a shallow trench isolation structure 130 is formed in the substrate 110, the shallow trench isolation structure 130 isolates the substrate 110 into a plurality of active regions 111 arranged at intervals, the mask layer 120 is located on the substrate 110 and includes at least one film layer, the substrate 100 has a bit line contact original hole 10, and the bit line contact original hole 10 extends from the surface of the mask layer 120 into the active region 111, please refer to fig. 2;
step S200, filling the bit line contact original hole 10 with a sacrificial mask 200, please refer to fig. 3;
step S300, removing at least one mask layer 120 based on the sacrificial mask 200, and forming bit line contact holes 20 by the remaining bit lines contacting the original holes 10, as shown in fig. 5;
step S400, removing the sacrificial mask 200, please refer to fig. 6;
in step S500, a bit line contact material layer 301 is formed, and the bit line contact material layer 301 fills the bit line contact hole 20 and is used for forming a bit line contact structure, as shown in fig. 7.
In step S100, providing the substrate 100 may be providing a previously prepared substrate, or processing the substrate 100 through a corresponding preparation process.
The substrate 110 may be a semiconductor substrate such as a silicon substrate. The mask layer 120 is a patterned mask formed to make bit line contacts to the original holes 10. The mask layer 120 may be one or more film layers. In particular, it may comprise a silicon dioxide layer.
The bit line contact original hole 10 extends from the surface of the mask layer 120 into the active region 111. In conventional processes, polysilicon is typically deposited directly after the formation of the bit line contact original hole 10. The polysilicon typically covers the polysilicon of the bitline contact original hole 10 and the mask layer 120. And then etching the polysilicon to form a bit line contact structure.
In step S200, the sacrificial mask 200 is an intermediate process structure that is removed in the subsequent step S400, and may be spin-on carbon or the like.
In step S300, the mask layer 120 may include a plurality of layers or only one layer. In the multi-layer mask layer 120, the material of the mask layer 120 of each layer may be the same or different, and the present application is not limited thereto.
When the mask layer 120 includes one film layer, the film layer is removed. When the mask layer 120 includes a plurality of film layers, all the film layers may be removed, or only a portion of the mask layer 120 may be removed, which is not limited in the present application.
After removing at least one mask layer 120, the partial hole space of the bit line contact original hole 10 corresponding to the partial mask layer 120 no longer exists, so that the bit line contact hole 20 formed by the rest bit line contact original hole 10 has a depth lower than that of the original bit line contact original hole 10.
In the process of removing the mask layer 120, the sacrificial mask 200 can effectively protect the bit line from contacting the active region 111 around the hole wall of the original hole 10.
In step S400, the sacrificial mask 200 may be removed by an ashing process, as an example. Of course, other effective ways to remove it are possible and not limited in this application.
In step S500, the bit line contact material layer 301 may be a polysilicon layer, which is filled in the bit line contact hole 20, thereby providing a basis for forming a bit line contact structure.
Meanwhile, since the depth of the bit line contact hole 20 is smaller than the depth of the original bit line contact hole 10 extending from the surface of the mask layer 120 to the active region 111, when the bit line contact material layer 301 is filled in the bit line contact hole 20 with the smaller depth, the formation of a gap in the bit line contact material layer 301 can be effectively prevented.
When the mask layer 120 includes a plurality of layers, the greater the number of layers of the mask layer 120 to be removed, the smaller the depth of the bit line contact hole 20 to be formed, which is more advantageous for forming the bit line contact material layer 301 with good quality. Of course, if the process requirements allow or other process requirements, a combination of considerations may be taken into account to remove portions of masking layer 120.
In this embodiment, at least one mask layer is removed through the sacrificial mask 200, so as to reduce the depth of the bit line contact hole, thereby effectively preventing the bit line contact material layer 301 from generating a gap during filling. Therefore, the present embodiment can effectively reduce the gap problem in the bit line contact structure 200.
In one embodiment, a method of forming the substrate 100 includes:
step S110, providing a substrate 110;
step S120, forming a mask material layer on the substrate 110;
step S150, patterning the mask material layer to form a mask layer 120, wherein an opening is formed in the mask layer 120, and the opening defines the position and the shape of the bit line contacting the original hole 10;
in step S160, etching is performed based on the mask layer 120 to form the bit line contact original hole 10.
In step S110, providing the substrate 110 may be providing the substrate 110 in which a shallow trench isolation structure has been formed. Alternatively, an original substrate is provided, and then the original substrate is processed, so as to form the substrate 110 having the shallow trench isolation structure therein.
In step S120, a mask material layer such as a silicon dioxide layer may be formed on the substrate 110 by chemical vapor deposition (e.g., plasma chemical vapor deposition), physical vapor deposition (e.g., magnetron sputtering), and the like.
In step S150, after forming a mask material layer on the substrate 110, a photoresist may be coated on the mask material layer. The photoresist is then patterned using a photolithography process. Thereafter, the layer of masking material is etched based on the patterning, thereby forming a patterned masking layer 120.
In step S160, the active region 111 and the like below the mask layer 120 may be continuously etched based on the mask layer 120 by dry etching or the like, so as to form the bit line contact original hole 10.
It is noted that the bit line contact original hole 10 refers to a via hole extending from the surface of the mask layer 120 into the active region 111.
In one embodiment, before step S150, the method further includes:
in step S140, an isolation material layer is formed on the substrate 110.
On this basis, step S160 includes:
step S161, etching the isolation material layer based on the mask layer 120, and forming the isolation layer 140 by the remaining isolation material layer, please refer to fig. 1;
in step S162, etching is performed based on the mask layer 120 and the isolation layer 140 to form a bit line contact original hole 10.
Specifically, the isolation layer 140 may include a silicon nitride layer or the like.
At this time, the isolation layer 140 is formed between the mask layer 120 and the substrate 110, so that the substrate active region and the like under the isolation layer 140 can be effectively protected by the isolation layer 140 in the process of removing the mask layer 120 (especially, removing all the mask layer 120).
In this embodiment, further, step S500 may specifically include:
a bit line contact material layer 301 is formed on the surface of the isolation layer 140 and in the bit line contact hole 20.
After step S500, the method may further include:
the bit line contact material layer 301 on the surface of the isolation layer 140 is removed, and the remaining bit line contact material layer 301 constitutes a bit line contact structure.
At this time, all the mask layer 120 is removed in step S300, so that the bit line contact material layer 301 may be formed on the surface of the isolation layer 140 and in the bit line contact hole 20.
In addition, at this time, the isolation layer may also effectively protect the substrate active region and the like below the isolation layer 140, so as to facilitate formation of the bit line contact structure and formation of the bit line contact structure when the bit line contact material layer 301 is removed.
In one embodiment, before step S140, the method further includes:
in step S130, an insulating material layer is formed on the substrate 110.
Step S162 now includes:
step S1621, etching the insulating material layer based on the mask layer 120 and the isolation layer 140, and forming an insulating dielectric layer 150 from the remaining insulating material layer, as shown in fig. 1;
in step S1622, the substrate 110 is etched based on the mask layer 120, the isolation layer 140 and the insulating dielectric layer 150 to form a bit line contact original hole 10.
Specifically, the insulating dielectric layer 150 may include a first oxide layer, which may effectively isolate the mask layer 120 from the substrate 110, thereby effectively protecting the substrate 110 during the mask layer removal process. Meanwhile, the insulating dielectric layer 150 may also be used as a gate oxide layer in other regions.
For example, the semiconductor structure may have a device region and a peripheral circuit region. A bit line contact starting hole 10 is formed in the device region, thereby forming a conductive contact structure 300 in the device region. The peripheral circuit region is a region surrounding the device region. At this time, the insulating dielectric layer 150 may serve as a gate oxide layer in the peripheral circuit region.
In the present embodiment, an insulating dielectric layer 150, an isolation layer 140, and at least one layer 120 are sequentially formed on the substrate 110. That is, the insulating dielectric layer 150 and the isolation layer 140 are formed on the substrate 110 in addition to the at least one mask layer 120. The isolation layer 140 can effectively protect the insulating dielectric layer 150 and the substrate 110 thereunder. The insulating dielectric layer 150 can also effectively protect the substrate 110 thereunder, and at the same time, it can also be used as a gate oxide layer in a peripheral circuit region.
Of course, in some embodiments, only the at least one mask layer 120 may be formed on the substrate 110. Alternatively, at least one mask layer 120 and an isolation layer 140 may be formed on the substrate 110. Alternatively, at least one mask layer 120 and an insulating dielectric layer 150 may be formed on the substrate 110. The present application is not limited in this regard.
In one embodiment, step S200 includes:
step S210, forming a sacrificial material layer on the surface of the mask layer 120 and in the bit line contact original hole 10;
in step S220, the sacrificial material layer on the surface of the mask layer 120 is removed, and the remaining sacrificial material layer constitutes the sacrificial mask 200.
In step S210, the sacrificial material layer may or may not fill the bit line contact original hole 10, which is not limited in the present application.
Specifically, the filling height of the sacrificial material layer in the bit line contact original hole 10 can be set to be higher than the substrate surface, so that the sacrificial mask 200 formed thereby can effectively protect the substrate 110 during the process of removing the mask layer 120.
In step S220, the sacrificial material layer on the surface of the mask layer 120 outside the bit line contact original hole 10 may be removed by an etching process or the like.
In other embodiments, step S200 may be filled in other manners. For example, a patterned reticle may be provided first. Then, the openings of the patterned mask are aligned with the bit line contact original holes. And then directly depositing a sacrificial mask in the bit line contact original hole based on the patterned mask.
At this time, it is not necessary to form a sacrificial material layer on the surface of the mask layer 120, so that the step of removing the sacrificial material layer can be omitted, thereby reducing the number of processes and improving the process efficiency.
In one embodiment, step S210 includes:
a layer of sacrificial material is deposited by fluid chemical vapor deposition on the surface of the mask layer 120 and within the bit line contact original holes 10.
At this time, the material of the exemplary sacrificial mask 200 may be spin-on carbon.
The spin-on carbon or the like formed by the fluid chemical vapor deposition method can be conveniently removed by an ashing process or the like in a subsequent process.
In one embodiment, a semiconductor structure has a device region and a peripheral circuit region. A bit line contact primitive hole 10 is formed in the device region. The mask layer 120 is formed in both the device region and the peripheral circuit region.
Meanwhile, step S300 includes:
portions of the at least one mask layer 120 located in the device region are removed based on the sacrificial mask 200 while portions of the mask layer 120 located in the peripheral circuit region remain.
At this time, the remaining mask layer 120 in the peripheral circuit region may protect the peripheral circuit region when the sacrificial mask is removed. Moreover, the remaining mask layer 120 in the peripheral circuit region or a part of the film layer of the mask layer 120 may be used as a functional film layer in the peripheral circuit region.
Of course, in some embodiments, the portions of the at least one mask layer 120 in the peripheral circuit region may be removed simultaneously with the portions of the at least one mask layer 120 in the device region being removed based on the sacrificial mask 200.
At this time, if the mask layer 120 includes a plurality of film layers, the portion of the mask layer 120 in the peripheral circuit region may be removed, or all of the portions of the mask layer 120 in the peripheral circuit region may be removed.
When the portions of the partial layer mask layer 120 in the peripheral circuit region are all removed, the number of the mask layer 120 removed in the peripheral circuit region and the number of the mask layer 120 removed in the device region may be the same or different. The number of mask layers 120 removed in the peripheral circuit region may be greater than the number of mask layers 120 removed in the device region. Alternatively, the number of mask layers 120 removed in the peripheral circuit region may also be less than the number of mask layers 120 removed in the device region.
In one embodiment, further, the mask layer 120 may include a conductive layer 121 and a protective dielectric layer 122. The protective dielectric layer 122 is located on the surface of the conductive layer 121.
As an example, the conductive layer 121 may include a polysilicon layer, which may be a component of a gate structure of the peripheral circuit region.
As an example, the protective dielectric layer 122 may include a second oxide layer, which may effectively protect the polysilicon layer that is a component of the gate structure of the peripheral circuit region.
In other embodiments, the mask layer 120 may be disposed differently. For example, the mask layer 120 may include only the protective dielectric layer 122 without providing the conductive layer 121. Alternatively, the mask layer 120 may include other film layers besides the conductive layer 121 and the protective dielectric layer 122. The present application is not limited in this regard.
In one embodiment, step S300 includes:
step S310, removing the portion of the protective dielectric layer 122 in the device region, please refer to fig. 4;
in step S320, the portion of the conductive layer 121 in the device region is removed, please refer to fig. 5.
At this time, the protective dielectric layer 122 and the conductive layer 121 are completely removed, so that the bit line contact hole 20 with a smaller depth can be conveniently formed, and the aspect ratio of the bit line contact hole 20 is effectively reduced.
Of course, in some embodiments, only the protective dielectric layer 122 may be removed, and the conductive layer 121 may not be removed. At this time, the depth of the bit line contact hole 20 is also smaller than that of the bit line contact original hole 10 formed in the conventional method, so that a gap phenomenon in the bit line contact structure formed in the bit line contact hole 20 can be improved.
It should be understood that, although the steps in the flowchart of fig. 1 are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least a portion of the steps in fig. 1 may include multiple steps or multiple stages, which are not necessarily performed at the same time, but may be performed at different times, which are not necessarily performed in sequence, but may be performed in turn or alternately with other steps or at least a portion of the other steps or stages.
In the description herein, references to the description of the terms "some embodiments," "other embodiments," "desired embodiments," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, a schematic description of the above terminology may not necessarily refer to the same embodiment or example.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features of the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the claims. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (16)
1. A method for fabricating a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a substrate and a mask layer, a shallow trench isolation structure is formed in the substrate and isolates a plurality of active regions which are arranged at intervals from the substrate, the mask layer is positioned on the substrate and comprises at least one film layer, the substrate is provided with a bit line contact original hole, and the bit line contact original hole extends into the active regions from the surface of the mask layer;
filling a sacrificial mask in the bit line contact original hole;
removing at least one layer of the mask layer based on the sacrificial mask, wherein the rest bit lines contact the original holes to form bit line contact holes;
removing the sacrificial mask;
and forming a bit line contact material layer which fills the bit line contact holes and is used for forming a bit line contact structure.
2. The method of claim 1, wherein the substrate is formed by a method comprising:
providing the substrate;
forming a mask material layer on the substrate;
patterning the mask material layer to form the mask layer, wherein an opening is formed in the mask layer, and the position and the shape of the bit line contacting the original hole are defined by the opening;
and etching based on the mask layer to form the bit line contact original hole.
3. The method of claim 2, wherein the step of forming the semiconductor structure comprises,
before forming the mask material layer on the substrate, the method further comprises:
forming an isolation material layer on the substrate;
the etching based on the mask layer to form the bit line contact original hole comprises the following steps:
etching the isolation material layer based on the mask layer, wherein the rest isolation material layer forms an isolation layer;
and etching based on the mask layer and the isolation layer to form the bit line contact original hole.
4. The method of claim 3, wherein the step of forming the semiconductor structure comprises,
the forming of the bit line contact material layer comprises:
forming a bit line contact material layer in the surface of the isolation layer and the bit line contact hole;
after the forming of the bit line contact material layer, the method further comprises:
and removing the bit line contact material layer on the surface of the isolation layer, wherein the rest bit line contact material layer forms a bit line contact structure.
5. The method of claim 3, further comprising, prior to forming a layer of isolation material on the substrate:
forming an insulating material layer on the substrate;
the etching based on the mask layer and the isolation layer to form the bit line contact original hole comprises the following steps:
etching the insulating material layer based on the mask layer and the isolation layer, wherein the rest insulating material layer forms an insulating medium layer;
and etching the substrate based on the mask layer, the isolation layer and the insulating medium layer to form the bit line contact original hole.
6. The method of claim 5, wherein the insulating dielectric layer comprises a first oxide layer.
7. The method of claim 3, wherein said isolation layer comprises a silicon nitride layer.
8. The method of claim 1, wherein filling the bit line contact primitive hole with a sacrificial mask comprises:
forming a sacrificial material layer on the surface of the mask layer and in the bit line contact original hole;
and removing the sacrificial material layer on the surface of the mask layer, wherein the rest sacrificial material layer forms the sacrificial mask.
9. The method as claimed in claim 8, wherein forming a sacrificial material layer in the mask layer surface and the bit line contact primitive hole comprises:
and depositing the sacrificial material layer on the surface of the mask layer and in the bit line contact original hole by a fluid chemical vapor deposition method.
10. The method of claim 9, wherein the sacrificial mask is a spin-on carbon.
11. The method as claimed in claim 1, wherein the semiconductor structure has a device region and a peripheral circuit region, the bit line contact primitive hole is formed in the device region, the mask layer is formed in the device region and the peripheral circuit region simultaneously,
removing at least one of the mask layers based on the sacrificial mask comprises:
and removing the part of at least one layer of the mask layer positioned in the device area on the basis of the sacrificial mask, and simultaneously reserving the part of the mask layer positioned in the peripheral circuit area.
12. The method of claim 11, wherein the mask layer comprises a conductive layer and a protective dielectric layer, and the protective dielectric layer is located on a surface of the conductive layer.
13. The method of claim 12, wherein the conductive layer comprises a polysilicon layer.
14. The method of claim 12, wherein the protective dielectric layer comprises a second oxide layer.
15. The method of claim 12, wherein the removing the portion of the at least one mask layer in the device region based on the sacrificial mask comprises:
removing the part of the protective dielectric layer positioned in the device region;
and removing the part of the conductive layer, which is positioned in the device area.
16. The method of claim 1, wherein said removing said sacrificial mask comprises:
the sacrificial mask is removed by an ashing process.
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