CN114883491A - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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Publication number
CN114883491A
CN114883491A CN202210408183.5A CN202210408183A CN114883491A CN 114883491 A CN114883491 A CN 114883491A CN 202210408183 A CN202210408183 A CN 202210408183A CN 114883491 A CN114883491 A CN 114883491A
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insulating layer
electrode layer
layer
electrode
grooves
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辛春艳
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Fengfeixin Shanghai Technology Co ltd
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Fengfeixin Shanghai Technology Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes

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  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

The present application provides a semiconductor structure and a method of forming the same, the semiconductor structure comprising: a semiconductor substrate; the second grooves are positioned in the semiconductor substrate, the depths of the second grooves are the same, and the widths of the second grooves are different; filling structures are positioned in the plurality of second grooves, and the central layers of the filling structures in the second grooves with different widths are different electrode layers in the plurality of electrode layers respectively; the plurality of first grooves are communicated with the plurality of second grooves; and the capacitor is positioned in the first grooves and comprises a plurality of electrode layers and insulating layers for isolating adjacent electrode layers. According to the semiconductor structure and the forming method thereof, the process for manufacturing the contact structure and electrically connecting each electrode layer is simple and easy to realize, the manufactured contact structure is uniformly distributed in the whole capacitor device, and the connection resistance between the contact structure and the electrode layer is lower.

Description

Semiconductor structure and forming method thereof
Technical Field
The present application relates to the field of semiconductor technology, and more particularly, to a semiconductor structure and a method for forming the same.
Background
The capacitor is a passive element commonly used in a very large scale integrated circuit, and mainly includes Polysilicon-Insulator-Polysilicon (PIP), Metal-Insulator-Silicon (MIS), Metal-Insulator-Metal (MIM), and the like. The MIM capacitor has a minimum disturbance to the transistor and provides better Linearity and Symmetry, and thus is more widely used.
The MIM capacitor with the groove structure has higher capacity, low electric leakage and high reliability. To further increase capacity, multi-layer MIM structures are also typically stacked. The MIM capacitor generally includes a multi-layer MIM structure and a contact structure electrically communicating each metal layer.
However, the processes for fabricating contact structures and electrically connecting each metal layer in some processes are still complicated, and the performance of the fabricated contact structures still has defects. Therefore, there is a need to provide more efficient and reliable solutions.
Disclosure of Invention
The application provides a semiconductor structure and a forming method thereof, the process for manufacturing the contact structure and electrically communicating each electrode layer is simple and easy to realize, and the connection resistance between the manufactured contact structure and the electrode layer is lower.
One aspect of the present application provides a method of forming a semiconductor structure, comprising: providing a semiconductor substrate; forming a plurality of second grooves in the semiconductor substrate, wherein the depths of the plurality of second grooves are the same, and the widths of the plurality of second grooves are different; forming a plurality of first trenches communicated with the plurality of second trenches in the semiconductor substrate; and forming capacitors in the first grooves and simultaneously forming filling structures in the second grooves, wherein the capacitors comprise a plurality of electrode layers and insulating layers for isolating adjacent electrode layers, and the central layers of the filling structures in the second grooves with different widths are different electrode layers in the electrode layers respectively.
In some embodiments of the present application, the capacitor includes a first insulating layer, a first electrode layer, a second insulating layer, a second electrode layer, a third insulating layer, and a third electrode layer sequentially located at the bottom and the sidewall of the first trench; the filling structures in the second trenches with different widths are respectively a first filling structure, a second filling structure and a third filling structure.
In some embodiments of the present application, the first filling structure comprises: and the first insulating layer and the first electrode layer are sequentially positioned at the bottom and the side wall of the second groove and are filled in the second groove.
In some embodiments of the present application, the second filling structure comprises: the first insulating layer, the first electrode layer, the second insulating layer and the second electrode layer are sequentially located at the bottom and the side wall of the second groove, and the first insulating layer, the first electrode layer, the second insulating layer and the second electrode layer are filled in the second groove.
In some embodiments of the present application, the third filling structure comprises: the first insulating layer, the first electrode layer, the second insulating layer, the second electrode layer, the third insulating layer and the third electrode layer are sequentially located at the bottom and the side wall of the second groove, and the first insulating layer, the first electrode layer, the second insulating layer, the second electrode layer, the third insulating layer and the third electrode layer are filled in the second groove.
In some embodiments of the present application, a sum of 2 times a thickness of the first insulating layer and 1.2 times a thickness of the first electrode layer is ≦ a width of the first filling structure ≦ 2 times a sum of thicknesses of the first insulating layer and the first electrode layer; the sum of 2 times of the thicknesses of the first insulating layer, the first electrode layer and the second insulating layer and 1.2 times of the thickness of the second electrode layer is less than or equal to 2 times of the thickness of the first insulating layer, the first electrode layer, the second insulating layer and the second electrode layer, and the width of the second filling structure is less than or equal to 2 times of the thickness of the first insulating layer, the first electrode layer, the second insulating layer and the second electrode layer; the sum of 2 times of the thickness sum of the first insulating layer, the first electrode layer, the second insulating layer, the second electrode layer and the third insulating layer and 1.2 times of the thickness sum of the third electrode layer is less than or equal to 2 times of the thickness sum of the first insulating layer, the first electrode layer, the second insulating layer, the second electrode layer, the third insulating layer and the third electrode layer.
In some embodiments of the present application, a method of forming a capacitor in the number of first trenches and simultaneously forming a fill structure in the number of second trenches comprises: sequentially forming a first insulating layer and a first electrode layer in the plurality of first grooves and the plurality of second grooves and on the surface of the semiconductor substrate, wherein the first insulating layer and the first electrode layer are filled in the second grooves with the minimum width; sequentially forming a second insulating layer and a second electrode layer on the surface of the first electrode layer, wherein the first insulating layer, the first electrode layer, the second insulating layer and the second electrode layer fill a second groove with a second small width; sequentially forming a third insulating layer and a third electrode layer on the surface of the second electrode layer, wherein the first insulating layer, the first electrode layer, the second insulating layer, the second electrode layer, the third insulating layer and the third electrode layer are filled in a second groove with the largest width; and removing the first insulating layer, the first electrode layer, the second insulating layer, the second electrode layer, the third insulating layer and the third electrode layer which are higher than the surface of the semiconductor substrate, wherein the capacitor is formed in the first groove, the first filling structure is formed in the second groove with the smallest width, the second filling structure is formed in the second groove with the second smallest width, and the third filling structure is formed in the second groove with the largest width.
In some embodiments of the present application, the number of the second trenches is the same as the number of the electrode layers.
In some embodiments of the present application, the second trench has an aspect ratio of (0.5-30) to 1, and the first trench has an aspect ratio of (3-50) to 1.
In some embodiments of the present application, the method of forming a semiconductor structure further comprises: and forming an interlayer dielectric layer on the semiconductor substrate, and forming contact structures which penetrate through the interlayer dielectric layer and are electrically connected to the electrode layers in the center of the second groove respectively in the interlayer dielectric layer.
In some embodiments of the present application, a method of forming a capacitor in the number of first trenches and simultaneously forming a fill structure in the number of second trenches comprises: forming a capacitor structure in the first grooves and the second grooves and on the surface of the semiconductor substrate, wherein the capacitor structure comprises a plurality of electrode layers and insulating layers for isolating adjacent electrode layers; and removing the capacitance structure higher than the surface of the semiconductor substrate, wherein the capacitance structure left in the first groove forms the capacitor, and the capacitance structure left in the second groove forms the filling structure.
Another aspect of the present application also includes a semiconductor structure comprising: a semiconductor substrate; the second grooves are positioned in the semiconductor substrate, the depths of the second grooves are the same, and the widths of the second grooves are different; filling structures are positioned in the plurality of second grooves, and the central layers of the filling structures in the second grooves with different widths are different electrode layers in the plurality of electrode layers respectively; the plurality of first grooves are communicated with the plurality of second grooves; and the capacitor is positioned in the first grooves and comprises a plurality of electrode layers and insulating layers for isolating adjacent electrode layers.
In some embodiments of the present application, the capacitor includes a first insulating layer, a first electrode layer, a second insulating layer, a second electrode layer, a third insulating layer, and a third electrode layer sequentially located at the bottom and the sidewall of the first trench; the filling structures in the plurality of second grooves are respectively a first filling structure, a second filling structure and a third filling structure.
In some embodiments of the present application, the first filling structure comprises: and the first insulating layer and the first electrode layer are sequentially positioned at the bottom and the side wall of the second groove and are filled in the second groove.
In some embodiments of the present application, the second filling structure comprises: the first insulating layer, the first electrode layer, the second insulating layer and the second electrode layer are sequentially located at the bottom and the side wall of the second groove, and the first insulating layer, the first electrode layer, the second insulating layer and the second electrode layer are filled in the second groove.
In some embodiments of the present application, the third filling structure comprises: the first insulating layer, the first electrode layer, the second insulating layer, the second electrode layer, the third insulating layer and the third electrode layer are sequentially located at the bottom and the side wall of the second groove, and the first insulating layer, the first electrode layer, the second insulating layer, the second electrode layer, the third insulating layer and the third electrode layer are filled in the second groove.
In some embodiments of the present application, a sum of 2 times a thickness of the first insulating layer and 1.2 times a thickness of the first electrode layer is ≦ a width of the first filling structure ≦ 2 times a sum of thicknesses of the first insulating layer and the first electrode layer; the sum of 2 times of the thicknesses of the first insulating layer, the first electrode layer and the second insulating layer and 1.2 times of the thickness of the second electrode layer is less than or equal to 2 times of the thickness of the first insulating layer, the first electrode layer, the second insulating layer and the second electrode layer, and the width of the second filling structure is less than or equal to 2 times of the thickness of the first insulating layer, the first electrode layer, the second insulating layer and the second electrode layer; the sum of 2 times of the thickness sum of the first insulating layer, the first electrode layer, the second insulating layer, the second electrode layer and the third insulating layer and 1.2 times of the thickness sum of the third electrode layer is less than or equal to 2 times of the thickness sum of the first insulating layer, the first electrode layer, the second insulating layer, the second electrode layer, the third insulating layer and the third electrode layer.
In some embodiments of the present application, the number of the second trenches is the same as the number of the electrode layers.
In some embodiments of the present application, the second trench has an aspect ratio of (0.5-30) to 1, and the first trench has an aspect ratio of (3-50) to 1.
In some embodiments of the present application, the semiconductor structure further comprises: the semiconductor substrate comprises an interlayer dielectric layer positioned on the semiconductor substrate and contact structures which penetrate through the interlayer dielectric layer and are electrically connected to the electrode layers in the center of the second groove respectively.
The application provides a semiconductor structure and a forming method thereof, the process for manufacturing the contact structure and electrically communicating each electrode layer is simple and easy to realize, the manufactured contact structure is uniformly distributed in the whole capacitor device, and the connection resistance between the contact structure and the electrode layer is lower.
Drawings
The following drawings describe in detail exemplary embodiments disclosed in the present application. Wherein like reference numerals represent similar structures throughout the several views of the drawings. Those of ordinary skill in the art will understand that the present embodiments are non-limiting, exemplary embodiments and that the accompanying drawings are for illustrative and descriptive purposes only and are not intended to limit the scope of the present application, as other embodiments may equally fulfill the inventive intent of the present application. It should be understood that the drawings are not to scale. Wherein:
fig. 1 to 11 are schematic structural views of steps in a method for forming a semiconductor structure according to an embodiment of the present application
Fig. 12 is a schematic structural diagram of a semiconductor structure according to further embodiments of the present application.
Detailed Description
The following description is presented to enable any person skilled in the art to make and use the present disclosure, and is provided in the context of a particular application and its requirements. Various modifications to the disclosed embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present application. Thus, the present application is not limited to the embodiments shown, but is to be accorded the widest scope consistent with the claims.
The technical solution of the present invention will be described in detail below with reference to the embodiments and the accompanying drawings.
Fig. 1 to 11 are schematic structural views of steps in a method for forming a semiconductor structure according to an embodiment of the present disclosure. A method for forming a semiconductor structure according to an embodiment of the present application is described below with reference to the drawings.
Referring to fig. 1, a semiconductor substrate 100 is provided.
In some embodiments of the present application, the material of the semiconductor substrate 100 includes (i) elemental semiconductors such as silicon or germanium; (ii) a compound semiconductor such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, or the like; (iii) alloy semiconductors such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide, or gallium indium phosphide, or the like; or (iv) combinations of the foregoing. In addition, the semiconductor substrate 100 may be doped (e.g., a P-type substrate or an N-type substrate). In some embodiments of the present application, the semiconductor substrate 100 may be doped with a P-type dopant (e.g., boron, indium, aluminum, or gallium) or an N-type dopant (e.g., phosphorus or arsenic).
Referring to fig. 2 and 3, a plurality of second trenches 120 are uniformly formed in the semiconductor substrate 100, the plurality of second trenches 120 have the same depth, and the plurality of second trenches 120 have different widths. Fig. 2 is a top view of the semiconductor substrate, and fig. 3 is a cross-sectional view taken along a dotted line in fig. 2.
The number of second trenches 120 is used to form the filling structure. The fill structure is used to subsequently electrically connect the capacitor and the contact structure. Since the contact structures need to be electrically connected to different electrode layers in the capacitor, respectively, different filling structures are needed to electrically connect different electrode layers and contact structures, respectively. Specifically, each different electrode layer corresponds to a different filling structure, so the kind of filling structure and the number of electrode layers are the same. Different kinds of filling structures are formed in the second trenches with different widths, so that the different width kinds of the second trenches are the same as the number of the electrode layers. For example, if there are two electrode layers, the second trench has two widths; if three electrode layers are provided, the second groove has three widths; if there are four electrode layers, the second trench has four widths, and so on.
In the present embodiment, only three electrode layers are taken as an example, and thus the second trenches 120 have three widths. Referring to fig. 2 and 3, the second trench 120 with the smallest width is the first second trench 121; the second trench 120 with the second smallest width is a second trench 122; the second trench 120 having the largest width is a third second trench 123. Of course, in other embodiments of the present application, the number of the plurality of second grooves 120 may also be four, five or more.
Since the plurality of second trenches 120 are respectively used for forming the filling structures, the size of the plurality of second trenches 120 matches the size of the corresponding filling structures. For example, the size of the first and second trenches 121 matches the size of the first filling structure; the size of the second trench 122 matches the size of the second fill structure; the dimensions of the third second trenches 123 match the dimensions of the third fill structures. How to define the dimensions of the second trench 120 and the dimensions of the different fill structures is further described below.
In some embodiments of the present application, the plurality of second trenches 120 are formed simultaneously, and thus the depths of the plurality of second trenches 110 are all the same. The plurality of second trenches 120 are formed simultaneously, so that the process is simplified, the efficiency is improved, and the time is saved.
In some embodiments of the present application, although the width of the second trench 120 needs to be the same as the number of the electrode layers, the number of the second trench 120 may be any, as long as at least three different widths are satisfied. Of course, the number of second trenches 120 of different widths is preferably the same. That is, the number of the second grooves 120 may be, for example, 3, 6, 9, 12, etc.
In the technical solution of the present application, the plurality of second grooves 120 are uniformly distributed. Therefore, the distance between each second groove 120 and the adjacent first groove 110 is the same. Further, since the first trench 110 is used to form a capacitor and the second trench 120 is used to form a filling structure and electrically connect contact structures, each contact structure is at the same distance from an adjacent capacitor. The distribution mode can minimize the connection resistance between the contact structure and the electrode layer, improve the upper limit of the capacitance of the capacitor and further improve the performance of the device. And, because the contact structure is evenly distributed among a plurality of capacitors, the capacitance difference among the plurality of capacitors can be minimized, and the reliability of the device is improved.
In some embodiments of the present application, the method for forming the plurality of second trenches 120 includes wet etching, plasma dry etching, or the like. Specifically, for example, it includes: forming a patterned photoresist layer on the surface of the semiconductor substrate 100, wherein the patterned photoresist layer defines the position of the second trench 120; etching the semiconductor substrate 100 with the patterned photoresist layer as a mask to form the second trench 120; and removing the patterned photoresist layer.
In some embodiments of the present application, the second trench 120 has an aspect ratio of (0.5-30) to 1, such as 1: 1.5, 1: 2, 1: 3, etc.
In some embodiments of the present application, the depth of the number of second trenches 120 is less than the depth of the number of first trenches 110. In one aspect, the second trench 120 is used to form a fill structure that electrically connects contact structures, and thus is not too deep to waste process and material; on the other hand, the central layer of the filling structure in the second trench 120 needs to be one of a plurality of electrode layers, and therefore the depth of the second trench 120 is smaller than the depth of the first trench 110, otherwise it cannot be guaranteed that the second trench can be filled, and the central layer of the second trench is a void. In addition, since the depth of the second trenches 120 is smaller than the depth of the first trenches 110, the second trenches 120 need to be formed first, and then the first trenches 110 need to be formed, otherwise if the first trenches 110 with deeper depth are formed first, more photoresist is needed to fill the first trenches 110, material is wasted, and process requirements are higher.
Referring to fig. 4 and 5, a plurality of first trenches 110 communicating with the plurality of second trenches 120 are formed in the semiconductor substrate 100. Fig. 4 is a top view of the semiconductor substrate, and fig. 5 is a cross-sectional view taken along a dotted line in fig. 4.
The number of first trenches 110 is used to form a capacitor. In order to increase the total capacitance of a semiconductor capacitor device, a plurality of capacitors are typically formed in a semiconductor substrate. In the present embodiment, the number of the capacitors is only two as an example, and thus the number of the first trenches 110 is two. It will be understood by those skilled in the art that this is not a limitation of the present application, and in other embodiments of the present application, the number of the first trenches 110 and the capacitors may be three, four or more.
In some embodiments of the present application, a method of forming the plurality of first trenches 110 includes wet etching, plasma dry etching, or the like. Specifically, for example, it includes: forming a patterned photoresist layer on the surface of the semiconductor substrate 100, wherein the patterned photoresist layer defines the position of the first trench 110; etching the semiconductor substrate 100 with the patterned photoresist layer as a mask to form the first trench 110; and removing the patterned photoresist layer.
In some embodiments of the present application, the first trench has an aspect ratio of (3-50): 1, such as 10: 1, 15: 1, 20: 1, 25: 1, 30: 1, or 35: 1, etc. The first trench 110 is used to form a capacitor, and the high aspect ratio can increase the capacitance of the capacitor, but the high aspect ratio has high requirements for the etching process. In an actual process, an appropriate aspect ratio can be selected according to needs. It is to be noted that, in the embodiments of the present application, unless otherwise specified, the depth refers to a dimension in a vertical direction in a longitudinal sectional view, and the width refers to a dimension in a horizontal direction in a longitudinal sectional view.
In some embodiments of the present application, the plurality of first trenches 110 are formed simultaneously, and thus the plurality of first trenches 110 are all the same size. The plurality of first trenches 110 are formed simultaneously, so that the process is simplified, the efficiency is improved, and the time is saved.
Referring to fig. 6 to 9, a capacitor 140 is formed in the first trenches 110 and a filling structure 150 is simultaneously formed in the second trenches 120, the capacitor includes a plurality of electrode layers and insulating layers for isolating adjacent electrode layers, and center layers of the filling structures in the second trenches with different widths are different electrode layers in the plurality of electrode layers.
In some embodiments of the present application, a method of forming a capacitor in the number of first trenches and simultaneously forming a fill structure in the number of second trenches comprises: forming a capacitor structure in the first grooves and the second grooves and on the surface of the semiconductor substrate, wherein the capacitor structure comprises a plurality of electrode layers and insulating layers for isolating adjacent electrode layers; and removing the capacitance structure higher than the surface of the semiconductor substrate, wherein the capacitance structure left in the first groove forms the capacitor, and the capacitance structure left in the second groove forms the filling structure.
In some embodiments of the present application, the thickness ratio of the electrode layer and the insulating layer is (15-30): 1, such as 15: 1, 20: 1, or 30: 1. The insulating layer is used for isolating adjacent electrode layers, so that the smaller the thickness of the insulating layer is, the larger the capacitance value is while achieving the isolation purpose.
The process of forming the capacitor and fill structure is described in detail below using a specific embodiment as an example.
In a specific embodiment, the number of the electrode layers is three, and the capacitor comprises a first insulating layer, a first electrode layer, a second insulating layer, a second electrode layer, a third insulating layer and a third electrode layer which are sequentially arranged at the bottom and the side wall of the first trench; the filling structures in the second trenches with different widths are respectively a first filling structure, a second filling structure and a third filling structure. The first filling structure includes: and the first insulating layer and the first electrode layer are sequentially positioned at the bottom and the side wall of the second groove and are filled in the second groove. The second filling structure includes: and the first insulating layer, the first electrode layer, the second insulating layer and the second electrode layer are sequentially positioned at the bottom of the second groove and on the side wall, and the first insulating layer, the first electrode layer, the second insulating layer and the second electrode layer are filled in the second groove. The third filling structure includes: the first insulating layer, the first electrode layer, the second insulating layer, the second electrode layer, the third insulating layer and the third electrode layer are sequentially located at the bottom and the side wall of the second groove, and the first insulating layer, the first electrode layer, the second insulating layer, the second electrode layer, the third insulating layer and the third electrode layer are filled in the second groove.
Referring to fig. 6, a first insulating layer 141 and a first electrode layer 142 are sequentially formed in the plurality of first trenches 110 and the plurality of second trenches 120 and on the surface of the semiconductor substrate 100, and the first insulating layer 141 and the first electrode layer 142 fill the second trench with the smallest width, that is, the first second trench 121. The first and second trenches 121 have the smallest width and are thus filled first.
In some embodiments of the present application, a sum of 2 times a thickness of the first insulating layer 141 and 1.2 times a thickness of the first electrode layer 142 is ≦ a width of the first second trench 121 ≦ 2 times a sum of thicknesses of the first insulating layer 141 and the first electrode layer 142. With such a size setting, the first and second trenches 121 can accommodate 2 layers of the first insulating layer 141 and at least 1.5 layers of the first electrode layer 142, and are filled with 2 layers of the first insulating layer 141 and the first electrode layer 142. The first electrode layer 142 is disposed at the center of the first and second trenches 121, and the 2 first electrode layers 142 at the center of the first and second trenches 121 are combined in a U shape, so that the width of the first electrode layer 142 at the center of the first and second trenches 121 is greater than the thickness of one first electrode layer 142, and the contact area between the subsequent contact structure and the portion of the first electrode layer 142 can be larger.
In some embodiments of the present application, the material of the first electrode layer 142 includes metal or polysilicon or a metal compound or amorphous silicon. The metal is, for example, aluminum or titanium, and the metal compound is, for example, titanium oxide or the like. The method for forming the first electrode layer 142 includes a chemical vapor deposition process or a physical vapor deposition process.
In some embodiments of the present application, the material of the first insulating layer 141 includes silicon oxide, silicon nitride, aluminum oxide, or hafnium oxide. A method of forming the first insulating layer 141 includes a chemical vapor deposition process or a physical vapor deposition process.
Referring to fig. 7, a second insulating layer 143 and a second electrode layer 144 are sequentially formed on the surface of the first electrode layer 142, and the first insulating layer 141, the first electrode layer 142, the second insulating layer 143, and the second electrode layer 144 fill a second trench having a second smallest width, that is, the second trench 122. The width of the second trench 122 is the second smallest, so the second is filled.
In some embodiments of the present application, a sum of 2 times a sum of thicknesses of the first insulating layer 141, the first electrode layer 142, and the second insulating layer 143 and a sum of 1.2 times a thickness of the second electrode layer 144 is not less than 2 times a sum of thicknesses of the first insulating layer 141, the first electrode layer 142, the second insulating layer 143, and the second electrode layer 144. With such a size setting, the second trench 122 can accommodate 2 layers of the first insulating layer 141, the first electrode layer 142, the second insulating layer 143, and at least 1.5 layers of the second electrode layer 144, and is filled with 2 layers of the first insulating layer 141, the first electrode layer 142, the second insulating layer 143, and the second electrode layer 144. The second electrode layer 144 is disposed at the center of the second trench 122, and the 2 second electrode layers 144 at the center of the second trench 122 are combined in a U shape, so that the width of the second electrode layer 144 at the center of the second trench 122 is greater than the thickness of one second electrode layer 144, and the contact area between the subsequent contact structure and the second electrode layer 144 can be larger.
In some embodiments of the present application, the material of the second electrode layer 144 includes metal or polysilicon or a metal compound or amorphous silicon. The metal is, for example, aluminum or titanium, and the metal compound is, for example, titanium oxide or the like. The method for forming the second electrode layer 144 includes a chemical vapor deposition process or a physical vapor deposition process.
In some embodiments of the present application, the material of the second insulating layer 143 includes silicon oxide, silicon nitride, aluminum oxide, or hafnium oxide. The method for forming the second insulating layer 143 includes a chemical vapor deposition process or a physical vapor deposition process.
Referring to fig. 8, a third insulating layer 145 and a third electrode layer 146 are sequentially formed on the surface of the second electrode layer 144, and the first insulating layer 141, the first electrode layer 142, the second insulating layer 143, the second electrode layer 144, the third insulating layer 145 and the third electrode layer 146 fill the second trench with the largest width, that is, the third second trench 123. The third second trenches 123 have the largest width and are thus filled up finally. In some embodiments of the present application, the first trench 110 is also filled.
In some embodiments of the present application, a sum of 2 times a sum of thicknesses of the first insulating layer 141, the first electrode layer 142, the second insulating layer 143, the second electrode layer 144, and the third insulating layer 145 and 1.2 times a sum of thicknesses of the third electrode layer 146 is equal to or less than 2 times a sum of thicknesses of the first insulating layer 141, the first electrode layer 142, the second insulating layer 143, the second electrode layer 144, the third insulating layer 145, and the third electrode layer 146. With such a size setting, the third second trench 123 can accommodate 2 layers of the first insulating layer 141, the first electrode layer 142, the second insulating layer 143, the second electrode layer 144, the third insulating layer 145, and at least 1.5 layers of the third electrode layer 146, and is filled with 2 layers of the first insulating layer 141, the first electrode layer 142, the second insulating layer 143, the second electrode layer 144, the third insulating layer 145, and the third electrode layer 146. The third electrode layer 146 is disposed at the center of the third second trench 123, and the 2 third electrode layers 146 at the center of the third second trench 123 are combined in a U shape, so that the width of the third electrode layer 146 at the center of the third second trench 123 is greater than the thickness of one third electrode layer 146, and the contact area between the subsequent contact structure and the portion of the third electrode layer 146 can be larger.
In some embodiments of the present application, the material of the third electrode layer 146 includes metal or polysilicon or a metal compound or amorphous silicon. The metal is, for example, aluminum or titanium, and the metal compound is, for example, titanium oxide or the like. The method for forming the third electrode layer 146 includes a chemical vapor deposition process or a physical vapor deposition process.
In some embodiments of the present application, the material of the third insulating layer 145 includes silicon oxide, silicon nitride, aluminum oxide, or hafnium oxide. The method for forming the third insulating layer 145 includes a chemical vapor deposition process or a physical vapor deposition process.
While three electrode layers are exemplified above, it will be understood by those skilled in the art that the number of the plurality of electrode layers may be four, five or more. The larger the number of stacked electrode layers, the larger the capacitance of the capacitor, but the process of depositing multiple material layers is limited by the semiconductor deposition process and the semiconductor size, and in the actual process, the appropriate number of stacked layers can be selected according to the needs.
Referring to fig. 9, the first insulating layer 141, the first electrode layer 142, the second insulating layer 143, the second electrode layer 144, the third insulating layer 145 and the third electrode layer 146 above the surface of the semiconductor substrate 100 are removed, the capacitor 140 is formed in the first trench 110, the first filling structure 151 is formed in the second trench with the smallest width (i.e., the first and second trenches 121), the second filling structure 152 is formed in the second trench with the second smallest width (i.e., the second and second trenches 122), and the third filling structure 153 is formed in the second trench with the largest width (i.e., the third and second trenches 123).
In some embodiments of the present application, the method of removing the first insulating layer 141, the first electrode layer 142, the second insulating layer 143, the second electrode layer 144, the third insulating layer 145 and the third electrode layer 146 above the surface of the semiconductor substrate 100 includes a chemical mechanical polishing process.
In some embodiments of the present application, a sum of 2 times a thickness of the first insulating layer 141 and 1.2 times a thickness of the first electrode layer 142 is ≦ a width of the first filling structure 151 ≦ 2 times a sum of thicknesses of the first insulating layer 141 and the first electrode layer 142; the sum of 2 times the thickness of the first insulating layer 141, the first electrode layer 142, and the second insulating layer 143 and 1.2 times the thickness of the second electrode layer 144 is less than or equal to 2 times the width of the second filling structure 152; the sum of 2 times the thickness of the first insulating layer 141, the first electrode layer 142, the second insulating layer 143, the second electrode layer 144, and the third insulating layer 145 and 1.2 times the thickness of the third electrode layer 146 is not less than 2 times the width of the third filling structure 153 is not less than the sum of the thickness of the first insulating layer 141, the first electrode layer 142, the second insulating layer 143, the second electrode layer 144, the third insulating layer 145, and the third electrode layer 146.
In the semiconductor capacitor structure, different electrode layers need to be connected to different contact structures, respectively, and therefore the central layer of the filling structure 150 is each of the plurality of electrode layers. For example, the central layer of the first filling structure 151 is the first electrode layer 142; the central layer of the second filling structure 152 is the second electrode layer 144; the central layer of the third filling structure 153 is the third electrode layer 146.
Referring to fig. 10, an interlayer dielectric layer 160 is formed on the semiconductor substrate 100 to completely cover the semiconductor substrate 100.
In some embodiments of the present application, the method of forming the interlayer dielectric layer 160 includes a chemical vapor deposition process or a physical vapor deposition process. The material of the interlayer dielectric layer 160 includes silicon oxide.
Referring to fig. 11, contact structures 170 penetrating the interlayer dielectric layer 160 and electrically connected to the electrode layers at the center of the second trench, respectively, are formed in the interlayer dielectric layer 160.
In some embodiments of the present application, the number of the contact structures 170 is the same as the number of the electrode layers. In some embodiments of the present application, the number of the contact structures 170 is three, and the three contact structures 170 are electrically connected to the first electrode layer 142, the second electrode layer 144 and the third electrode layer 146, respectively.
Fig. 12 is a schematic structural diagram of a semiconductor structure according to yet another embodiment of the present application. It should be noted that, for the sake of simplicity, only the structure of the semiconductor substrate 100 and the first trench 110 and the second trench 120 is shown in fig. 12, and the filling structure and the capacitor formed in the first trench 110 and the second trench 120 are omitted.
Comparing the schematic structures of fig. 4 and 12, in other embodiments, a portion of the second trench 120 between the first trenches 110 has a wider width. The increased width locations are used for subsequent fabrication of contact structures. Therefore, the width of the part of the second groove is increased, so that the contact structure with larger width can be prevented from being well electrically connected with the electrode layer in the capacitor.
In the technical scheme of the application, on one hand, compared with the process of manufacturing the capacitor and connecting the contact structure of the capacitor in the conventional process, the process flow of the application is simple, the first groove and the second groove are synchronously formed, the subsequent electrode layer and the insulating layer are deposited in the first groove and the second groove simultaneously, the total process flow is only etching process manufacturing grooves, depositing process forming electrode layers and insulating layers, grinding process removing materials on the surface of the semiconductor substrate, manufacturing interlayer dielectric layers and contact structures, and compared with the conventional process in which repeated etching, repeated deposition and repeated grinding are carried out for multiple times, the process flow is simplified greatly, the efficiency can be improved, and the cost can be saved; on the other hand, the contact structures 170 are uniformly distributed between any adjacent capacitors 140, and therefore, the distance from each contact structure 170 to the adjacent capacitor 140 is the same, and this distribution can minimize the connection resistance between the contact structure 170 and the capacitor 140, improve the upper limit of the capacitance of the capacitor, and further improve the device performance. And, because the contact structure is evenly distributed among a plurality of capacitors, the capacitance difference among the plurality of capacitors can be minimized, and the reliability of the device is improved.
According to the forming method of the semiconductor structure, the process for manufacturing the contact structure and electrically communicating each electrode layer is simple and easy to realize, the manufactured contact structure is uniformly distributed in the whole capacitor device, and the connection resistance between the contact structure and the electrode layer is lower.
Embodiments of the present application also provide a semiconductor structure, shown with reference to fig. 11, comprising: a semiconductor substrate 100; a plurality of second trenches 120 located in the semiconductor substrate 100, the plurality of second trenches 120 having the same depth and the plurality of second trenches 120 having different widths; the filling structures 150 are located in the plurality of second trenches 120, and the central layers of the filling structures 150 in the second trenches 120 with different widths are different electrode layers in the plurality of electrode layers respectively; a plurality of first grooves 110 communicating with the plurality of second grooves 120; and a capacitor 140 in the first trench 110, wherein the capacitor 140 includes a plurality of electrode layers and insulating layers for isolating adjacent electrode layers.
A semiconductor structure according to an embodiment of the present application will be described in detail below with reference to the accompanying drawings.
Referring to fig. 11, in some embodiments of the present application, the material of the semiconductor substrate 100 includes (i) an elemental semiconductor, such as silicon or germanium; (ii) a compound semiconductor such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, or the like; (iii) alloy semiconductors such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide, or gallium indium phosphide, or the like; or (iv) combinations of the foregoing. In addition, the semiconductor substrate 100 may be doped (e.g., a P-type substrate or an N-type substrate). In some embodiments of the present application, the semiconductor substrate 100 may be doped with a P-type dopant (e.g., boron, indium, tungsten, or gallium) or an N-type dopant (e.g., phosphorus or arsenic).
Referring to fig. 2 and 3, a plurality of second trenches 120 are uniformly distributed in the semiconductor substrate 100, the plurality of second trenches 120 have the same depth, and the plurality of second trenches 120 have different widths. Fig. 2 is a top view of the semiconductor substrate, and fig. 3 is a cross-sectional view taken along a dotted line in fig. 2.
The second trenches 120 are used to form the filling structure 150. The fill structure 150 is used to subsequently electrically connect the capacitor 140 and the contact structure 170. Since the contact structures 170 need to be electrically connected to different electrode layers in the capacitor, respectively, different filling structures are needed to electrically connect different electrode layers and contact structures, respectively. Specifically, each different electrode layer corresponds to a different filling structure, so the type of filling structure and the number of electrode layers are the same. Different kinds of filling structures are formed in the second trenches with different widths, so that the different width kinds of the second trenches are the same as the number of the electrode layers. For example, if there are two electrode layers, the second trench has two widths; if three electrode layers are provided, the second groove has three widths; if there are four electrode layers, the second trench has four widths, and so on.
In the present embodiment, only three electrode layers are taken as an example, and thus the second trenches 120 have three widths. Referring to fig. 2 and 3, the second trench 120 with the smallest width is the first second trench 121; the second trench 120 with the second smallest width is a second trench 122; the second trench 120 having the largest width is a third second trench 123. Of course, in other embodiments of the present application, the number of the plurality of second grooves 120 may also be four, five or more.
Since the plurality of second trenches 120 are respectively used for forming the filling structures, the size of the plurality of second trenches 120 matches the size of the corresponding filling structures. For example, the size of the first and second trenches 121 matches the size of the first filling structure 151; the size of the second trenches 122 matches the size of the second fill structures 152; the size of the third second trenches 123 matches the size of the third fill structures 153. How to define the dimensions of the second trench 120 and the dimensions of the different fill structures is further described below.
In some embodiments of the present application, the depths of the plurality of second trenches 120 are all the same.
In some embodiments of the present application, although the width of the second trench 120 is required to be the same as the number of the electrode layers, the number of the second trench 120 may be any, as long as at least three different widths are satisfied. Of course, the number of second trenches 120 of different widths is preferably the same. That is, the number of the second grooves 120 may be, for example, 3, 6, 9, 12, etc.
In the technical solution of the present application, the plurality of second grooves 120 are uniformly distributed. Therefore, the distance between each second groove 120 and the adjacent first groove 110 is the same. Further, since the first trench 110 is used to form a capacitor and the second trench 120 is used to form a filling structure and electrically connect contact structures, each contact structure is at the same distance from an adjacent capacitor. The distribution mode can minimize the connection resistance between the contact structure and the electrode layer, improve the upper limit of the capacitance of the capacitor and further improve the performance of the device. And, because the contact structure is evenly distributed among a plurality of capacitors, the capacitance difference among the plurality of capacitors can be minimized, and the reliability of the device is improved.
In some embodiments of the present application, the second trench 120 has an aspect ratio of (0.5-30) to 1, such as 1: 1.5, 1: 2, 1: 3, etc.
In some embodiments of the present application, the depth of the number of second trenches 120 is less than the depth of the number of first trenches 110. In one aspect, the second trench 120 is used to form a fill structure that electrically connects contact structures, and thus is not too deep to waste process and material; on the other hand, the central layer of the filling structure in the second trench 120 needs to be one of a plurality of electrode layers, and therefore the depth of the second trench 120 is smaller than the depth of the first trench 110, otherwise it cannot be ensured that the second trench can be filled, which may result in a void in the central layer of the second trench.
Referring to fig. 4 and 5, a plurality of first trenches 110 communicating with the plurality of second trenches 120 are formed in the semiconductor substrate 100. Fig. 4 is a top view of the semiconductor substrate, and fig. 5 is a cross-sectional view taken along a dotted line in fig. 4.
The number of first trenches 110 is used to form a capacitor 140. In order to increase the total capacitance of a semiconductor capacitor device, a plurality of capacitors are typically formed in a semiconductor substrate. In the present embodiment, the number of the capacitors is only two as an example, and thus the number of the first trenches 110 is two. It will be understood by those skilled in the art that this is not a limitation of the present application, and in other embodiments of the present application, the number of the first trenches 110 and the capacitors may be three, four or more.
In some embodiments of the present application, the first trench has an aspect ratio of (3-50): 1, such as 10: 1, 15: 1, 20: 1, 25: 1, 30: 1, or 35: 1, etc. The first trench 110 is used to form a capacitor, and the high aspect ratio can increase the capacitance of the capacitor, but the high aspect ratio has high requirements for the etching process. In an actual process, an appropriate aspect ratio can be selected according to needs. It should be noted that, in the embodiments of the present application, unless otherwise specified, the depth refers to a dimension in a vertical direction in a longitudinal sectional view, and the width refers to a dimension in a horizontal direction in the longitudinal sectional view.
In some embodiments of the present application, the plurality of first grooves 110 are all the same size.
With continued reference to fig. 11, a capacitor 140 is formed in the first trenches 110, a filling structure 150 is formed in the second trenches 120, the capacitor 140 includes a plurality of electrode layers and an insulating layer for isolating adjacent electrode layers, and the center layers of the filling structures in the second trenches with different widths are different electrode layers in the plurality of electrode layers, respectively.
In some embodiments of the present application, the thickness ratio of the electrode layer and the insulating layer is (15-30): 1, such as 15: 1, 20: 1, or 30: 1. The insulating layer is used for isolating adjacent electrode layers, so that the smaller the thickness of the insulating layer is, the larger the capacitance value is while achieving the isolation purpose.
The detailed structure of the capacitor and the fill structure is described in detail below using a specific embodiment as an example.
In a specific embodiment, the number of the electrode layers is three, and the capacitor 140 includes a first insulating layer 141, a first electrode layer 142, a second insulating layer 143, a second electrode layer 144, a third insulating layer 145, and a third electrode layer 146, which are sequentially located at the bottom and the sidewall of the first trench 110; the filling structures in the second trenches with different widths are the first filling structure 151, the second filling structure 152 and the third filling structure 153, respectively. Wherein the first filling structure 151 includes: and the first insulating layer 141 and the first electrode layer 142 are sequentially positioned at the bottom and the side wall of the second trench, and the second trench is filled with the first insulating layer 141 and the first electrode layer 142. The second filling structure 152 includes a first insulating layer 141, a first electrode layer 142, a second insulating layer 143, and a second electrode layer 144, which are sequentially located at the bottom and the sidewall of the second trench, and the first insulating layer 141, the first electrode layer 142, the second insulating layer 143, and the second electrode layer 144 fill the second trench. The third filling structure 153 includes: the first insulating layer 141, the first electrode layer 142, the second insulating layer 143, the second electrode layer 144, the third insulating layer 145 and the third electrode layer 146 are sequentially located at the bottom and the side wall of the second trench, and the first insulating layer 141, the first electrode layer 142, the second insulating layer 143, the second electrode layer 144, the third insulating layer 145 and the third electrode layer 146 fill the second trench.
In some embodiments of the present application, a sum of 2 times a thickness of the first insulating layer 141 and 1.2 times a thickness of the first electrode layer 142 is ≦ a width of the first filling structure 151 ≦ 2 times a sum of thicknesses of the first insulating layer 141 and the first electrode layer 142. Under such a size setting, the central layer of the first filling structure 151 is the first electrode layer 142, and the 2 first electrode layers 142 of the central layer of the first filling structure 151 are combined in a U shape, so that the width of the first electrode layer 142 of the central layer of the first filling structure 151 is greater than the thickness of one first electrode layer 142, and the contact area between the subsequent contact structure and the part of the first electrode layer 142 can be larger.
In some embodiments of the present application, the material of the first electrode layer 142 includes metal or polysilicon or a metal compound or amorphous silicon. The metal is, for example, aluminum or titanium, and the metal compound is, for example, titanium oxide or the like.
In some embodiments of the present application, the material of the first insulating layer 141 includes silicon oxide, silicon nitride, aluminum oxide, or hafnium oxide.
In some embodiments of the present application, a sum of 2 times a sum of thicknesses of the first insulating layer 141, the first electrode layer 142, and the second insulating layer 143 and 1.2 times a thickness of the second electrode layer 144 is less than or equal to 2 times a sum of thicknesses of the first insulating layer 141, the first electrode layer 142, the second insulating layer 143, and the second electrode layer 144. Under such a size setting, the central layer of the second filling structure 152 is the second electrode layer 144, and the 2 second electrode layers 144 of the central layer of the second filling structure 152 are combined in a U shape, so that the width of the second electrode layer 144 of the central layer of the second filling structure 152 is greater than the thickness of one second electrode layer 144, and the contact area between the subsequent contact structure and the part of the second electrode layer 144 can be larger.
In some embodiments of the present application, the material of the second electrode layer 144 includes metal or polysilicon or a metal compound or amorphous silicon. The metal is, for example, aluminum or titanium, and the metal compound is, for example, titanium oxide or the like.
In some embodiments of the present application, the material of the second insulating layer 143 includes silicon oxide, silicon nitride, aluminum oxide, or hafnium oxide.
In some embodiments of the present application, a sum of 2 times a sum of thicknesses of the first insulating layer 141, the first electrode layer 142, the second insulating layer 143, the second electrode layer 144, and the third insulating layer 145 and 1.2 times a sum of thicknesses of the third electrode layer 146 is less than or equal to 2 times a sum of thicknesses of the first insulating layer 141, the first electrode layer 142, the second insulating layer 143, the second electrode layer 144, the third insulating layer 145, and the third electrode layer 146. Under such a size setting, the central layer of the third filling structure 153 is the third electrode layer 146, and the 2 third electrode layers 146 of the central layer of the third filling structure 153 are combined in a U shape, so that the width of the third electrode layer 146 of the central layer of the third filling structure 153 is greater than the thickness of one third electrode layer 146, and the contact area between the subsequent contact structure and the part of the third electrode layer 146 can be larger.
In some embodiments of the present application, the material of the third electrode layer 146 includes metal or polysilicon or a metal compound or amorphous silicon. The metal is, for example, aluminum or titanium, and the metal compound is, for example, titanium oxide or the like.
In some embodiments of the present application, the material of the third insulating layer 145 includes silicon oxide, silicon nitride, aluminum oxide, or hafnium oxide.
While three electrode layers are exemplified above, it will be understood by those skilled in the art that the number of the plurality of electrode layers may be four, five or more. The larger the number of stacked electrode layers, the larger the capacitance of the capacitor, but the process of depositing multiple material layers is limited by the semiconductor deposition process and the semiconductor size, and in the actual process, the appropriate number of stacked layers can be selected according to the needs.
In the semiconductor capacitor structure, different electrode layers need to be connected to different contact structures, respectively, and therefore the central layer of the filling structure 150 is each of the plurality of electrode layers. For example, the central layer of the first filling structure 151 is the first electrode layer 142; the central layer of the second filling structure 152 is the second electrode layer 144; the central layer of the third filling structure 153 is the third electrode layer 146.
With continued reference to fig. 11, an interlayer dielectric layer 160 completely covering the semiconductor substrate 100 is formed on the semiconductor substrate 100, and contact structures 170 penetrating through the interlayer dielectric layer 160 and electrically connected to the electrode layers in the centers of the second trenches are formed in the interlayer dielectric layer 160.
In some embodiments of the present application, the material of the interlayer dielectric layer 160 includes silicon oxide.
In some embodiments of the present application, the number of the contact structures 170 is the same as the number of the electrode layers. In some embodiments of the present application, the number of the contact structures 170 is three, and the three contact structures 170 are electrically connected to the first electrode layer 142, the second electrode layer 144 and the third electrode layer 146, respectively.
Fig. 12 is a schematic structural diagram of a semiconductor structure according to further embodiments of the present application.
Comparing the schematic structures of fig. 4 and 12, in other embodiments, a portion of the second trench 120 between the first trenches 110 has a wider width. The increased width locations are used for subsequent fabrication of contact structures. Therefore, the width of the part of the second groove is increased, so that the contact structure with larger width can be prevented from being well electrically connected with the electrode layer in the capacitor.
In the technical solution of the present application, the contact structures 170 are uniformly distributed between any adjacent capacitors 140, and therefore, the distance between each contact structure 170 and the adjacent capacitor 140 is the same, and this distribution manner can minimize the connection resistance between the contact structure 170 and the capacitor 140, improve the upper limit of the capacitance of the capacitor, and further improve the device performance. And, because the contact structure is evenly distributed among a plurality of capacitors, the capacitance difference among the plurality of capacitors can be minimized, and the reliability of the device is improved.
The application provides a semiconductor structure and a forming method thereof, the process for manufacturing the contact structure and electrically communicating each electrode layer is simple and easy to realize, the manufactured contact structure is uniformly distributed in the whole capacitor device, and the connection resistance between the contact structure and the electrode layer is lower.
In view of the above, it will be apparent to those skilled in the art upon reading the present application that the foregoing application content may be presented by way of example only, and may not be limiting. Those skilled in the art will appreciate that the present application is intended to cover various reasonable variations, adaptations, and modifications of the embodiments described herein, although not explicitly described herein. Such alterations, modifications, and variations are intended to be within the spirit and scope of the exemplary embodiments of this application.
It is to be understood that the term "and/or" as used herein in this embodiment includes any and all combinations of one or more of the associated listed items. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may also be present.
Similarly, it will be understood that when an element such as a layer, region or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. In contrast, the term "directly" means that there are no intervening elements. It will be further understood that the terms "comprises," "comprising," "includes" or "including," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It will be further understood that, although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, a first element in some embodiments may be termed a second element in other embodiments without departing from the teachings of the present application. The same reference numerals or the same reference characters denote the same elements throughout the specification.
Further, the present specification describes example embodiments with reference to idealized example cross-sectional and/or plan and/or perspective views. Accordingly, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, example embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region shown as a rectangle will typically have rounded or curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of exemplary embodiments.

Claims (20)

1. A method of forming a semiconductor structure, comprising:
providing a semiconductor substrate;
forming a plurality of second grooves in the semiconductor substrate, wherein the depths of the plurality of second grooves are the same, and the widths of the plurality of second grooves are different;
forming a plurality of first trenches communicated with the plurality of second trenches in the semiconductor substrate;
and forming capacitors in the first grooves and simultaneously forming filling structures in the second grooves, wherein the capacitors comprise a plurality of electrode layers and insulating layers for isolating adjacent electrode layers, and the central layers of the filling structures in the second grooves with different widths are different electrode layers in the electrode layers respectively.
2. The method of forming a semiconductor structure according to claim 1, wherein the capacitor includes a first insulating layer, a first electrode layer, a second insulating layer, a second electrode layer, a third insulating layer, and a third electrode layer which are sequentially located at a bottom and a sidewall of the first trench; the filling structures in the second trenches with different widths are respectively a first filling structure, a second filling structure and a third filling structure.
3. The method of forming a semiconductor structure of claim 2, wherein the first fill structure comprises: and the first insulating layer and the first electrode layer are sequentially positioned at the bottom and the side wall of the second groove and are filled in the second groove.
4. The method of forming a semiconductor structure of claim 2, wherein the second fill structure comprises: and the first insulating layer, the first electrode layer, the second insulating layer and the second electrode layer are sequentially positioned at the bottom of the second groove and on the side wall, and the first insulating layer, the first electrode layer, the second insulating layer and the second electrode layer are filled in the second groove.
5. The method of forming a semiconductor structure of claim 2, wherein the third fill structure comprises: the first insulating layer, the first electrode layer, the second insulating layer, the second electrode layer, the third insulating layer and the third electrode layer are sequentially located at the bottom and the side wall of the second groove, and the first insulating layer, the first electrode layer, the second insulating layer, the second electrode layer, the third insulating layer and the third electrode layer are filled in the second groove.
6. The method according to claim 2, wherein a sum of 2 times a thickness of the first insulating layer and 1.2 times a thickness of the first electrode layer is less than or equal to 2 times a width of the first filling structure is less than or equal to a sum of thicknesses of the first insulating layer and the first electrode layer; the sum of 2 times of the thicknesses of the first insulating layer, the first electrode layer and the second insulating layer and 1.2 times of the thickness of the second electrode layer is less than or equal to 2 times of the thickness of the first insulating layer, the first electrode layer, the second insulating layer and the second electrode layer, and the width of the second filling structure is less than or equal to 2 times of the thickness of the first insulating layer, the first electrode layer, the second insulating layer and the second electrode layer; the sum of 2 times of the thickness sum of the first insulating layer, the first electrode layer, the second insulating layer, the second electrode layer and the third insulating layer and 1.2 times of the thickness sum of the third electrode layer is less than or equal to 2 times of the thickness sum of the first insulating layer, the first electrode layer, the second insulating layer, the second electrode layer, the third insulating layer and the third electrode layer.
7. The method of forming a semiconductor structure of claim 2, wherein forming a capacitor in the first plurality of trenches and simultaneously forming a fill structure in the second plurality of trenches comprises:
sequentially forming a first insulating layer and a first electrode layer in the plurality of first grooves and the plurality of second grooves and on the surface of the semiconductor substrate, wherein the first insulating layer and the first electrode layer are filled in the second grooves with the minimum width;
sequentially forming a second insulating layer and a second electrode layer on the surface of the first electrode layer, wherein the first insulating layer, the first electrode layer, the second insulating layer and the second electrode layer fill a second groove with a second small width;
sequentially forming a third insulating layer and a third electrode layer on the surface of the second electrode layer, wherein the first insulating layer, the first electrode layer, the second insulating layer, the second electrode layer, the third insulating layer and the third electrode layer are filled in a second groove with the largest width;
and removing the first insulating layer, the first electrode layer, the second insulating layer, the second electrode layer, the third insulating layer and the third electrode layer which are higher than the surface of the semiconductor substrate, wherein the capacitor is formed in the first groove, the first filling structure is formed in the second groove with the smallest width, the second filling structure is formed in the second groove with the second smallest width, and the third filling structure is formed in the second groove with the largest width.
8. The method of claim 1, wherein the second trenches have different width types equal to the number of the electrode layers.
9. The method of claim 1, wherein the second trench has an aspect ratio of (0.5-30) to 1 and the first trench has an aspect ratio of (3-50) to 1.
10. The method of forming a semiconductor structure of claim 1, further comprising: and forming an interlayer dielectric layer on the semiconductor substrate, and forming contact structures which penetrate through the interlayer dielectric layer and are electrically connected to the electrode layers in the center of the second groove respectively in the interlayer dielectric layer.
11. The method of forming a semiconductor structure of claim 1, wherein forming a capacitor in the first plurality of trenches and simultaneously forming a fill structure in the second plurality of trenches comprises:
forming a capacitor structure in the first grooves and the second grooves and on the surface of the semiconductor substrate, wherein the capacitor structure comprises a plurality of electrode layers and insulating layers for isolating adjacent electrode layers;
and removing the capacitance structure higher than the surface of the semiconductor substrate, wherein the capacitance structure left in the first groove forms a capacitor, and the capacitance structure left in the second groove forms the filling structure.
12. A semiconductor structure, comprising:
a semiconductor substrate;
the second grooves are positioned in the semiconductor substrate, the depths of the second grooves are the same, and the widths of the second grooves are different;
filling structures are positioned in the plurality of second grooves, and the central layers of the filling structures in the second grooves with different widths are different electrode layers in the plurality of electrode layers respectively;
the plurality of first grooves are communicated with the plurality of second grooves;
and the capacitor is positioned in the first grooves and comprises a plurality of electrode layers and insulating layers for isolating adjacent electrode layers.
13. The semiconductor structure of claim 12, wherein the capacitor comprises a first insulating layer, a first electrode layer, a second insulating layer, a second electrode layer, a third insulating layer, and a third electrode layer sequentially located at a bottom and a sidewall of the first trench; the filling structures in the plurality of second grooves are respectively a first filling structure, a second filling structure and a third filling structure.
14. The semiconductor structure of claim 13, wherein the first fill structure comprises: and the first insulating layer and the first electrode layer are sequentially positioned at the bottom and the side wall of the second groove and are filled in the second groove.
15. The semiconductor structure of claim 13, wherein the second fill structure comprises: the first insulating layer, the first electrode layer, the second insulating layer and the second electrode layer are sequentially located at the bottom and the side wall of the second groove, and the first insulating layer, the first electrode layer, the second insulating layer and the second electrode layer are filled in the second groove.
16. The semiconductor structure of claim 13, wherein the third fill structure comprises: the first insulating layer, the first electrode layer, the second insulating layer, the second electrode layer, the third insulating layer and the third electrode layer are sequentially located at the bottom and the side wall of the second groove, and the first insulating layer, the first electrode layer, the second insulating layer, the second electrode layer, the third insulating layer and the third electrode layer are filled in the second groove.
17. The semiconductor structure of claim 13, wherein a sum of 2 times a thickness of the first insulating layer and 1.2 times a thickness of the first electrode layer is less than or equal to 2 times a width of the first fill structure; the sum of 2 times of the thicknesses of the first insulating layer, the first electrode layer and the second insulating layer and 1.2 times of the thickness of the second electrode layer is less than or equal to 2 times of the thickness of the first insulating layer, the first electrode layer, the second insulating layer and the second electrode layer, and the width of the second filling structure is less than or equal to 2 times of the thickness of the first insulating layer, the first electrode layer, the second insulating layer and the second electrode layer; the sum of 2 times of the thickness sum of the first insulating layer, the first electrode layer, the second insulating layer, the second electrode layer and the third insulating layer and 1.2 times of the thickness sum of the third electrode layer is less than or equal to 2 times of the thickness sum of the first insulating layer, the first electrode layer, the second insulating layer, the second electrode layer, the third insulating layer and the third electrode layer.
18. The semiconductor structure of claim 12, wherein the number of the second trenches is the same as the number of the electrode layers.
19. The semiconductor structure of claim 12, wherein the second trench has an aspect ratio of (0.5-30) to 1 and the first trench has an aspect ratio of (3-50) to 1.
20. The semiconductor structure of claim 12, further comprising: the semiconductor substrate comprises an interlayer dielectric layer positioned on the semiconductor substrate and contact structures which penetrate through the interlayer dielectric layer and are electrically connected to the electrode layers in the center of the second groove respectively.
CN202210408183.5A 2022-04-19 2022-04-19 Semiconductor structure and forming method thereof Pending CN114883491A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2024066278A1 (en) * 2022-09-29 2024-04-04 长鑫存储技术有限公司 Trench capacitor packaging structure and preparation method therefor, and semiconductor structure

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2024066278A1 (en) * 2022-09-29 2024-04-04 长鑫存储技术有限公司 Trench capacitor packaging structure and preparation method therefor, and semiconductor structure

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