CN115223981A - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN115223981A
CN115223981A CN202110843290.6A CN202110843290A CN115223981A CN 115223981 A CN115223981 A CN 115223981A CN 202110843290 A CN202110843290 A CN 202110843290A CN 115223981 A CN115223981 A CN 115223981A
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CN
China
Prior art keywords
wiring layer
layer
wiring
gate
semiconductor device
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Pending
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CN202110843290.6A
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English (en)
Inventor
竹田骏
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Toshiba Electronic Devices and Storage Corp
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Toshiba Corp
Toshiba Electronic Devices and Storage Corp
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Publication of CN115223981A publication Critical patent/CN115223981A/zh
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Abstract

提供一种能够实现半导体元件的高集成化和在动作时产生的电感的降低的半导体装置。实施方式的半导体装置具有第1基板、第2基板、第1金属层、第2金属层、第1半导体元件、第2半导体元件、第1端子、第2端子、第3端子、第1栅极端子和第2栅极端子。第2基板在第1方向上与第1基板分离而设置，具有主配线和信号配线。主配线具有第1配线层、第2配线层、第3配线层和第4配线层。信号配线具有设置在与主配线不同的层的第1栅极配线层、以及设置在与主配线不同的层的第2栅极配线层。第1半导体元件设置在第1金属层上，具有第1电极、第2电极和第1栅极电极。第2半导体元件设置在第2金属层上，具有第3电极、第4电极和第2栅极电极。

Description

半导体装置
本申请基于日本专利申请第2021－70759号(申请日：2021年4月20日)主张优先权，这里通过参照而引用其全部内容。
技术领域
本发明的实施方式涉及半导体装置。
背景技术
以往的功率模块在基板上搭载有半导体元件。半导体元件的电极通过金属细线等配线与基板上的电路电连接。
如果在配线中流过电流，则产生电感(Ls)。在截止时产生的浪涌电压由电流变化率与电感的积表示，由于随着通断的高速化电流变化率变大，所以浪涌电压变大。如果浪涌电压超过规定的电压，则有可能击穿半导体元件，所以要求减小电感。
作为使电感减小的一例，存在使电流朝向相反的配线对置的方法。但是，在使用形成于绝缘电路基板上的二维的电路的情况下，由配线间的对置电流带来的电感的抵消效果小。此外，在将配线设置于1片绝缘电路基板上的情况下，不能将半导体元件高密度地集成。
发明内容
本发明的实施方式提供一种能够实现半导体元件的高集成化和在动作时产生的电感的降低的半导体装置。
实施方式的半导体装置具有第1基板、第2基板、第1金属层、第2金属层、第1半导体元件、第2半导体元件、第1端子、第2端子、第3端子、第1栅极端子和第2栅极端子。第1金属层设置在第1基板上。第2金属层与第1金属层分离而设置在第1基板上。第2基板在第1方向上与第1基板分离而设置，具有主配线和信号配线。主配线具有与第1金属层电连接的第1配线层、与第2金属层电连接的第2配线层、与第1配线层及第2配线层分离而设置的第3配线层、以及与第3配线层电连接的第4配线层。信号配线具有在第1方向上设置在与主配线不同的层的第1栅极配线层、以及在第1方向上设置在与主配线不同的层的第2栅极配线层。第1半导体元件设置在第1金属层上，具有第1电极、第2电极和第1栅极电极。第1电极与第1金属层电连接，设置在第1半导体元件的第1面。第2电极与第2配线层电连接，设置在第1半导体元件的与第1面对置的第2面。第1栅极电极与第1栅极配线层电连接，设置在第1半导体元件的第2面。第2半导体元件设置在第2金属层上，具有第3电极、第4电极和第2栅极电极。第3电极与第2金属层电连接，设置在第2半导体元件的第1面。第4电极与第4配线层电连接，设置在第2半导体元件的与第1面对置的第2面。第2栅极电极与第2栅极配线层电连接，设置在第2半导体元件的第2面。第1端子与第1配线层电连接。第2端子与第3配线层电连接。第3端子与第2金属层电连接。第1栅极端子与第1栅极配线层电连接。第2栅极端子与第2栅极配线层电连接。
附图说明
图1的(a)是有关第1实施方式的半导体装置100的俯视图。图1的(b)是有关第1实施方式的半导体装置100的俯视图。
图2的(a)是图1的(b)所示的A－A’线的剖面图。图2的(b)是图1的(b)所示的B－B’线的剖面图。图2的(c)是图1的(b)所示的C－C’线的剖面图。
图3的(a)是图1的(b)所示的D－D’线的剖面图。图3的(b)是图1的(b)所示的E－E’线的剖面图。图3的(c)是图1的(b)所示的F－F’线的剖面图。图3的(d)是图1的(b)所示的G－G’线的剖面图。
图4是有关第1实施方式的半导体装置100的等价电路。
图5是有关第1实施方式的变形例的半导体装置101的剖面图。
图6是有关第1实施方式的变形例的半导体装置102的剖面图。
图7是有关比较例的半导体装置300的剖面图。
图8是有关第2实施方式的半导体装置200的剖面图。
图9是第1半导体元件30、第2半导体元件31的表面和背面的斜视图。
具体实施方式
以下，一边参照附图一边对本发明的实施方式进行说明。在进行说明时，对于全部的图，对共同的部分赋予共同的标号。此外，附图的尺寸比例并不限定于图示的比例。另外，本实施方式并不限定本发明。
[第1实施方式]
(半导体装置100的构造)
参照图1、图2、图3及图4对有关第1实施方式的半导体装置100的详细的构造进行说明。图1的(a)示出了有关第1实施方式的半导体装置100的俯视图。图1的(b)从图1的(a)投影第2基板12，示出了第1半导体元件30及第2半导体元件31的上表面俯视图。
图2的(a)示出了图1的(b)所示的A－A’线的剖面图，图2的(b)示出了图1的(b)所示的B－B’线的剖面图，图2的(c)示出了图1的(b)所示的C－C’线的剖面图。图3的(a)示出了图1的(b)所示的D－D’线的剖面图，图3的(b)示出了图1的(b)所示的E－E’线的剖面图，图3的(c)示出了图1的(b)所示的F－F’线的剖面图，图3的(d)示出了图1的(b)所示的G－G’线的剖面图。图4示出了有关第1实施方式的半导体装置100的等价电路。
有关第1实施方式的半导体装置100是功率半导体模块。有关第1实施方式的半导体装置100如图4所示，是能够用1个模块构成半桥电路的所谓的“2in1”型的模块。
半导体装置100具有树脂壳体1、盖2、第1基板11、第2基板12、第1金属层21、第2金属层22、第3金属层23、第1半导体元件30、第2半导体元件31、第1导体层41、第2导体层42、第3导体层43、第4导体层44、第5导体层45、第1栅极导体层46、第2栅极导体层47、第1端子51、第2端子52、第3端子53、第1栅极端子54、第2栅极端子55、第1源极感测端子56和第2源极感测端子57。
将从第1基板11朝向第2基板12的方向设为Z方向(第1方向)。此外，将与Z方向正交的方向设为X方向(第2方向)，将与X方向及Z方向正交的方向设为Y方向(第3方向)。图1所示的半导体装置100示出了X－Y平面的俯视图，图2的(a)所示的半导体装置100示出了X－Z平面的剖面图，图2的(b)、图2的(c)及图3所示的半导体装置100示出了Y－Z平面的剖面图。另外，X方向、Y方向及Z方向在本实施方式中用正交关系表示，但并不限于正交，只要是相互相交的关系即可。此外，为了便于说明，将从第1基板11朝向第2基板12的方向称作“上”，将其相反方向称作“下”。
第1基板11是具有第1面和第2面的绝缘性的基板。在第1基板11的第1面，设置有第1金属层21、第2金属层22和第3金属层23。第1基板11的第2面与散热板3连接。
树脂壳体1立起设置在第1基板11的周围。在树脂壳体1设置有盖2。此外，在树脂壳体1的内部，作为密封材料而填充了硅胶4。树脂壳体1、盖2、第1基板11及硅胶4具有对半导体装置100内的部件进行保护或绝缘的功能。
第1金属层21、第2金属层22及第3金属层23在第1基板11的第1面之上相互分离而设置。第2金属层22在X方向上设置在第1金属层21与第3金属层23之间。第1金属层21、第2金属层22及第3金属层23例如由铜(Cu)板构成。
第2基板12在Z方向上在第1基板11的第1面侧与第1基板11分离而设置。第2基板12具有第1配线层61、第2配线层62、第3配线层63、第4配线层64、第5配线层65、第1栅极配线层66、第2栅极配线层67、第1源极感测配线层68、第2源极感测配线层69、第1导通接触孔71(第1连接部)、第2导通接触孔72(第2连接部)、第3导通接触孔73(第3连接部)、第4导通接触孔74(第4连接部)、第5导通接触孔75(第5连接部)和第6导通接触孔76(第6连接部)。
第1配线层61如图1的(a)、图2及图3的(d)所示，设置在第2基板12的上部，位于第1金属层21的上侧。第1配线层61在Y方向上延伸而设置。此外，第5配线层65如图2的(a)及图3的(d)所示，设置在第2基板12的下部，位于第1配线层61与第1金属层21之间。并且，第1导通接触孔71如图2的(a)及图3的(d)所示，在第1配线层61与第5配线层65之间的第2基板12内部设置多个，将第1配线层61与第5配线层65电连接。
第3配线层63如图1的(a)、图2的(a)、图3的(a)及图3的(b)所示，设置在第2基板12的上部，位于第2金属层22及第3金属层23的上侧。第3配线层63在Y方向上延伸而设置，在X方向上与第1配线层61相邻。此外，第4配线层64如图2的(a)及图3的(b)所示，设置在第2基板12的下部，位于第2金属层22及第3金属层23的上侧。并且，第2导通接触孔72如图2的(a)所示，设置在第3配线层63与第4配线层64之间的第2基板12内，将第3配线层63与第4配线层64电连接。另外，虽然在图中没有表示，但第2导通接触孔72可以与第1导通接触孔71同样地在Y方向上设置多个。
第2配线层62如图2的(a)、图2的(c)及图3的(c)所示，设置在第2基板12的下部，位于第1金属层21及第2金属层22的上侧。第2配线层62在X方向上位于第4配线层64与第5配线层65之间。此外，第2配线层62与第1配线层61在Z方向上分离而设置。进而，第2配线层62的一部分以与第1配线层61的一部分对置的方式设置。
第1栅极配线层66如图2的(a)～图2的(c)所示，在Z方向上设置在与第1配线层61及第2配线层62不同的层。详细地说，第1栅极配线层66设置在第2基板12的内部，并且在Y方向上延伸。
第2栅极配线层67如图2的(a)、图3的(a)及图3的(b)所示，在Z方向上设置在与第3配线层63及第4配线层64不同的层。详细地说，第2栅极配线层67设置在第2基板12的内部，并且在Y方向上延伸。此外，在第2基板12的内部，第1栅极配线层66和第2栅极配线层67在X方向上相邻。
第1源极感测配线层68如图2的(a)～图2的(c)所示，在Z方向上设置在与第1配线层61及第2配线层62不同的层。详细地说，第1源极感测配线层68设置在第2基板12的内部，并且在Y方向上延伸。
第2源极感测配线层69如图2的(a)、图3的(a)及图3的(b)所示，在Z方向上设置在与第3配线层63及第4配线层64不同的层。详细地说，第2源极感测配线层69设置在第2基板12的内部，并且在Y方向上延伸。此外，在第2基板12的内部，第1源极感测配线层68和第2源极感测配线层69在X方向上相邻。
另外，在图2的(a)中，示出了第1栅极配线层66及第1源极感测配线层68设置在第1配线层61与第2配线层62之间，但只要设置在与第1配线层61及第2配线层62不同的层即可，例如也可以从上起按照第1栅极配线层66、第1源极感测配线层68、第1配线层61、第2配线层62的顺序配置。同样地，在图2的(a)中，示出了第2栅极配线层67及第2源极感测配线层69设置在第3配线层63与第4配线层64之间，但只要设置在与第3配线层63及第4配线层64不同的层即可。
将第1配线层61、第2配线层62、第3配线层63、第4配线层64及第5配线层65定义为主配线。此外，将第1栅极配线层66、第2栅极配线层67、第1源极感测配线层68及第2源极感测配线层69定义为信号配线。
第1配线层61、第2配线层62、第3配线层63、第4配线层64、第5配线层65、第1栅极配线层66、第2栅极配线层67、第1源极感测配线层68及第2源极感测配线层69例如由Cu构成。
接着，对设置在第1金属层21或第2金属层22上的第1半导体元件30和第2半导体元件31进行说明。图9示出了第1半导体元件30、第2半导体元件31的表面和背面的斜视图。
第1半导体元件30设置在第1金属层21与第2基板12之间。第1半导体元件30例如是纵型MOSFET，在Z方向上的下表面(第1面P1)形成有第1漏极电极32(第1电极)，在上表面(第2面P2)形成有第1源极电极33(第2电极)及第1栅极电极34。第1漏极电极32与第1金属层21电连接。在第1源极电极33之上设置有第1导体层41，第1源极电极33与第2配线层62经由第1导体层41电连接。此外，由于第2配线层62经由第5导通接触孔75与第1源极感测配线层68电连接，所以第1源极电极33和第1源极感测配线层68电连接。在第1栅极电极34之上设置有第1栅极导体层46，第1栅极电极34与第1栅极配线层66经由第1栅极导体层46和第3导通接触孔73连接。即，第1栅极导体层46与第3导通接触孔73电连接。
第2半导体元件31设置在第2金属层22与第2基板12之间。与第1半导体元件30同样地，第2半导体元件31例如是纵型MOSFET，在Z方向上的下表面(第1面S1)形成有第2漏极电极35(第3电极)，在上表面(第2面S2)形成有第2源极电极36(第4电极)和第2栅极电极37。第2漏极电极35与第2金属层22电连接。在第2源极电极36之上，设置有第2导体层42，第2源极电极36与第4配线层64经由第2导体层42电连接。此外，由于第4配线层64经由第6导通接触孔76与第2源极感测配线层69电连接，所以第2源极电极36和第2源极感测配线层69电连接。在第2栅极电极37之上，设置有第2栅极导体层47，第2栅极电极37与第2栅极配线层67经由第2栅极导体层47和第4导通接触孔74连接。即，第2栅极导体层47与第4导通接触孔74电连接。
第1半导体元件30及第2半导体元件31例如由硅(Si)、碳化硅(SiC)或氮化镓(GaN)等构成。
第3导体层43设置在第2配线层62与第2金属层22之间，将第2配线层62与第2金属层22电连接。即，第1半导体元件30的第1源极电极33经由第2配线层62、第3导体层43及第2金属层22与第2半导体元件31的第2源极电极36电连接。另外，第3导体层43的Z方向的高度大致等同于后述的第1半导体元件30的第1漏极电极(第1电极)32与第1导体层41和第2配线层62的边界部之间的高度。
第4导体层44设置在第1金属层21与第5配线层65之间，将第1金属层21与第5配线层65电连接。另外，第5配线层65设置在第2基板12的下部。此外，如上所述，第1配线层61与第5配线层65经由第1导通接触孔71电连接。即，第1配线层61和第1金属层21经由第1导通接触孔71、第5配线层65及第4导体层44电连接。第5导体层45设置在第3金属层23与第4配线层64之间。
第5导体层45设置在第3配线层63与第4配线层64之间，将第3金属层23与第4配线层64电连接。即，第3金属层23与第2半导体元件31的第2源极电极36电连接。
第1金属层21至第3金属层23、第1配线层61至第5配线层65、第1栅极配线层66、第2栅极配线层67、第1源极感测配线层68及第2源极感测配线层69在Y方向上延伸。此外，在图1～图3中，示出了第1半导体元件30、第2半导体元件31、第1导体层41至第5导体层45、第1栅极导体层46、第2栅极导体层47及第1导通接触孔71至第6导通接触孔76在Y方向上各设置有8个。
各电极和各金属层、各电极和各导体层以及各导体层和各配线层例如使用焊料(未图示)连接。
P电力端子51(第1端子)一端露出在树脂壳体1的外部，另一端与第1配线层61电连接。N电力端子52(第2端子)一端露出在树脂壳体1的外部，另一端与第3配线层63电连接。AC输出端子53(第3端子)一端露出在树脂壳体1的外部，另一端与第2金属层22电连接。
第1栅极端子54一端露出在树脂壳体1的外部，另一端与第1栅极配线层66电连接。第2栅极端子55一端露出在树脂壳体1的外部，另一端与第2栅极配线层67电连接。第1源极感测端子56一端露出在树脂壳体1的外部，另一端与第1源极感测配线层68电连接。第2源极感测端子57一端露出在树脂壳体1的外部，另一端与第2源极感测配线层69电连接。第1源极感测端子56及第2源极感测端子57是源极电位，作为向第1栅极电极34及第2栅极电极37施加电压时的基准。
另外，可以在第1栅极配线层66及第2栅极配线层67连接无源元件。无源元件例如是电阻或电容，为了抑制栅极电压的噪声等目的而设置。
图5示出了有关第1实施方式的变形例的半导体装置101的剖面图。如半导体装置101那样，可以分别在第1漏极电极32与第1金属层21之间设置第6导体层81、在第2漏极电极35与第2金属层22之间设置第7导体层82。关于这以外的结构，半导体装置100和半导体装置101具有同样的结构。
图6示出了有关第1实施方式的变形例的半导体装置102的剖面图。如图6所示，第1半导体元件30可以通过树脂83密封。同样地，第2半导体元件31也可以通过树脂83密封。树脂83例如是环氧树脂。另外，在图6中示出了，能够透过树脂83的一部分看到树脂83的内部(第1半导体元件30、第2半导体元件31)的构造。
(半导体装置100的动作)
对半导体装置100的动作进行说明。
从P电力端子51输入的电流沿X方向及Y方向流过第1配线层61中，到达第1导通接触孔71。然后，电流依次经过第1导通接触孔71、第5配线层65、第4导体层44、第1金属层21，到达第1半导体元件30的漏极电极。当第1栅极电极34的电压为阈值以上时，电流沿纵方向(Z方向)流过第1半导体元件30中，依次经过第1源极电极33、第1导体层41而到达第2配线层62。电流沿X方向经过第2配线层62，流过第3导体层43、第2金属层22后到达AC输出端子53。此时，在第1配线层61中沿X方向流动的电流的朝向与在第2配线层62沿X方向流动的电流的朝向相反。
当第2栅极电极37的电压为阈值以上时，到达了AC输出端子53的电流依次经过第2金属层22、第2漏极电极35、第2源极电极36、第2导体层42，沿X方向流过第4配线层64。然后，电流经过第2导通接触孔72，沿X方向及Y方向经过第3配线层63，从N电力端子52输出。此时，在第4配线层64中沿X方向流动的电流的朝向与在第3配线层63沿X方向流动的电流的朝向相反。
(第1实施方式的效果)
对于有关第1实施方式的半导体装置100的效果，使用有关比较例的半导体装置300进行说明。图7示出了有关比较例的半导体装置300的剖面图。对于与有关第1实施方式的半导体装置100相同的部分标注相同的标号。
对比较例的半导体装置300的构造进行说明。半导体装置300没有设置第2基板12，而在第1基板11上设置有第3配线层63、第1栅极配线层66及第2栅极配线层67，这一点与有关第1实施方式的半导体装置100不同。进而，第1源极电极33和第2金属层22、第1栅极电极34和第1栅极配线层66、第2源极电极36和第3配线层63、第2栅极电极37和第2栅极配线层67例如使用焊料通过金属细线90连接。
对于有关比较例的半导体装置300，在第1基板11上需要有设置第3配线层63、第1栅极配线层66及第2栅极配线层67的区域。
此外，对于有关比较例的半导体装置300，由于第1半导体元件30及第2半导体元件31的各电极和各配线层分别通过金属细线90连接，所以使用配线层间的对置电流抵消电感(Ls)的效果小。此外，由于金属细线90细，所以在金属细线90产生的电感(Ls)大。在半导体装置截止时产生的浪涌电压由电流变化率与电感的积表示，由于随着通断的高速化电流变化率变大，所以浪涌电压变大。如果浪涌电压超过规定的电压，则半导体元件有可能被击穿。
另一方面，有关第1实施方式的半导体装置100在第1基板11的上侧设置有第2基板12，主配线及信号配线设置于第2基板12。因此，与在第1基板11上设置有主配线层的一部分及信号配线层的比较例相比，在第1基板11上能够安装半导体元件的面积增加。即，有关第1实施方式的半导体装置100与有关比较例的半导体装置300相比，能够使单位面积能够流过的电流变大。
此外，如上所述，在第1配线层61中沿X方向流动的电流的朝向与在第2配线层62沿X方向流动的电流的朝向相反。同样地，在第4配线层64中沿X方向流动的电流的朝向与在第3配线层63沿X方向流动的电流的朝向相反。第1配线层61和第2配线层62在Z方向上相向设置。此外，第3配线层63和第4配线层64在Z方向上相向设置。因此，在有关第1实施方式的半导体装置100动作时产生的电感(Ls)被朝向相反的对置电流抵消。由此，半导体装置100能够使通断时的浪涌电压变小，能够抑制半导体元件的击穿。
进而，第2配线层62与上述第1导体层41的接合分界面、第2配线层62与第3导体层43的接合分界面、第4配线层64与第2导体层42的接合分界面、以及第5配线层65与第4导体层44的接合分界面位于相同的X－Y平面上。因而，在将第1漏极电极32和第1金属层21、第1源极电极33和第1导体层41及第2配线层62、第1栅极导体层46和第1栅极电极34及第3导通接触孔73、第2漏极电极35和第2导体层42、第2源极电极36和第2导体层42及第4配线层64、第2栅极导体层47和第2栅极电极37及第4导通接触孔74、第3导体层43和第2金属层22及第2配线层62、第4导体层44和第1金属层21及第5配线层65、第5导体层45和第3金属层23及第4配线层64使用焊料等连接时，能够使用回流炉同时连接。因此，与在通过金属细线90连接第1半导体元件30及第2半导体元件31的各电极和各配线时将金属细线90一根根地通过焊料等连接的半导体装置300相比，半导体装置100能够减少制造工序数。
进而，有关本实施方式的半导体装置100具有第3金属层23及第5导体层45。通过设置第3金属层23及第5导体层45，能够将在半导体装置100的接通动作时产生的热量更有效率地排出。此外，通过设置第3金属层23及第5导体层45，能够使半导体装置100的接通动作时的电流分布变得均匀。但是，即使不设置第3金属层23及第5导体层45，也能够实施半导体装置100。
[第2实施方式]
(半导体装置200的构造)
参照图8对有关第2实施方式的半导体装置200进行说明。图8是有关第2实施方式的半导体装置200的剖面图。图8所示的剖面图相当于图1的(b)中的A－A’线的剖面位置。
有关第2实施方式的半导体装置200在第2基板12设置有屏蔽层84，这一点与有关第1实施方式的半导体装置100不同。更详细地说，屏蔽层84设置在主配线(第1配线层61、第2配线层62、第3配线层63、第4配线层64、第5配线层65)与信号配线(第1栅极配线层66、第2栅极配线层67、第1源极感测配线层68、第2源极感测配线层69)之间。屏蔽层84例如由铜构成，设置为浮动电位。关于与有关第1实施方式的半导体装置100重复的点省略记载。
流过主配线的电流的大小根据时间而变化。电流大小随着时间变化产生电磁噪声，给信号配线带来影响。
对于有关第2实施方式的半导体装置200，在主配线与信号配线之间设置有屏蔽层84。因此，半导体装置200能够减小通过主电路的电流变化产生的电磁噪声给信号配线层带来的影响，所以能够抑制误动作的发生。
说明了本发明的几个实施方式，但这些实施方式是作为例子提示的，不是要限定发明的范围。这些新的实施方式能够以其他各种各样的形态实施，在不脱离发明的主旨的范围内能够进行各种各样的省略、替换、变更。这些实施方式及其变形包含在发明的范围或主旨中，并且包含在权利要求书所记载的发明和其等价的范围中。

Claims (10)

1.一种半导体装置，其具有：
第1基板；
第1金属层，设置在所述第1基板上；
第2金属层，与所述第1金属层分离而设置在所述第1基板上；
第2基板，在第1方向上与所述第1基板分离而设置，具有主配线和信号配线，所述主配线具有与所述第1金属层电连接的第1配线层、与所述第2金属层电连接的第2配线层、与所述第1配线层及所述第2配线层分离而设置的第3配线层以及与所述第3配线层电连接的第4配线层，所述信号配线具有在所述第1方向上设置在与所述主配线不同的层的第1栅极配线层以及在所述第1方向上设置在与所述主配线不同的层的第2栅极配线层；
第1半导体元件，设置在所述第1金属层上，具有与所述第1金属层电连接并设置在所述第1半导体元件的第1面的第1电极、与所述第2配线层电连接并设置在所述第1半导体元件的与所述第1面对置的第2面的第2电极、以及与所述第1栅极配线层电连接并设置在所述第1半导体元件的所述第2面的第1栅极电极；
第2半导体元件，设置在所述第2金属层上，具有与所述第2金属层电连接并设置在所述第2半导体元件的第1面的第3电极、与所述第4配线层电连接并设置在所述第2半导体元件的与所述第1面对置的第2面的第4电极、以及与所述第2栅极配线层电连接并设置在所述第2半导体元件的所述第2面的第2栅极电极；
第1端子，与所述第1配线层电连接；
第2端子，与所述第3配线层电连接；
第3端子，与所述第2金属层电连接；
第1栅极端子，与所述第1栅极配线层电连接；以及
第2栅极端子，与所述第2栅极配线层电连接。
2.如权利要求1所述的半导体装置，其中，
所述信号配线还具有与所述第2电极电连接的第1源极感测配线层、以及与所述第4电极电连接的第2源极感测配线层；
所述半导体装置还具有：
第1源极感测端子，与所述第1源极感测配线层电连接；以及
第2源极感测端子，与所述第2源极感测配线层电连接。
3.如权利要求1或2所述的半导体装置，其中，
所述半导体装置还具有：
第1导体层，设置在所述第2电极与所述第2配线层之间；
第1栅极导体层，设置在所述第1栅极电极与所述第1栅极配线层之间；
第2导体层，设置在所述第4电极与所述第4配线层之间；
第2栅极导体层，设置在所述第2栅极电极与所述第2栅极配线层之间；
第3导体层，设置在所述第2金属层与所述第2配线层之间；
第4导体层，经由第1连接部与所述第1配线层电连接；以及
第5配线层，设置在所述第2基板，设置在所述第1配线层与所述第4导体层之间。
4.如权利要求1或2所述的半导体装置，其中，
所述半导体装置还具有：
第3金属层，以在与所述第1方向相交的第2方向上与所述第2金属层相邻的方式设置在所述第1基板上；以及
第5导体层，设置在所述第3金属层与所述第4配线层之间。
5.如权利要求1或2所述的半导体装置，其中，
所述第1配线层的一部分在所述第1方向上与所述第2配线层的一部分对置设置；所述第3配线层的一部分在所述第1方向上与所述第4配线层的一部分对置设置。
6.如权利要求1或2所述的半导体装置，其中，
在所述主配线与所述信号配线之间设置有屏蔽层。
7.如权利要求1或2所述的半导体装置，其中，
所述半导体装置还具有：
第6导体层，设置在所述第1电极与所述第1金属层之间；以及
第7导体层，设置在所述第3电极与所述第2金属层之间。
8.如权利要求3所述的半导体装置，其中，
所述第2配线层与所述第1导体层的接合分界面、所述第2配线层与所述第3导体层的接合分界面、所述第4配线层与所述第2导体层的接合分界面、以及所述第5配线层与所述第4导体层的接合分界面在所述第2方向上位于同一平面上。
9.如权利要求1或2所述的半导体装置，其中，
在所述信号配线连接着无源元件。
10.如权利要求1或2所述的半导体装置，其中，
流过所述第1配线层的电流的朝向和流过所述第2配线层的电流的朝向在所述第2方向上是相反的朝向；
流过所述第3配线层的电流的朝向和流过所述第4配线层的电流的朝向在所述第2方向上是相反的朝向。
CN202110843290.6A 2021-04-20 2021-07-26 半导体装置 Pending CN115223981A (zh)

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