CN115223976A - 具有引脚配合引线的高电压半导体封装 - Google Patents

具有引脚配合引线的高电压半导体封装 Download PDF

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Publication number
CN115223976A
CN115223976A CN202210416728.7A CN202210416728A CN115223976A CN 115223976 A CN115223976 A CN 115223976A CN 202210416728 A CN202210416728 A CN 202210416728A CN 115223976 A CN115223976 A CN 115223976A
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opening
die pad
semiconductor package
semiconductor
outer edge
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CN202210416728.7A
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English (en)
Inventor
E·S·卡巴特巴特
颜台棋
K·M·顾
段珂颜
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Infineon Technologies AG
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Infineon Technologies AG
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Publication of CN115223976A publication Critical patent/CN115223976A/zh
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Abstract

本文公开了一种半导体封装，其包括：管芯焊盘；安装在管芯焊盘上并且包括背离管芯焊盘的第一端子和面向管芯焊盘并电连接到管芯焊盘的第二端子；电连接到第一端子的互连夹；包封半导体管芯和互连夹的电绝缘材料的包封体；以及包封体中的暴露互连夹的表面的第一开口，包封体包括下表面、与下表面相对的上表面、以及在下表面与上表面之间延伸的第一外边缘侧，并且第一开口从第一外边缘侧横向偏移。

Description

具有引脚配合引线的高电压半导体封装
技术领域
本申请涉及半导体器件，并且更具体地涉及用于高电压应用的半导体封装。
背景技术
在半导体封装中提供诸如MOSFET(金属氧化物半导体场效应晶体管)、IGBT(绝缘栅双极晶体管)和HEMT(高电子迁移率晶体管)的高电压半导体器件。半导体封装包括保护性绝缘体和导电引线或触点，这些引线或触点为半导体管芯的端子提供外部可访问的电接触点。在高电压应用中，半导体封装的一个重要设计考虑因素是爬电距离。半导体封装的适应在器件正常操作期间的高电压(例如，100V、500V、1000V或更高的量级)的引线或触点需要大的爬电距离，以防止不想要的电弧放电和/或器件故障。然而，增加半导体封装的引线或触点之间的爬电距离与使半导体封装尽可能小的总体期望相冲突。
发明内容
本领域技术人员在阅读以下具体实施方式并查看附图后将认识到附加的特征和优点。
公开了一种半导体封装。根据实施例，半导体封装包括：管芯焊盘、安装在管芯焊盘上并包括背离管芯焊盘的第一端子和面向管芯焊盘并电连接到管芯焊盘的第二端子的半导体管芯、电连接到第一端子的互连夹、包封半导体管芯和互连夹的电绝缘材料的包封体、以及包封体中的暴露互连夹的表面的第一开口，其中包封体包括下表面、与下表面相对的上表面、以及在下表面与上表面之间延伸的第一外边缘侧，其中第一开口从第一外边缘侧横向偏移。
单独地或组合地，管芯焊盘的外表面从所述上表面暴露，并且第一开口从所述下表面延伸到包封体中。
单独地或组合地，管芯焊盘的外表面的一端与第一外边缘侧横向间隔开，并且管芯焊盘的被暴露的外表面与互连夹的暴露表面之间的爬电距离包括管芯焊盘的端部与第一外边缘侧之间沿上表面的距离、上表面与下表面之间沿第一外边缘侧的距离、以及第一外边缘侧与第一开口之间沿下表面的距离。
单独地或组合地，爬电距离还包括下表面与互连夹之间沿第一开口的最靠近第一外边缘侧的第一侧壁的距离。
单独地或组合地，第一侧壁包括一个或多个阶梯形过渡部，并且一个或多个阶梯形过渡部中的每一个包括包封体的平面表面之间的成角度的交叉部。
单独或组合地，包封体包括较宽部分和在较宽部分顶部的较窄部分，并且爬电距离包括沿着包封体的形成较宽部分和较窄部分之间的过渡部的一个或多个表面的距离。
单独地或组合地，半导体封装进一步包括：第一导电引线，其连续地连接到管芯焊盘并且包括从管芯焊盘垂直偏移的横向跨越部(span)；以及包封体中的暴露第一引线的位于所述横向跨越部中的表面的第二开口，并且第二开口从下表面延伸到包封体中。
单独地或组合地，包封体包括在下表面与上表面之间延伸且与第一外边缘侧相对的第二外边缘侧，并且第二开口从第二外边缘侧横向偏移。
单独地或组合地，第一开口和第二开口均包括相对面对的侧壁，第一开口和第二开口的侧壁包括一个或多个阶梯形过渡部，并且一个或多个阶梯形过渡部中的每一个包括包封体的平面表面之间的成角度的交叉部。
单独地或组合地，互连夹包括导电的第一部分和电绝缘的第二部分，第一部分电连接到第一端子并且包括被第一开口暴露的表面，并且第二部分接触第一导电引线的横向跨越部。
单独地或组合地，半导体管芯是分立的功率器件，并且第一端子和第二端子是半导体管芯的电压阻挡端子。
公开了一种半导体器件组件。根据实施例，半导体器件组件包括：半导体封装，其包括管芯焊盘、安装在管芯焊盘上并且包括背离管芯焊盘的第一端子和面向管芯焊盘并电连接到管芯焊盘的第二端子的半导体管芯、电连接到第一端子的互连夹、包封半导体管芯和互连夹的电绝缘材料的包封体、以及包封体中的暴露互连夹的表面的第一开口；以及第一连接器，其可附接至半导体封装，且第一连接器被配置为插入第一开口中并在附接位置与互连夹的从包封体暴露的表面形成导电连接。
单独地或组合地，第一连接器包括在附接位置接触互连夹的表面的导电柱。
单独地或组合地，第一连接器还包括围绕导电柱的电绝缘套管，并且在附接位置，电绝缘套管与第一开口的相对面对的侧壁啮合。
单独地或组合地，第一开口包括相对面对的侧壁，相对面对的侧壁包括一个或多个阶梯形过渡部，一个或多个阶梯形过渡部中的每一个包括包封体的平面表面之间的成角度的交叉部，并且电绝缘套管在第一开口的最宽部分中与相对面对的侧壁啮合。
单独地或组合地，包封体包括下表面、与下表面相对的上表面、以及在下表面和上表面之间延伸的第一外边缘侧，管芯焊盘的外表面从包封体的上表面暴露，并且管芯焊盘的从包封体暴露的外表面与互连夹的暴露表面之间的爬电距离包括管芯焊盘的端部与第一外边缘侧之间沿上表面的距离、上表面与下表面之间沿第一外边缘侧的距离、以及第一外边缘侧与第一开口之间沿下表面的距离。
单独地或组合地，半导体器件组件进一步包括电路载体，该电路载体包括电绝缘衬底和结构化金属化层，并且第一连接器在互连夹和结构化金属化层之间形成电连接。
单独地或组合地，第一连接器是电路载体的一体形成的元件。
单独地或组合地，第一连接器是与电路载体和半导体封装分开的独立元件。
单独地或组合地，半导体封装进一步包括：第一导电引线，其连续地连接到管芯焊盘并且包括从管芯焊盘垂直偏移的横向跨越部；以及包封体中的暴露所述横向跨越部的表面的第二开口，半导体器件组件还包括第二连接器，该第二连接器可附接到半导体封装并且包括第二导电柱，并且第二连接器被配置为插入到第二开口中并在附接位置与第一导电引线的表面形成第二导电连接。
附图说明
附图的元件不必相对于彼此按比例。类似的附图标记表示对应的相似部分。各种图示的实施例的特征可以组合，除非它们相互排斥。实施例在附图中被描绘并且在下面的描述中被详细描述。
图1A、图1B、图1C和图1D描绘了根据实施例的半导体封装。图1A从平面透视图描绘了半导体封装的内部元件；图1B从侧面透视图描绘了半导体封装，其中内部元件是可见的；图1C从半导体封装的下表面上的平面透视图描绘了半导体封装的外部；并且图1D从半导体封装的上表面上的平面透视图描绘了半导体封装的外部。
图2从侧视透视图描绘了根据另一实施例的半导体封装，其中内部元件是可见的。
图3从侧视透视图描绘了根据另一实施例的半导体封装，其中内部元件是可见的。
图4A和图4B描绘了根据另一个实施例的半导体封装。图4A从平面透视图描绘了半导体封装的内部元件；并且图4B从侧面透视图描绘了半导体封装，其中内部元件是可见的。
图5A和图5B描绘了根据实施例的包括电路载体、导电连接器和半导体封装的半导体器件组件。图5A描绘了在将连接器插入半导体封装的开口之前的组件；并且图5B描绘了在将连接器插入半导体封装的开口之后的组件。
图6描绘了根据另一实施例的包括电路载体、导电连接器和半导体封装的半导体器件组件。
图7A和图7B描绘了根据实施例的包括半导体封装和导电连接器的半导体器件组件。图7A描绘了在将连接器插入半导体封装的开口之前的组件；并且图7B描绘了在将连接器插入半导体封装的开口之后的组件。
图8A和图8B描绘了根据另一实施例的包括半导体封装和导电连接器的半导体器件组件。图8A描绘了在将连接器插入半导体封装的开口之前的组件；并且图8B描绘了在将连接器插入半导体封装的开口之后的组件。
图9A和图9B描绘了形成导电连接器的方法。图9A描绘了附接到外围环的多个导电连接器；并且图9B描绘了从外围环分离的导电连接器。
图10描绘了根据实施例的用于形成半导体封装并将导电连接器插入到半导体封装的开口中的工艺流程。
具体实施方式
本文描述了相对于整个半导体封装尺寸具有有利的高爬电距离的半导体封装的实施例。高爬电距离导致半导体封装的上表面处的暴露的管芯焊盘与半导体封装的下表面处的暴露的互连夹之间的大距离。通过插入到半导体封装的下表面中的开口中的可插入导电连接器而接触暴露的互连夹。有利地，半导体封装的三个侧面有助于半导体封装的上表面处的暴露的管芯焊盘与半导体封装的下表面处的暴露的互连夹之间的爬电距离。因此，器件的电压阻挡端子之间的爬电距离可以有利地包括封装的外边缘侧的完整长度以及外边缘侧与容纳可插入导电连接器的开口之间的横向偏移距离。
参考图1A-1D，描绘了根据实施例的半导体封装100。如图1A所示，半导体封装100包括引线框架102。引线框架102包括导电材料，例如Cu(铜)、Ni(镍)、NiP(镍磷)、Ag(银)、Pd(钯)、Au(金)等，以及它们的合金或组合。引线框架102可以由基本上平面的金属片材提供，例如，所述片材包括以上列出的材料中的任何一种或多种，并且可以通过执行诸如冲压、冲孔、蚀刻、弯曲等金属加工技术来在该平面金属片材上提供本文所示和描述的引线框架102的几何特征。引线框架102包括管芯焊盘104，该管芯焊盘104包括大致平面的管芯附接表面。引线框架102另外包括从管芯焊盘104延伸出来的多个引线。如图所示，引线框架包括一组第一引线106和第二引线108。该组第一引线106中的每个引线连续地连接到管芯焊盘104。第二引线108与管芯焊盘104断开连接。如图1B所示，引线框架102可以具有所谓的下移构造。根据该构造，该组第一引线106随着它们接近管芯焊盘104而向下弯曲，使得管芯焊盘104沿与第一引线106不同的垂直平面设置。
如图1A-1B所示，半导体封装100还包括安装在管芯焊盘104上的半导体管芯110。一般而言，半导体管芯110可以具有多种器件构造。这些器件构造的示例包括分立器件，例如MOSFET(金属氧化物半导体场效应晶体管)、IGBT(绝缘栅双极晶体管)和HEMT(高电子迁移率晶体管)、JFET(结型场效应晶体管)、二极管等。这些器件构造的附加示例包括集成电路器件，例如控制器、驱动器、放大器、处理器、传感器等。半导体管芯110可以包括IV型半导体材料(例如，硅、硅锗、碳化硅等)和/或III-V型半导体材料(例如氮化镓、砷化镓等)。半导体管芯110可以被配置为垂直器件，该垂直器件被配置为控制在相对面对的主表面和后表面之间流动的电流。替代地，半导体管芯110可以被配置为横向器件，其被配置为控制平行于半导体管芯110的主表面流动的电流。
根据实施例，半导体管芯110被配置为分立功率器件。分立功率器件是额定为控制至少100V、并且更常见为500V或更高量级的大电压和/或控制至少1A、并且更常见为10A或更高量级的大电流的器件。分立功率器件包括晶体管，例如MOSFET(金属氧化物半导体场效应晶体管)、IGBT(绝缘栅双极晶体管)和HEMT(高电子迁移率晶体管)、二极管、JFET(结型场效应晶体管)等。在分立功率器件的具体示例中，半导体管芯110被配置为基于碳化硅的MOSFET，其额定为控制1200V的电压。
半导体管芯110可以包括在半导体管芯110的主表面和后表面之一或两者上的多个导电接合焊盘。这些导电接合焊盘被配置为半导体管芯110的器件端子。在所描绘的实施例中，半导体管芯110包括设置在半导体管芯110的背离管芯焊盘104的主表面上的第一端子112和设置在半导体管芯110的面向管芯焊盘104的后表面上的第二端子114(如图1B所示)。第二端子114电连接到管芯焊盘104。这种电连接可以包括导电粘合剂，例如，焊料、烧结物、导电胶、扩散焊料等。根据实施例，第一端子112和第二端子114是半导体管芯110的电压阻挡端子。半导体管芯110的电压阻挡端子是控制负载电压的端子。例如，电压阻挡端子在MOSFET的情况下可以是漏极端子和源极端子，在IGBT的情况下可以是发射极和集电极端子，等等。在这个实施例中，第一端子112可以是电压阻挡端子(例如，源极、漏极、集电极、发射极、阳极、阴极等)中的任一个，而第二端子114是电压阻挡端子(例如，漏极、源极、发射极、集电极、阳极、阴极等)中的相对的一个。在所描绘的实施例中，半导体管芯110另外包括设置在半导体管芯110的主表面上的第三端子116。第三端子116可以是被配置为控制第一和第二端子112、114之间的导电连接的控制端子，例如，栅极端子。
半导体封装100还包括互连夹118。互连夹118包括导电材料，例如Cu(铜)、Ni(镍)、NiP(镍磷)、Ag(银)、Pd(钯)、Au(金)等，以及它们的合金或组合。互连夹118可以由包括以上列出的材料中的任何一种或多种的基本上平面的金属片材提供，并且可以通过执行诸如冲压、冲孔、蚀刻、弯曲等金属加工技术来提供本文所示和描述的互连夹118的几何特征。互连夹118电连接到半导体管芯110的第一端子112。该电连接可以包括导电粘合剂，例如焊料、烧结物、导电胶、扩散焊料等。
半导体封装100还包括电连接在第三端子116和第二引线108之间的导电接合线120(图1A中所示)。更一般地，半导体封装100可以包括任何一种或多种不同类型的互连元件，例如接合线、金属夹、带等，以实现任何必要的电互连。
半导体封装100另外包括包封体122(如图1B-1D所示)。包封体122包括密封并保护半导体管芯110和相关联的电连接的电绝缘包封材料，所述电连接包括与互连夹118的电连接。这种包封材料的示例包括模制化合物、热固性塑料、环氧树脂、树脂、层合材料等。可以通过模制工艺形成包封体122，所述模制工艺例如注塑模制、压缩模制、传递模制等。在另一实施例中，通过层合技术形成包封体122，其中多个层合层依次堆叠在彼此顶上。包封体122包括上表面124、与上表面124相对的下表面126、以及在上表面124和下表面126之间延伸的第一外边缘侧128。管芯焊盘104的与半导体管芯110相对的外表面130从包封体122的上表面124暴露出。管芯焊盘104的暴露的外表面可以与半导体管芯110的上表面124共面或基本共面，因此暴露的管芯焊盘104与外部散热器紧密配合。
半导体封装100还包括从包封体122暴露互连夹118的表面的第一开口132和在第一引线106的横向跨越部中暴露第一引线106的表面的第二开口134，第一引线106从管芯焊盘104抬高。第一和第二开口132、134是从下表面126延伸到包封体122中的沟槽状结构。第一开口132包括从包封体122的下表面126延伸到互连夹118的由第一开口132暴露的表面的相对面对的侧壁136。第二开口134同样包括从包封体122的下表面126延伸到第一引线106的从第二开口134暴露的表面的相对面对的侧壁136。在所描绘的实施例中，侧壁136基本垂直于包封体122的下表面126。更一般地，开口可以具有多种几何形状，例如锥形几何形状、弯曲表面等。半导体封装100可以另外包括第三开口138(图1C中所示)，其具有与第一和第二开口132、134相似的构造并且暴露出第二引线108的表面。
第一、第二和第三开口132、134和138可以根据多种技术形成。在一个实施例中，包封体122最初形成为具有完全为平面的包封体122的下表面126，并且通过例如经由蚀刻或研磨从下表面126去除包封材料而形成第一、第二和第三开口132、134和138。根据另一示例，例如，在模制注射工艺的情况下借助于模制腔的适当几何构造，与包封体122的形成同时地形成了第一、第二和第三开口132、134和138。
半导体封装100具有关于电压阻挡端子之间的爬电距离的有利构造。爬电距离是指两个暴露的导电表面之间沿电绝缘材料的最短距离。如前所述，第一端子112和第二端子114可以是器件的电压阻挡端子。半导体封装的与这些电压阻挡端子连接的暴露的导电表面之间的爬电距离可以在管芯焊盘104的外表面130与互连夹118的从第一开口132暴露的表面之间测量。虽然图2未按比例绘制，但应当理解，管芯焊盘104与互连夹118的表面之间的爬电距离测量结果可以短于互连夹118的从第一开口132暴露的表面与第一引线106的从第二开口134暴露的表面之间的距离，从而确定器件的电压阻挡端子之间的爬电距离。因此，半导体封装100的爬电距离包括在管芯焊盘104的端部与第一外边缘侧128之间沿上表面124的第一距离140、在上表面124与下表面126之间沿第一外边缘侧128的第二距离142、第一外边缘侧128与第一开口132之间沿下表面126的第三距离144、以及下表面126与互连夹118之间沿第一开口132的最靠近第一外边缘侧128的第一侧壁136的第四距离146。
通过配置半导体封装100使得第一端子112可经由下表面126上的从第一外边缘侧128横向偏移的开口进行电访问，实现了有利的大的爬电距离。该爬电距离有利地包括包封体122的第一外边缘侧128的整个长度以及包封体122的第一外边缘侧128与第一开口132之间的横向分隔距离。作为比较，在所谓的表面安装型封装中，引线从封装的侧壁突出。因此，如果管芯焊盘从封装的上表面暴露，则爬电距离仅包括上表面的一部分以及封装侧壁的处于上表面与封装引线之间的一部分。表面安装型封装与当前公开的实施例之间在爬电距离方面的有利益处可以通过以下数值示例来证明。如上所述的具有从封装侧壁突出的引线的表面安装型封装可以具有在源极引线与从包封体的上表面暴露的管芯焊盘之间的大约3.15mm(毫米)的爬电距离。根据当前描述的实施例的具有相同体积占用面积和管芯焊盘布置的包封体122的半导体封装100可以具有至少5.0mm的爬电距离，例如在5.5mm至6.0mm的范围内，这意味着爬电距离改善至少59％，例如在75％到90％的范围内。这些值仅代表一种特定的封装构造，并且更一般地，代表跨多种封装构造对爬电距离的改进是可能的。
如图所示，第一引线106可以可选地包括至少到达包封体206的与第一外边缘侧128相对的外边缘侧的部分。该部分可以对应于最初连接在引线框架条的外环与引线框架102之间并在包封之后被修整的剩余引线框架部分。该部分可以与包封体206的外边缘侧齐平或者可以稍微向外突出(如图所示)。第二引线108同样可以具有类似的构造。
参考图1C，半导体封装可以包括一组第一开口132，其中这些第一开口132中的每一个被布置成与第一外边缘侧128隔开相同距离的行。以这种方式，跨第一外边缘侧128测量的最小爬电距离被维持用于第一开口中的每一个。此外，第一开口132可以被布置成使得跨与第一外边缘侧128交叉的第二外边缘侧148的爬电距离测量结果等于或大于跨第一外边缘侧128测量的最小爬电距离。例如，最靠近第二外边缘侧148的第一开口132可以与第二外边缘侧148横向间隔开一定距离，该距离与第一开口132与第一外边缘侧128横向间隔开的距离相同或大于第一开口132与第一外边缘侧128横向间隔开的距离。相同的原理可以应用于最靠近与第一外边缘侧128交叉的第三外边缘侧150的第一开口132。
参考图1D，管芯焊盘可以被布置成在每一个方向上被包封体122的上表面124包围。可以选择管芯焊盘104的暴露的外表面130与第一、第二和第三外边缘侧128、148和150中的每一个之间的横向分离距离，以维持最小爬电距离值。更一般地，可以将包封体122的下表面126上的第一开口132的几何形状和位置以及包封体122的上表面124上的暴露的管芯焊盘104的位置和几何形状选择为包括与封装的边缘侧的有利的横向偏移，以维持爬电距离，同时平衡其他设计考虑因素，例如导电性和散热能力。
参考图2，描绘了根据实施例的半导体封装100。除了开口的几何形状之外，图2的半导体封装100与图1A-1D的半导体封装基本相同。在图2的实施例中，第一和第二开口132、134具有锥形几何形状，使得第一和第二开口132、134的宽度随着远离包封体122的下表面126而减小。第三开口138(未示出)可以具有相同的锥形几何形状。开口的锥形几何形状使得能够增加包封体122的厚度，这允许通过加长外边缘侧来增加爬电距离。
根据图2的实施例，第一和第二开口132、134包括阶梯形过渡部。这些阶梯形过渡部中的每一个包括包封体122的平面表面之间的成角度的交叉部152。例如，这些成角度的交叉部152可以在平行和垂直于包封体122的下表面126的平面表面之间形成相互垂直的角。更一般地，成角度的交叉部152可以形成斜角或锐角，和/或形成成角度的交叉部152的表面可以是非平面的。通过将开口配置为包括阶梯形过渡部，增强了外部连接器的插入和牢固配合，这将在下文关于图8A-8B进一步详细描述。
参考图3，描绘了根据另一实施例的半导体封装100。在该实施例中，包封体122包括较宽部分154和设置在较宽部分154顶部的较窄部分156。管芯焊盘104的暴露外表面130与互连夹118的暴露表面之间的爬电距离包括包封体122的在较宽部分154和较窄部分156之间形成过渡部的表面中的每个表面。如图所示，这些表面包括在较宽部分154和较窄部分156之间形成阶梯形过渡部的第一表面155和第二表面157。更一般地，包封体122的在较宽部分154和较窄部分156之间形成过渡部的表面可以包括多个阶梯形过渡部、锐角或钝角等。图4A-4B的多宽度构造允许通过增加包封体122的厚度来增加爬电距离。换句话说，较窄部分156允许管芯焊盘104被移动得更远离包封体122的下表面126，从而增加了对爬电距离有贡献的表面的长度。
参考图4A-4B，描绘了根据另一实施例的半导体封装100。在该实施例中，互连夹118包括导电的第一部分158和电绝缘的第二部分160。第一部分158包括导电材料，例如Cu(铜)、Ni(镍)、NiP(镍磷)、Ag(银)、Pd(钯)、Au(金)等，以及它们的合金或组合。第二部分160包括适用于半导体应用的电绝缘材料，例如塑料、环氧树脂材料、玻璃材料、陶瓷等。根据一个实施例，第一部分158和第二部分160是预制的。例如，第一部分158可以使用标准金属加工技术由平面金属片材形成。同时，第二部分160可以是模制塑料结构。这两个预制结构可以例如使用胶水彼此附接，并且所得的互连夹118可以结合到半导体封装100中。
互连夹118的第一部分158电连接到第一端子112并包括通过第一开口132从包封体122暴露的表面。因此，互连夹118的第一部分158以与前面描述的类似方式提供外部可访问的电接触点。互连夹118的第二部分160接触第一引线106的从管芯焊盘104垂直偏移的横向跨越部，从而将互连夹118机械耦合到引线框架102。互连夹118的第二部分160用作提高互连夹118的机械稳定性的稳定特征。换句话说，通过将互连夹118锚定到引线框架102，它在包封体122的初始组装、处理和形成期间不太可能移动或旋转。第二部分160的电绝缘特性维持半导体管芯110的第一端子112和第二端子114之间的电隔离。如图4A所示，互连夹118的第二部分160可以包括跨越第二引线108中的多个第二引线的放大部分，从而增加接触表面区域并改善互连夹118和引线框架102之间的机械耦合。
参考图5A-5B，描绘了根据实施例的半导体器件组件200。半导体器件组件200包括电路载体202。电路载体202是用于机械地支撑多个电子部件(例如，半导体封装、无源件、散热器等)并且容纳这些电子部件之间的电连接的结构。电路载体202可以包括具有一个或多个结构化金属化层的电绝缘衬底，该结构化金属化层提供接合焊盘和/或互连轨。例如，电路载体202可以是印刷电路板(PCB)，其包括由诸如FR-4、CEM-1、G-10等的预浸材料形成的电绝缘衬底，并且接合焊盘和互连轨由结构化金属化层(例如铜金属化层)形成。在另一示例中，电路载体202是功率电子衬底。更具体地，电路载体202可以是包括由陶瓷形成的电绝缘衬底的DBC(直接接合铜)衬底，并且接合焊盘和导电轨是结构化金属化层(例如，铜金属化层)的部分，其通过氧化技术接合到陶瓷材料。在其他实施例中，例如，电路载体202是另一种类型的功率电子衬底，例如AMB(活性金属钎焊)衬底或IMS(绝缘金属衬底)衬底。
半导体器件组件200还包括多个连接器204。每个所述连接器204包括导电柱206和包围导电柱206的电绝缘套管208。导电柱206可以包括导电金属，例如Cu(铜)、Ni(镍)、NiP(镍磷)、Ag(银)、Pd(钯)、Au(金)等，以及它们的合金。根据实施例，导电柱206是包括Cu或由Cu形成的圆柱形柱。电绝缘套管208由适合于半导体应用的电绝缘材料形成，例如塑料、环氧树脂材料、玻璃材料、陶瓷等。导电柱206可以例如使用粘合剂牢固地附接到电绝缘套管208。替代地，可以将导电柱206松散地插入套管中。
连接器204被配置为与电路载体202的电接触点。例如，连接器204可以与来自电路载体202的接合焊盘电连接，接合焊盘又电连接到电路载体202中的导电轨。替代地，连接器204可以直接与电路载体202中的导电轨连接，并且来自电路载体202的接合焊盘被省略。根据实施例，连接器204是电路载体202的一体成型元件。这意味着导电柱206和电绝缘套管208中的一个或两者是连续结构的还形成载体的接合焊盘和/或衬底的部分。替代地，连接器204可以是分立结构，其最初被提供作为与电路载体202分开的结构并且随后例如通过焊接而被附接。
半导体器件组件200还包括如上所述的半导体封装100。虽然所描绘的实施例示出了参考图2描述的半导体封装100，但应当理解，下文将描述的附接概念对于本文描述的半导体封装100的任何实施例都是可能的。
现在将描述使用连接器204将半导体封装100附接到电路载体202。如图5A所示，半导体封装100布置在电路载体202之上，使得第一和第二开口132、134与连接器204对准。如图5B所示，半导体封装100通过将连接器204插入到半导体封装100的开口中而被布置为处于附接位置。在附接位置中，连接器204之一被插入到第一开口132中并且连接器204之一被插入到第二开口134中。连接器204中的另一个(未示出)可以按类似方式被插入到第三开口138中。
根据实施例，连接器204被配置为以形状配合的方式插入到开口中。这意味着连接器204的几何特征(例如电绝缘套管208的宽度、导电柱206的宽度以及从电绝缘套管208暴露的导电柱206的高度)与开口兼容以利用机械压力形成配对连接。可以使用诸如焊料、烧结物、导电胶等的导电粘合剂来确保导电柱206和半导体封装100的暴露的导电表面之间的机械和电可靠的接触。
根据所描绘的实施例，电绝缘套管208的宽度使得在附接位置中，电绝缘套管208与开口的最宽部分中的开口的相对面对的侧壁啮合(例如，如图5B所示)。导电柱206比开口的最窄部分更窄，并且具有从电绝缘套管208暴露的足够高度，以便到达处于附接位置的半导体封装100的暴露导电表面。半导体封装100可以在附接位置搁置在电绝缘套管208上。此外，电绝缘套管208和开口之间的形状配合连接可以形成防止导电粘合剂渗出和潜在地产生电短路的保护性密封。
图5A-5B中所示的连接器204和开口的几何形状只是其中连接器204可以插入开口中并与半导体封装100的暴露导体形成导电连接的布置的一个示例。更一般地，这两种结构可以被设计为具有任何互补的几何形状，从而可以进行按压配合连接和/或可以进行直接电连接。例如，在半导体封装100具有参考图1A-1D描述的开口的几何形状的情况下，导电柱206可以具有与开口相似或相同的几何形状。导电柱206的暴露部分的高度可以对应于开口的深度，使得包封体122的下表面126搁置在绝缘套管的上侧上。附加地或替代地，可以完全省略电绝缘套管208。
参考图6，描绘了根据另一实施例的半导体器件组件200。半导体器件组件200包括如上所述的电路载体202。另外，半导体器件组件200包括根据参考图2描述的实施例的半导体封装100。半导体器件组件200另外包括提供半导体封装100和电路载体202之间的电连接的连接器204。
在图6的实施例中，连接器204被配置为独立于电路载体202和半导体封装100的独立元件。也就是说，连接器204不是半导体封装100或电路载体202中任一个的一体形成的特征。相反，连接器204通过导电粘合剂(例如焊料、烧结物、导电胶等)附接并电连接到半导体封装100或电路载体202。连接器204包括导电柱206和电绝缘套管208，它们中的每一个可以具有与参考图5A-5B描述的连接器204相同的材料成分。与先前描述的实施例不同，图6的连接器204被设计为以与来自有引线封装的引线类似的方式与电路载体202接口连接。为此，导电柱206在下侧从电绝缘套管208暴露出来，使得它可以与电路载体202形成电接触。
参考图7A-7B，示出了插入连接器204之前和之后的半导体封装100，其中连接器204被配置作为独立元件。如图7A所示，连接器204最初被提供为与半导体封装100分开，并且连接器204的内端与开口对准。如图7B所示，连接器204插入开口中以形成电连接。导电柱206和开口的尺寸被设计成在处于附接位置的连接器204和半导体封装100之间具有形状配合的连接。连接器204中的另一个(未示出)可以按类似的方式插入到第三开口138中。
参考图8A-8B，示出了根据另一实施例的在插入被配置作为独立元件的连接器204之前和之后的半导体封装100。在图8A-8B的实施例中，连接器204具有直的构造。结果，当连接器204处于附接位置时，半导体封装100可以具有所谓的通孔式封装构造。这些类型的封装被设计成使得引线(或者在这种情况下为连接器204)可以被电路载体中相应尺寸的插座可插入地接纳。从图7A-7B和图8A-8B可以理解，通过定制连接器204可以使用相同的基本封装获得不同的封装构造。更一般地，可以获得对应于各种封装类型(例如DIP、TO、QFN、等)的封装占用空间。
参考图9A-9B，描述了根据实施例的用于形成连接器204的技术。如图9A所示，连接器204由类似于用于形成半导体封装的引线框架的金属结构300形成。该金属结构300可以由平面金属片材形成，该金属片材包括诸如Cu(铜)、Ni(镍)、NiP(镍磷)、Ag(银)、Pd(钯)、Au(金)等的导电材料，以及它们的合金或组合。例如，使用诸如冲压、冲孔等金属加工技术处理平面片材以形成从外围环302延伸出去的多个导电柱206。导电柱206与外围环302切断。如图9B所示，分离的导电柱206可以弯曲成例如九十度角。可以执行额外的切割步骤(未示出)以将连接的导电柱206彼此分离。随后，证明电绝缘套管208围绕导电柱206。虽然所描绘的实施例示出了具有与图7A-7B的实施例类似的构造的连接器204，但图9A和图9B的引线框架技术更普遍地适用于本文描述的导电柱构造中的任何一种。
参考图10，描绘了根据实施例的用于形成处于附接位置的半导体封装100和连接器204的工艺流程。在第一工艺步骤402中，提供包括管芯焊盘104和引线的引线框架102，并且将半导体管芯110安装在管芯焊盘104上。导电粘合剂(例如焊料、烧结物、导电胶等)可以提供在半导体管芯110和管芯焊盘104之间，以实现这种连接。在第二工艺步骤402中，形成互连。形成互连可以包括用于附接和电连接接合线120的引线接合步骤、以及用于附接和电连接互连夹118的夹附接步骤，所述步骤是例如通过焊接进行的。在第三工艺步骤404中，执行模制工艺以形成包封体122。这可以使用诸如注射模制、压缩模制、传递模制等的模制工艺来完成。在第四工艺步骤406中，执行系杆切割步骤。系杆切口切断了引线和引线框架102的外围环之间的连接。在第五工艺步骤408中，执行第二镀覆工艺。第二镀覆工艺在半导体封装100和连接器204的暴露金属表面上形成金属镀层。第二镀覆工艺可以使用化学镀或电镀技术来执行。金属镀层可以包括保护半导体封装100的暴露表面的金属，例如锡。在第六处理步骤410中，执行最后的标记和修整步骤。在该工艺步骤中，在封装中蚀刻标记并且可以进一步修整引线和/或将引线彼此切断。
根据另一实施例，执行工艺步骤400至步骤410以制造半导体封装。该半导体封装作为独立部件出售给用户，然后用户将单独的连接器插入封装的开口中，以将封装附接到另一个衬底，如PCB等。在这个替代工艺中，不需要步骤408-410。
诸如“之下”、“下方”、“下部”、“之上”、“上部”等的空间相对术语用于便于描述，以解释一个元件相对于第二元件的定位。这些术语旨在涵盖除了图中所描绘的取向以外的器件的不同取向。此外，诸如“第一”、“第二”等术语也用于描述各种元件、区域、部分等，并且也不旨在进行限制。相似的术语在整个描述中指代相似的元件。
如本文所用，术语“具有”、“包含”、“包括”等是开放式术语，表示存在所述元件或特征，但不排除附加元件或特征。冠词“一”和“所述”旨在包括复数和单数，除非上下文另有明确说明。
考虑到上述变化和应用范围，应当理解，本发明不受上述描述的限制，也不受附图的限制。相反，本发明仅受以下权利要求及其合法等同物的限制。

Claims (20)

1.一种半导体封装，包括：
管芯焊盘；
半导体管芯，安装在所述管芯焊盘上，并且包括背离所述管芯焊盘的第一端子和面向所述管芯焊盘并电连接到所述管芯焊盘的第二端子；
电连接到所述第一端子的互连夹；
包封所述半导体管芯和所述互连夹的电绝缘材料的包封体；以及
所述包封体中的第一开口，所述第一开口暴露所述互连夹的表面，
其中，所述包封体包括下表面、与所述下表面相对的上表面、以及在所述下表面与所述上表面之间延伸的第一外边缘侧，并且
其中，所述第一开口从所述第一外边缘侧横向偏移。
2.根据权利要求1所述的半导体封装，其中，所述管芯焊盘的外表面从所述上表面暴露，并且其中，所述第一开口从所述下表面延伸到所述包封体中。
3.根据权利要求2所述的半导体封装，其中，所述管芯焊盘的所述外表面的端部与所述第一外边缘侧横向间隔开，并且其中，所述管芯焊盘的被暴露的外表面与所述互连夹的暴露表面之间的爬电距离包括所述管芯焊盘的所述端部与所述第一外边缘侧之间沿所述上表面的距离、所述上表面和所述下表面之间沿所述第一外边缘侧的距离、以及所述第一外边缘侧和所述第一开口之间沿所述下表面的距离。
4.根据权利要求3所述的半导体封装，其中，所述爬电距离还包括所述下表面和所述互连夹之间沿所述第一开口的最靠近所述第一外边缘侧的第一侧壁的距离。
5.根据权利要求4所述的半导体封装，其中，所述第一侧壁包括一个或多个阶梯形过渡部，并且其中，所述一个或多个阶梯形过渡部中的每一个包括所述包封体的平面表面之间的成角度的交叉部。
6.根据权利要求3所述的半导体封装，其中，所述包封体包括较宽部分和在所述较宽部分的顶部上的较窄部分，并且其中，所述爬电距离包括沿所述包封体的在所述较宽部分和所述较窄部分之间形成过渡部的一个或多个表面的距离。
7.根据权利要求3所述的半导体封装，其中，所述半导体封装还包括：
第一导电引线，其连续连接到所述管芯焊盘并包括从所述管芯焊盘垂直偏移的横向跨越部；以及
所述包封体中的第二开口，所述第二开口暴露所述第一导电引线在所述横向跨越部中的表面，并且
其中，所述第二开口从所述下表面延伸到所述包封体中。
8.根据权利要求7所述的半导体封装，其中，所述包封体包括在所述下表面和所述上表面之间延伸并且与所述第一外边缘侧相对的第二外边缘侧，并且其中，所述第二开口从所述第二外边缘侧横向偏移。
9.根据权利要求8所述的半导体封装，其中，所述第一开口和所述第二开口均包括相对面对的侧壁，其中，所述第一开口和所述第二开口的侧壁包括一个或多个阶梯形过渡部，并且其中，所述一个或多个阶梯形过渡部中的每一个包括在所述包封体的平面表面之间的成角度的交叉部。
10.根据权利要求7所述的半导体封装，其中，所述互连夹包括导电的第一部分和电绝缘的第二部分，其中，所述第一部分电连接到所述第一端子并且包括被所述第一开口暴露的表面，并且其中，所述第二部分接触所述第一导电引线的所述横向跨越部。
11.根据权利要求1所述的半导体封装，其中，所述半导体管芯是分立的功率器件，并且其中，所述第一端子和所述第二端子是所述半导体管芯的电压阻挡端子。
12.一种半导体器件组件，包括：
半导体封装，包括：
管芯焊盘；
半导体管芯，安装在所述管芯焊盘上，并且包括背离所述管芯焊盘的第一端子和面向所述管芯焊盘并电连接到所述管芯焊盘的第二端子；
电连接到所述第一端子的互连夹；
包封所述半导体管芯和所述互连夹的电绝缘材料的包封体；以及
所述包封体中的第一开口，所述第一开口暴露所述互连夹的表面；以及
可附接到所述半导体封装的第一连接器，并且
其中，所述第一连接器被配置为插入到所述第一开口中并且在附接位置中与所述互连夹的从所述包封体暴露的表面形成导电连接。
13.根据权利要求12所述的半导体器件组件，其中，所述第一连接器包括导电柱，所述导电柱在所述附接位置接触所述互连夹的所述表面。
14.根据权利要求13所述的半导体器件组件，其中，所述第一连接器还包括围绕所述导电柱的电绝缘套管，并且其中，在所述附接位置中，所述电绝缘套管与所述第一开口的相对面对的侧壁啮合。
15.根据权利要求14所述的半导体器件组件，其中，所述第一开口包括相对面对的侧壁，其中，所述相对面对的侧壁包括一个或多个阶梯形过渡部，其中，所述一个或多个阶梯形过渡部中的每一个包括所述包封体的平面表面之间的成角度的交叉部，并且其中，所述电绝缘套管与所述第一开口的最宽部分中的相对面对的侧壁啮合。
16.根据权利要求12所述的半导体器件组件，其中，所述包封体包括下表面、与所述下表面相对的上表面、以及在所述下表面和所述上表面之间延伸的第一外边缘侧，其中，所述管芯焊盘的外表面从所述包封体的所述上表面暴露，并且其中，所述管芯焊盘的从所述包封体暴露的所述外表面与所述互连夹的暴露表面之间的爬电距离包括所述管芯焊盘的端部与所述第一外边缘侧之间沿所述上表面的距离、所述上表面和所述下表面之间沿所述第一外边缘侧的距离、以及所述第一外边缘侧和所述第一开口之间沿所述下表面的距离。
17.根据权利要求12所述的半导体器件组件，还包括电路载体，所述电路载体包括电绝缘衬底和结构化金属化层，并且其中，所述第一连接器在所述互连夹和所述结构化金属化层之间形成电连接。
18.根据权利要求17所述的半导体器件组件，其中，所述第一连接器是所述电路载体的一体形成的元件。
19.根据权利要求17所述的半导体器件组件，其中，所述第一连接器是与所述电路载体和所述半导体封装分开的独立元件。
20.根据权利要求12所述的半导体器件组件，其中，所述半导体封装还包括：第一导电引线，所述第一导电引线连续地连接到所述管芯焊盘并且包括从所述管芯焊盘垂直偏移的横向跨越部；以及所述包封体中的第二开口，所述第二开口暴露所述横向跨越部的表面，其中，所述半导体器件组件还包括第二连接器，所述第二连接器可附接到所述半导体封装并且包括第二导电柱，并且其中，所述第二连接器被配置为插入到所述第二开口中并在所述附接位置形成与所述第一导电引线的表面的第二导电连接。
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