CN115208843B - Cascade realization system and method for board-level domestic switch - Google Patents
Cascade realization system and method for board-level domestic switch Download PDFInfo
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- CN115208843B CN115208843B CN202210825082.8A CN202210825082A CN115208843B CN 115208843 B CN115208843 B CN 115208843B CN 202210825082 A CN202210825082 A CN 202210825082A CN 115208843 B CN115208843 B CN 115208843B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/55—Prevention, detection or correction of errors
- H04L49/552—Prevention, detection or correction of errors by ensuring the integrity of packets received through redundant connections
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L41/00—Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks
- H04L41/06—Management of faults, events, alarms or notifications
- H04L41/0654—Management of faults, events, alarms or notifications using network fault recovery
- H04L41/0663—Performing the actions predefined by failover planning, e.g. switching to standby network elements
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L41/00—Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks
- H04L41/08—Configuration management of networks or network elements
- H04L41/0803—Configuration setting
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention relates to a cascade realization system and method of a board-level domestic switch, belonging to the technical field of gigabit network communication and localization. In the invention, two exchange chips SF2507E are cascaded through a GMAC port, so that 2507E can be configured to work in an SOC mode and a non-SOC mode, and different modes correspond to different cascading implementation methods. All chips adopt autonomous and controllable domestic design, are autonomous and controllable and are not influenced by disablement; the same circuit design can realize two different cascading and redundant backup, thereby greatly improving the reliability of the system; two few port switches are cascaded to realize multi-port output, so that the cost is greatly reduced.
Description
Technical Field
The invention belongs to the technical field of gigabit network communication and localization, and particularly relates to a cascade realization system and method of a board-level domestic switch.
Background
In recent years, the development of network communication technology is increasingly common in equipment-level switch cascades. In the field of military applications, the autonomous controllable requirement is also more urgent along with the influence of external restricted service. How to design an autonomous and controllable nationwide board card capable of realizing switch cascading based on the existing environment becomes urgent.
In order to meet the requirements of localization and achieve the aim of autonomous and controllable low cost, a cascade implementation scheme of a board-level domestic switch is needed to be proposed.
Disclosure of Invention
First, the technical problem to be solved
The invention aims to solve the technical problems that: in order to overcome the defects of the existing gigabit network communication technology and the autonomous and controllable localization, specifically the problems that a core hardware chip cannot realize localization or the network communication performance is too low to realize switch cascading after localization is realized and the system requirements cannot be met, a board-level localization switch cascading implementation scheme is designed on the basis of autonomous and controllable.
(II) technical scheme
In order to solve the technical problems, the invention provides a cascade implementation system of a board-level domestic switch, which comprises a CPU, a BMC and two switch chips E1 and E2; the two exchange chips E1 and E2 are cascaded through a GMAC port, and can be configured to work in an SOC mode and a non-SOC mode, and different modes correspond to different cascading implementation methods; the CPU and the BMC are connected into the switching network through the PCIE network card and the 100M PHY respectively.
Preferably, in the SOC mode, the two switch chips E1 and E2 may independently operate, after the system is powered on, the BMC may control the two switch chips to power on, and then the two switch chips may load their respective SPI FLASH chips, perform initialization and register configuration, respectively configure GMAC ports to operate in the RGMII mode, and configure other ports to operate in the normal mode, so as to finally implement network cascading of the two switch chips.
Preferably, in the non-SOC mode, the two switch chips cannot independently operate, and after the system is powered on, the BMC controls the CPU and the two switch chips to power on, and the CPU invokes I 2 C handshake communication is carried out between the BMC and a switching chip, and the BMC calls I 2 C carrying out handshake communication with another exchange chip, then carrying out initialization configuration, and respectively calling I by CPU and BMC 2 And C, the GMAC ports which carry out handshake communication with the two exchange chips work in an RGMII mode, other ports are configured to work in a normal mode, and finally, network cascade of the two exchange chips is realized.
Preferably, the system is based on a VPX architecture, and can output 8 paths of 1000BASE-T electric ports and 2 paths of 1000BASE-X light ports.
Preferably, the system adopts a CPU chip 2K1000, adopts a 40nm technology, integrates 2 GS264 processor cores in a chip, has a main frequency of 1GHz, and integrates a shared 1MB secondary Cache, 2 x4PCIE2.0 interfaces and 2 RGMII gigabit network interfaces of a 64-bit 533MHz DDR3 controller in a chip.
Preferably, the BMC of the system is a chip GD32F450, an ARM Cortex-M432-bit processor core is adopted, and FLASH storage 3072KB and SRAM storage 512KB are integrated on a chip.
Preferably, two switching chips of the system are SF2507E, and 5+2 ports 10/100/1000M high-performance Ethernet switching is supported by adopting LQFP128-EPAD packaging, and 5 low-power consumption characteristics GigaPHY and 2 GMAC ports are integrated.
The invention also provides a cascade realization method of the board-level domestic switch realized by the system, which comprises the following steps:
step 1, powering up a system, and starting a BMC;
step 3, initializing a CPU, and judging the working mode of the exchange chip through the zone bit;
step 5, if the SOC is enabled, the system works in an SOC mode, and the steps 6 to 8 are executed; if the SOC is not enabled, the system works in a non-SOC mode, and steps 9 to 11 are executed;
step 6, the exchange chips E1 and E2 are initialized independently, the process and port configuration can be monitored through respective serial ports, and initialization configuration information is loaded from respective SPI FLASH;
step 7, the exchange chips E1 and E2 respectively configure the GMAC ports to work in RGMII mode and configure other ports to work in normal mode;
step 8, the CPU accesses E1 through the PCIE network card, and the BMC accesses E2 through the 100M PHY; the whole exchange network works normally to realize cascading;
step 9.CPU and BMC call I respectively 2 The C module is in handshake communication with the exchange chips E1 and E2 and is used for initializing and configuring the exchange chips E1 and E2;
step 10, respectively configuring GMAC2 ports of the exchange chips E1 and E2 to work in an RGMII mode, and configuring other ports to work in a normal mode;
step 11, the CPU accesses E1 through the PCIE network card, and the BMC accesses the exchange chip E2 through the 100M PHY; the whole switching network works normally to realize cascading.
The invention also provides application of the system in the technical fields of gigabit network communication and localization.
The invention also provides application of the method in the technical fields of gigabit network communication and localization.
(III) beneficial effects
In the invention, two exchange chips SF2507E are cascaded through a GMAC port, so that 2507E can be configured to work in an SOC mode and a non-SOC mode, and different modes correspond to different cascading implementation methods. All chips adopt autonomous and controllable domestic design, are autonomous and controllable and are not influenced by disablement; the same circuit design can realize two different cascading and redundant backup, thereby greatly improving the reliability of the system; two few port switches are cascaded to realize multi-port output, so that the cost is greatly reduced.
Drawings
FIG. 1 is a schematic block diagram of a switch cascade mode 1 on which the method of the present invention is based;
FIG. 2 is a schematic block diagram of a switch cascade mode 2 on which the method of the present invention is based;
fig. 3 is a logic flow diagram of a switching cascade of a method in accordance with an embodiment of the present invention.
Detailed Description
To make the objects, contents and advantages of the present invention more apparent, the following detailed description of the present invention will be given with reference to the accompanying drawings and examples.
The system and method of the present invention will be further described with reference to the schematic block diagram of switch cascading mode 1 shown in fig. 1, the schematic block diagram of switch cascading mode 2 shown in fig. 2, and the logical block diagram of switch cascading software shown in fig. 3.
The cascade implementation system of the board-level domestic switch adopts a scheme of CPU 2K1000+BMC GD32F450 +two switch chips SF2507E, and based on a VPX framework, 8 paths of 1000BASE-T electric ports and 2 paths of 1000BASE-X light ports can be output. The two exchange chips SF2507E are cascaded through a GMAC port, the SF2507E can be configured to work in an SOC mode and a non-SOC mode, and different modes correspond to different cascading implementation methods. The CPU and the BMC are connected into the switching network through the PCIE network card and the 100M PHY respectively, and in addition, under the non-SOC mode, the CPU and the BMC can also pass through I 2 And C, carrying out initialized configuration and management on the SF 2507E.
Further, the CPU chip 2K1000 adopts a 40nm technology, integrates 2 GS264 processor cores in a chip, has a main frequency of 1GHz, integrates a shared 1MB secondary Cache in the chip, and integrates 2 x4PCIE2.0 interfaces, 2 RGMII gigabit network interfaces and the like of a 64-bit 533MHz DDR3 controller.
Furthermore, the BMC chip GD32F450 adopts ARM Cortex-M432 bit processor cores, FLASH memory 3072KB and SRAM memory 512KB are integrated on the chip, IO resources and peripheral interfaces are rich, and conventional standards and advanced communication requirements can be met.
Further, the switch chip SF2507E, employing LQFP128-EPAD package, supports 5+2 ports 10/100/1000M high performance Ethernet switch, integrates 5 low power consumption characteristics GigaPHY and 2 GMAC ports.
As shown in fig. 1, the switch cascade mode 1, i.e., SOC mode. The two exchange chips SF2507E, hereinafter referred to as E1 and E2, can independently work autonomously, after the system is powered on, the BMC controls the SF2507E to be powered on, then the two SF2507E loads respective SPI FLASH chips respectively for initialization and register configuration, GMAC2 ports are configured to work in RGMII mode respectively, other ports are configured to work in normal mode, and finally network cascading of the two SF2507E is realized.
As shown in fig. 2, the switch cascade mode 2, i.e., the non-SOC mode. The two exchange chips SF2507E can not independently work, after the system is powered on, the BMC controls the CPU and the SF2507E to be powered on, and then the CPU and the BMC respectively call I 2 And C, carrying out handshake communication with the two exchange chips E1 and E2, then carrying out initialization configuration, configuring the GMAC2 port to work in an RGMII mode, configuring other ports to work in a normal mode, and finally realizing network cascade of the two SF 2507E.
In combination with the method for realizing the cascade of the board-level domestic switch realized by the system as shown in fig. 3, the cascade steps are as follows:
step 1, powering up a system, and starting a BMC;
step 3, initializing a CPU, and judging the working mode of the exchange chip through the zone bit;
step 5, if the SOC is enabled, the system works in an SOC mode, and the steps 6 to 8 are executed; if the SOC is not enabled, the system works in a non-SOC mode, and steps 9 to 11 are executed;
step 6, the exchange chips E1 and E2 are initialized independently, the process and port configuration can be monitored through respective serial ports, and initialization configuration information is loaded from respective SPI FLASH;
step 7, the exchange chips E1 and E2 respectively configure the GMAC2 port to work in RGMII mode and configure other ports to work in normal mode;
step 8, the CPU accesses E1 through the PCIE network card, and the BMC accesses E2 through the 100M PHY; the whole exchange network works normally to realize cascading;
step 9, respectively calling the IIC module by the CPU and the BMC, carrying out handshake communication with the exchange chips E1 and E2, and carrying out initialization configuration on the exchange chips E1 and E2;
step 10, respectively configuring GMAC2 ports of the exchange chips E1 and E2 to work in an RGMII mode, and configuring other ports to work in a normal mode;
step 11, the CPU accesses E1 through the PCIE network card, and the BMC accesses the exchange chip E2 through the 100M PHY; the whole switching network works normally to realize cascading.
It can be seen that the scheme of CPU 2K1000+BMC GD32F450 +two-chip exchange SF2507E is adopted, and based on the VPX architecture, 8 paths of 1000BASE-T electric ports and 2 paths of 1000BASE-X light ports can be output. Two exchange chips SF2507E are cascaded through a GMAC port, 2507E can be configured to work in an SOC mode and a non-SOC mode, and different modes correspond to different cascading implementation methods. The CPU and the BMC are connected into the switching network through the PCIE network card and the 100M PHY respectively. All chips adopt autonomous and controllable domestic design, are autonomous and controllable and are not influenced by disablement; the same circuit design can realize two different cascading and redundant backup, thereby greatly improving the reliability of the system; two few port switches are cascaded to realize multi-port output, so that the cost is greatly reduced.
The foregoing is merely a preferred embodiment of the present invention, and it should be noted that modifications and variations could be made by those skilled in the art without departing from the technical principles of the present invention, and such modifications and variations should also be regarded as being within the scope of the invention.
Claims (6)
1. The cascade implementation system of the board-level domestic switch is characterized by comprising a CPU, a BMC and two switching chips E1 and E2; the two exchange chips E1 and E2 are cascaded through a GMAC port, and can be configured to work in an SOC mode and a non-SOC mode, and different cascading implementation methods are adopted in different modes; the CPU and the BMC are connected into the switching network through the PCIE network card and the 100MPHY respectively;
in the SOC mode, the two exchange chips E1 and E2 can independently work, after the system is electrified, the BMC controls the two exchange chips to be electrified, then the two exchange chips are respectively loaded with respective SPILASH chips for initialization and register configuration, GMAC ports are respectively configured to work in RGMII mode, other ports are configured to work in normal mode, and finally network cascade of the two exchange chips is realized;
in the non-SOC mode, the two exchange chips can not independently work, after the system is electrified, the BMC controls the CPU and the two exchange chips to be electrified, and the CPU calls I 2 C handshake communication is carried out between the BMC and a switching chip, and the BMC calls I 2 C, carrying out handshake communication with another exchange chip, then carrying out initialization configuration, and respectively calling I by CPU and BMC after configuration 2 And C, the GMAC ports which carry out handshake communication with the two exchange chips work in an RGMII mode, other ports are configured to work in a normal mode, and finally, network cascade of the two exchange chips is realized.
2. The system of claim 1, wherein the system is based on a VPX architecture, and is externally capable of outputting 8-way 1000BASE-T electrical ports and 2-way 1000BASE-X optical ports.
3. The system of claim 1, wherein the system employs a CPU chip 2K1000, employs a 40nm technology, integrates 2 GS264 processor cores on-chip, has a main frequency of 1GHz, integrates a shared 1MB secondary Cache on-chip, and has a DDR3 controller 2 x4pcie2.0 interface and 2 RGMII gigabit network interfaces of 64 MHz.
4. The system of claim 1, wherein the BMC of the system is a chip GD32F450, and an ARMCortex-M432 bit processor core is adopted, and FLASH memory 3072KB and SRAM memory 512KB are integrated on a chip.
5. The system of claim 1, wherein the two switch chips of the system are SF2507E, and employ LQFP128-EPAD packaging to support 5+2 port 10/100/1000M high performance ethernet switching, integrating 5 low power consumption performance GigaPHY and 2 GMAC ports.
6. A method for implementing a cascade of board-level domestic switches implemented by the system of any one of claims 1 to 5, comprising the steps of:
step 1, powering up a system, and starting a BMC;
step 2, BMC controls the power-on time sequence of CPU and exchange chip;
step 3, initializing a CPU, and judging the working mode of the exchange chip through the zone bit;
step 4, judging whether the SOC is enabled or not;
step 5, if the SOC is enabled, the system works in an SOC mode, and the steps 6 to 8 are executed; if the SOC is not enabled, the system works in a non-SOC mode, and steps 9 to 11 are executed;
step 6, the exchange chips E1 and E2 are initialized independently, the process and port configuration can be monitored through respective serial ports, and initialization configuration information is loaded from respective SPIFASH;
step 7, the exchange chips E1 and E2 respectively configure the GMAC ports to work in RGMII mode and configure other ports to work in normal mode;
step 8, the CPU is accessed to E1 through a PCIE network card, and the BMC is accessed to E2 through 100 MPHY; the whole exchange network works normally to realize cascading;
step 9.CPU and BMC call I respectively 2 The C module is in handshake communication with the exchange chips E1 and E2 and is used for initializing and configuring the exchange chips E1 and E2;
step 10, respectively configuring GMAC2 ports of the exchange chips E1 and E2 to work in an RGMII mode, and configuring other ports to work in a normal mode;
step 11, the CPU is accessed to E1 through a PCIE network card, and the BMC is accessed to an exchange chip E2 through 100 MPHY; the whole switching network works normally to realize cascading.
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