CN115148808A - Normally-off transistor and manufacturing method thereof - Google Patents
Normally-off transistor and manufacturing method thereof Download PDFInfo
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- CN115148808A CN115148808A CN202210060089.5A CN202210060089A CN115148808A CN 115148808 A CN115148808 A CN 115148808A CN 202210060089 A CN202210060089 A CN 202210060089A CN 115148808 A CN115148808 A CN 115148808A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
- H01L29/7783—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Junction Field-Effect Transistors (AREA)
- Bipolar Transistors (AREA)
Abstract
A normally-off transistor, which is a III-V transistor, comprising: a buffer layer; a channel layer located above the channel layer; a barrier layer on the channel layer; a source, a drain and a gate on the barrier layer; and a threshold voltage adjusting layer composed of reduced transition metal oxide and located under the gate and on the barrier layer. The normally-closed transistor of the embodiment of the invention is simple to manufacture, does not need extra etching to cause surface damage, and does not need extra doping (the existing P-GaN gate needs doping).
Description
Technical Field
The present invention relates to a III-V transistor, and more particularly, to a III-V normally-off (E-mode) transistor and a method of fabricating the same.
Background
Nowadays, in the field of power electronics, the introduction of wide bandgap semiconductor devices to improve the energy efficiency of devices and modules and reduce the energy consumption has been a future trend. Particularly, gallium nitride high-frequency power devices are the most promising semiconductors beyond the limit of silicon materials in the next-generation high-power and high-frequency devices due to their excellent performance. However, to achieve high frequency and high power output, III-V transistors, such as gallium nitride (GaN) transistors, typically form two-dimensional electron clouds (2deg) such that the device is inherently normally-on (or D-mode), which makes the circuit more complex.
Fig. 1 shows a group III-V normally-on transistor, in which a normally-on transistor 1 includes a substrate 11, a buffer layer 12, a channel layer 13, a barrier (barrier) layer 14, a source 151, a drain 152, and a gate 153. The substrate 11 is, for example, a silicon, silicon-on-insulator (SOI), silicon carbide (SiC), or sapphire substrate. A buffer layer 12 of a III-V metal material is formed on the substrate 11 through a nucleation layer (not shown in fig. 1) on the substrate 11. The channel layer 13 is a III-V material for forming a channel, and is located on the buffer layer 12. A barrier layer 14 of a III-V metal material is formed over the channel layer 13. Source 151, drain 152 and gate 153 are formed on barrier layer 14, and in the horizontal direction, gate 153 is located between source 151 and drain 152. In a practical example, the buffer layer 12 and the barrier layer 14 may be aluminum gallium nitride (AlGaN) layers, and the channel layer 13 may be gallium nitride (GaN) layers. Under this structure, a continuous two-dimensional electron cloud 131 is formed in the channel layer 13 near the barrier layer 14, resulting in the normally-open transistor 1 being in a normally-open state and having a threshold voltage Vth less than zero.
In order to achieve the application goals of power saving, high speed and circuit shrink, the market requires a normally closed device. In order to realize a normally-off III-V transistor, there are three common approaches known today and are described below. The first approach is to etch the gate region of the transistor to form a recess (stress) so that the gate can be closer to the transmission channel. However, this approach requires that the stop-etch process be controlled within a few nanometers (< 10 nm) to reduce the residual etching thickness and integrate the dielectric layer to form a metal-insulator-semiconductor (MIS) structure, thereby increasing the threshold voltage (Vth) of the transistor, and thus the etching uniformity and the production stability of the gate region are very challenging. In addition, this may damage the surface of the transmission channel, resulting in a decrease of the highest current (Id) and a huge influence on the device electrical characteristics.
The second method is to introduce negatively charged fluorine ions under the gate to induce the channel under the gate to make the threshold voltage shift forward, thereby achieving the purpose of normally-off. The introduction of the fluorine ions can be achieved by plasma surface treatment or ion implantation, but it is also necessary to integrate the dielectric layer to form a metal-insulator-semiconductor (MIS) structure. Furthermore, the amount of the ions introduced into the negatively charged fluorine ions affects the threshold voltage, and the uniformity of the production is not easy to control, which affects the electrical uniformity of the transistor on the chip.
A third approach is to form a P-type III-V layer (e.g., P-GaN layer) between the gate and the barrier layer to realize a High Electron Mobility (HEMT) III-V normally-off transistor, wherein the threshold voltage Vth can reach 1.0V, for example, for a GaN transistor. The third approach can effectively turn off the transistor normally, however, when the epitaxial temperature exceeds 500 degrees celsius, magnesium hydride (Mg-H) complexes are formed in the presence of hydrogen, which results in a decrease in hole concentration and affects the threshold voltage. Accordingly, the compatibility of the P-GaN gate structure with the subsequent annealing process is very challenging, and the production cost is high.
Disclosure of Invention
According to an aspect of the present invention, there is provided a normally-off transistor, which is a III-V transistor, comprising: a buffer layer; the channel layer is positioned above the buffer layer; a barrier layer on the channel layer; a source, a drain and a gate on the barrier layer; and a threshold voltage adjustment layer, which is composed of reduced transition metal oxide and is located under the grid and on the barrier layer.
According to the above technical feature, the work function of the threshold voltage adjusting layer is 6.0 ev or more.
According to the above technical characteristics, the reduced transition metal oxide is reduced molybdenum oxide (MoO) x ,x<= 2), reduced Vanadium Oxide (VO) x ,x<= 2), reduced tungsten oxide (WO) x ,x<= 2), reduced niobium oxide (NbO) x ,x<= 2), reduced rhenium oxide (ReO) x ,x<= 2) or reduced palladium oxide (PdO) x ,x<＝2)。
According to the above technical feature, the normally-off transistor further includes: a substrate, wherein the buffer layer is located on the substrate.
According to the above technical features, the normally-closed transistor is a group III-N nitride high electron mobility transistor (HEMT transistor) or a metal oxide semiconductor field effect transistor (MOSFET transistor).
According to the above technical features, the normally-closed transistor is a GaN transistor, the channel layer has a thickness of 30 nm to 150 nm, the barrier layer has a thickness of 1 nm to 30 nm, and the threshold voltage adjustment layer has a thickness of 0.5 nm to 100 nm.
According to the technical characteristics, the buffer layer is made of AlGaN, and the chemical composition formula of AlGaN is Al y Ga 1-y N,5％<= y; the material of the barrier layer on AlGaN or AlN is AlGaN or AlN, and the chemical composition formula of AlGaN is Al x Ga 1-x N,0<＝x<＝40％。
According to the above technical features, the barrier layer is further formed with a trench (trench), wherein the threshold voltage adjustment layer is buried in the trench, and a portion of the gate is buried in the trench.
According to the above technical feature, the vertical cross section of the gate electrode is shaped like a trapezoid polygon.
According to an object of the present invention, there is provided a method of manufacturing a normally-off transistor, wherein the normally-off transistor is a III-V transistor, and the method comprises: providing a substrate, and sequentially forming a buffer layer, a channel layer and a barrier layer on the substrate; etching the barrier layer; forming a source and a drain on the barrier layer; forming a threshold voltage adjusting layer on the barrier layer, wherein the threshold voltage adjusting layer is composed of reduced transition metal oxide; and forming a gate over the threshold voltage adjustment layer.
According to the above technical features, the threshold voltage adjusting layer is formed on the barrier layer by thermal evaporation, electron gun evaporation, metal organic chemical vapor deposition, pulsed laser deposition or sputtering.
According to the above technical characteristics, sputtering is reactive sputtering in which a metal target of molybdenum, vanadium, tungsten, niobium, palladium or rhenium is mixed with an argon gas in combination with an oxygen or nitrogen dioxide gas, wherein the ratio of oxygen or nitrogen dioxide to the argon gas is 0.05 to 0.5.
In summary, the normally-off transistor of the present invention is simple to fabricate, does not require additional etching to cause surface damage, and does not require additional doping (for P-GaN gates).
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention:
FIG. 1 is a schematic cross-sectional view of a III-V normally-on transistor;
FIG. 2 is a schematic cross-sectional view of a normally-off transistor according to an embodiment of the present invention;
FIG. 3A is a schematic voltage-current curve of a normally-off transistor according to an embodiment of the present invention;
FIG. 3B is a voltage-current curve of a normally-off transistor with a P-GaN structure;
fig. 4A to 4G are schematic diagrams of steps of a method of manufacturing a normally-off transistor according to an embodiment of the present invention;
FIG. 5A is a schematic cross-sectional view of a normally-off transistor according to another embodiment of the present invention; and
fig. 5B is a schematic cross-sectional view of a normally-off transistor according to still another embodiment of the invention.
Wherein the reference numerals are as follows:
1: normally-on transistor
2. 2', 2": normally-closed transistor
11. 21: substrate
12. 22: buffer layer
13. 23: channel layer
131. 231: two-dimensional electronic cloud
14. 24, 24': barrier layer
151. 251: source electrode
152. 252: drain electrode
153. 253, 253': grid electrode
254: threshold voltage adjusting layer
Detailed Description
In order to facilitate understanding of technical features, contents, and advantages of the present invention and the effects achieved thereby, the present invention will be described in detail with reference to the accompanying drawings in the form of embodiments, wherein the drawings are used for illustration and an auxiliary description only, and are not necessarily true to scale and precise arrangement after the implementation of the present invention, and therefore, the drawings should not be read as limiting the scope of the present invention in practical implementation with the scale and arrangement relationship.
To avoid the technical drawbacks of the prior art normally-off transistor approach, the present invention proposes a novel and feasible method that does not damage the gate region, is simple to manufacture, and does not require additional surface treatment, thereby not causing surface damage and electrical degradation of the transistor channel. In the invention, a threshold voltage adjusting layer of reduced transition metal oxide is grown on the barrier layer, the threshold voltage adjusting layer is located between the barrier layer and the grid, and the work function (work function) is larger than or equal to 6 electron volts (eV),
referring to fig. 2, fig. 2 is a cross-sectional view of a normally-off transistor according to an embodiment of the invention. The normally-off transistor 2 includes a substrate 21, a buffer layer 22, a channel layer 23, a barrier layer 24, a source 251, a drain 252, a gate 253, and a threshold voltage adjustment layer 254. The substrate 21 may be a silicon, silicon carbide (SiC), silicon-on-insulator (SOI), or sapphire substrate, which may range in size from 2 inches to 8 inches, or larger, for example. A buffer layer 22 of a III-V metal material is formed on the substrate 21 through a nucleation layer (not shown in fig. 2) on the substrate 21. The channel layer 23 is a III-V material for forming a channel and is located on the buffer layer 22. A barrier layer 24 of a III-V metal material is formed over the channel layer 23.
In a practical example, the buffer layer 22 may be an aluminum gallium nitride (AlGaN) layer, the channel layer 23 may be a gallium nitride (GaN) layer, and the barrier layer 24 may be an aluminum gallium nitride (AlGaN) or aluminum nitride (AlN) layer. In the AlGaN buffer layer 22, alGaN has a chemical composition formula of Al y Ga 1-y N,5％<And (= y). The thickness of the channel layer 23 of GaN is between 30 nm and 150 nm (includingBoth endpoints of 30 nanometers and 150 nanometers). The AlGaN or AlN barrier layer 24 has a thickness of 2 to 40 nm (including two end points of 2 nm and 40 nm), and the chemical composition formula of AlGaN in the AlGaN or AlN barrier layer 24 is Al x Ga 1-x N,0<＝x<＝40％。
The source 251, the drain 252 and the gate 253 are formed on the barrier layer 24, and the gate 253 is located between the source 251 and the drain 252 in the horizontal direction, wherein the source 251, the drain 252 and the gate 253 are metal stack layers formed by at least one of titanium (Ti), aluminum (Al), nickel (Ni) and gold (Au), such as a Ni/Au metal stack. Note that the threshold voltage adjustment layer 254 is formed below the gate 253 and above the barrier layer 24, i.e., in the vertical direction, the threshold voltage adjustment layer 254 is located between the gate 253 and the barrier layer 24. The threshold voltage adjusting layer 254 is composed of a reduced transition metal oxide and has a work function higher than 6.0 electron volts, for example, reduced molybdenum oxide (MoO) x ,x<= 2), reduced Vanadium Oxide (VO) x ,x<=2, reduced tungsten oxide (WO) x ,x<= 2), reduced niobium oxide (NbO) x ,x<= 2), reduced rhenium oxide (ReO) x ,x<= 2) or reduced palladium oxide (PdO) x ,x<= 2). In a practical example, the thickness of the threshold voltage adjustment layer 254 may be between 0.5 nm and 100 nm (both endpoints of 0.5 nm and 100 nm), and preferably between 0.5 nm and 50 nm.
In this configuration, the discontinuous two-dimensional electron cloud 231 is formed in the channel layer 23 near the barrier layer 24, wherein the discontinuous portion of the two-dimensional electron cloud 231 is located below the gate 253, so that the normally-off transistor 2 is in a normally-off state and the threshold voltage Vth is greater than zero. In practical experiments, if the normally-off transistor 2 is a GaN transistor and the threshold voltage adjustment layer 254 with a work function of 6.6 ev is selected, the threshold voltage of the normally-off transistor 2 is positive 0.9 v.
It should be noted that the normally-off transistor 2 may be a HEMT transistor or a MOSFET transistor (metal oxide field effect transistor), and the invention is not limited thereto. In short, the threshold voltage adjusting layer formed by the reduced transition metal oxide is disposed between the gate and the barrier layer to generate the III-V transistor with the threshold voltage greater than 0V, which can be included in the range derived from the normally-off transistor 2. In addition, the normally-off transistor 2 may be a III-N (N is a group III nitride compound for group V) transistor, such as, but not limited to, alGaN/GaN, inAlN/GaN, alN/AlGaN, alInGaN/GaN, alInGaN/AlGaN architecture transistors.
Referring to fig. 3A and fig. 3B, fig. 3A is a voltage-current curve diagram of a normally-off transistor according to an embodiment of the invention, and fig. 3B is a voltage-current curve diagram of a P-GaN normally-off transistor. In fig. 3A and 3B, the horizontal axis represents the gate-source voltage of the transistor, and the vertical axis represents the transistor current per unit length. Comparing fig. 3A and fig. 3B, it can be seen that the threshold voltage of the normally-off transistor 2 using the threshold voltage adjustment layer 254 with the work function of 6.6 ev according to the embodiment of the present invention is higher than that of the normally-off transistor with the P-GaN gate structure, and has better current performance.
Referring to fig. 4A to 4F in sequence, fig. 4A to 4F are schematic diagrams illustrating steps of a method for manufacturing a normally-off transistor according to an embodiment of the invention. In fig. 4A, a substrate 21 is provided, a nucleation layer (not shown) is formed on the substrate 21, and then epitaxy is performed to form a buffer layer 22 on the substrate 21, wherein the buffer layer 22 is formed at a high temperature. In fig. 4B, epitaxy is performed on the buffer layer 22 to form a channel layer 23 on the buffer layer 22. In fig. 4C, epitaxy is performed on the channel layer 23 to form a barrier layer 24' on the channel layer 23.
In fig. 4D, the normally-off transistor is positioned to mesa etch the barrier layer 24', for example, using a chlorine (Cl) based process 2 ) The plasma etching system of (3). In fig. 4E, source and drain ohmic contacts are defined and formed on the barrier layer 24 by electron beam (electron beam) deposition, and a metal stack, which may be formed of at least one of titanium (Ti), aluminum (Al), nickel (Ni), and gold (Au), is annealed at high temperature to form the source 251 and drain 252 of the ohmic contacts. In thatIn fig. 4F, the threshold voltage adjustment layer 254 is formed on the barrier layer 24 by physical or chemical vapor deposition, such as thermal evaporation, electron gun evaporation, metal organic chemical vapor deposition, pulsed laser deposition, or sputtering, which is reactive sputtering in which a metal target (e.g., a metal target of molybdenum, vanadium, tungsten, niobium, palladium, rhenium) is mixed with oxygen or nitrogen dioxide gas in a ratio of 0.05 to 0.5 (including both endpoints of 0.05 and 0.5) and argon gas is mixed with argon gas. Finally, in FIG. 4G, a gate electrode 253 is defined and formed on the threshold voltage adjusting layer 254 by electron beam deposition.
Referring to fig. 2 and 5A, fig. 5A is a schematic cross-sectional view of a normally-off transistor according to another embodiment of the invention. In the embodiment of fig. 2, the barrier layer 24 does not have any trench (trench), and the threshold voltage adjustment layer 254 is formed directly on the barrier layer 24, but the invention is not limited thereto, and in fig. 5A, the barrier layer 24 of the normally-closed transistor 2' is formed with a trench, and the threshold voltage adjustment layer 254 is buried in the trench of the barrier layer 24, and a portion of the gate 253 is also buried in the trench of the barrier layer 24.
Referring to fig. 5A and 5B, fig. 5B is a schematic cross-sectional view of a normally-off transistor according to still another embodiment of the invention. The shape of the vertical cross-section of the gate 253 'of the normally-closed transistor 2 ″ of fig. 5B is different from the shape of the vertical cross-section of the gate 253 of the normally-closed transistor 2' of fig. 5A, wherein the shape of the vertical cross-section of the gate 253 'of the normally-closed transistor 2 ″ of fig. 5B is substantially a trapezoid-like polygon, and the shape of the vertical cross-section of the gate 253 of the normally-closed transistor 2' of fig. 5A is substantially a rectangle.
Specifically, the normally-off transistor of the present invention has a positive threshold voltage, is simple to fabricate, does not require additional etching to cause surface damage, and does not require additional doping (the P-GaN gate requires doping). In addition, as can be seen from fig. 3A and 3B, the normally-off transistor of the present invention has a higher threshold voltage and better current performance.
In view of the above, it will be seen that the present invention achieves the desired result in a breakthrough in the art, and is not readily perceived by those skilled in the art.
The above-described embodiments are merely illustrative of the technical spirit and features of the present invention, and the object of the present invention is to enable those skilled in the art to understand the content of the present invention and to implement the same, and the scope of the present invention should not be limited by the above-described embodiments, i.e., all equivalent changes and modifications made in the spirit of the present invention should be covered by the scope of the present invention.
Claims (12)
1. A normally-off transistor, which is a III-V transistor, comprising:
a buffer layer (22);
a channel layer (23) on the buffer layer (22);
a barrier layer (24) over the channel layer (23);
a source (251), a drain (252), and a gate (253) on the barrier layer (24); and
a threshold voltage adjustment layer (254) comprised of reduced transition metal oxide and located below the gate (253) and above the barrier layer (24).
2. The normally-off transistor of claim 1, wherein a work function of said threshold voltage adjusting layer (254) is equal to or greater than 6.0 ev.
3. The normally-closed transistor according to claim 1, wherein the reduced transition metal oxide is reduced molybdenum oxide (MoO) x ,x<= 2), reduced Vanadium Oxide (VO) x ,x<= 2), reduced tungsten oxide (WO) x ,x<= 2), reduced niobium oxide (NbO) x ,x<= 2), reduced rhenium oxide (ReO) x ,x<= 2) or reduced palladium oxide (PdO) x ,x<＝2)。
4. The normally-off transistor of claim 1, further comprising:
a substrate (21), wherein the buffer layer (22) is disposed on the substrate (21).
5. The normally-off transistor of claim 1, wherein the normally-off transistor (2) is a III-N HEMT transistor or MOSFET transistor.
6. The normally-off transistor of claim 1, wherein the normally-off transistor (2) is a GaN transistor, the channel layer (23) has a thickness of between 30 nm and 150 nm, the barrier layer (24) has a thickness of between 1 and 30 nm, and the threshold voltage adjustment layer (254) has a thickness of between 0.5 nm and 100 nm.
7. The normally-closed transistor according to claim 6, wherein the buffer layer (22) is made of AlGaN, and the chemical composition formula of AlGaN is Al y Ga 1-y N,5％<= y; and the material of the barrier layer (24) on AlGaN or AlN is AlGaN or AlN, and the chemical composition formula of AlGaN is Al x Ga 1-x N,0<＝x<＝40％。
8. The normally-closed transistor of claim 1, wherein the barrier layer (24) is further formed with a trench (trench), wherein the threshold voltage adjustment layer (254) is buried in the trench and a portion of the gate (253) is buried in the trench.
9. The normally-off transistor of claim 8, wherein the gate (253) has a vertical cross-section in the shape of a trapezoid-like polygon.
10. A method of manufacturing a normally-off transistor, wherein the normally-off transistor (2) is a III-V transistor, and the method comprises:
providing a substrate (21), and sequentially forming a buffer layer (22), a channel layer (23) and a barrier layer (24) on the substrate (21);
etching the barrier layer (24);
forming a source (251) and a drain (252) on the barrier layer (24);
forming a threshold voltage adjustment layer (254) over the barrier layer (24), wherein the threshold voltage adjustment layer (254) is comprised of a reduced transition metal oxide; and
a gate (253) is formed over the threshold voltage adjustment layer (254).
11. The method of claim 10, wherein said threshold voltage adjustment layer (254) is formed on said barrier layer (24) by thermal evaporation, electron gun evaporation, metal organic chemical vapor deposition, pulsed laser deposition, or sputtering.
12. The method of claim 11 wherein said sputtering is reactive sputtering of a metal target of molybdenum, vanadium, tungsten, niobium, palladium or rhenium mixed with oxygen or nitrogen dioxide gas in a ratio of 0.05 to 0.5 with argon.
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