CN115136323A - 晶体管、电子装置及晶体管之制造方法 - Google Patents

晶体管、电子装置及晶体管之制造方法 Download PDF

Info

Publication number
CN115136323A
CN115136323A CN202180014587.XA CN202180014587A CN115136323A CN 115136323 A CN115136323 A CN 115136323A CN 202180014587 A CN202180014587 A CN 202180014587A CN 115136323 A CN115136323 A CN 115136323A
Authority
CN
China
Prior art keywords
film
transistor
gate insulating
sio
sic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202180014587.XA
Other languages
English (en)
Inventor
中积诚
岸梅工
森诚树
藤元高佳
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nikon Corp
Toray Engineering Co Ltd
Original Assignee
Nikon Corp
Toray Engineering Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nikon Corp, Toray Engineering Co Ltd filed Critical Nikon Corp
Publication of CN115136323A publication Critical patent/CN115136323A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/36—Carbonitrides
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/42—Silicides
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/50—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02167—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon carbide not containing oxygen, e.g. SiC, SiC:H or silicon carbonitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
    • H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
    • H01L21/02211—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
    • H01L21/02304—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment formation of intermediate layers, e.g. buffer layers, layers to improve adhesion, lattice match or diffusion barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/44—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/38 - H01L21/428
    • H01L21/441—Deposition of conductive or insulating materials for electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
    • H10K10/40—Organic transistors
    • H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
    • H10K10/462—Insulated gate field-effect transistors [IGFETs]
    • H10K10/468—Insulated gate field-effect transistors [IGFETs] characterised by the gate dielectrics
    • H10K10/474—Insulated gate field-effect transistors [IGFETs] characterised by the gate dielectrics the gate dielectric comprising a multilayered structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02551—Group 12/16 materials
    • H01L21/02554—Oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02565—Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02631—Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Plasma & Fusion (AREA)
  • General Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Inorganic Chemistry (AREA)
  • Thin Film Transistor (AREA)

Abstract

本发明之晶体管具有闸极电极、闸极绝缘膜、半导体膜、源极电极及汲极电极，且上述闸极绝缘膜系交替积层SiOx膜与SiCyNz膜而成之积层膜，构成上述积层膜之膜之总数为3层以上18层以下，构成上述积层膜之各膜之膜厚为25nm以上150nm以下。

Description

晶体管、电子装置及晶体管之制造方法
技术领域
本发明系关于晶体管、电子装置及晶体管之制造方法。
本申请案主张基于2020年2月20日于日本申请之特愿2020-027134之优先权，将其内容引用于本文。
背景技术
薄膜晶体管(Thin Film Transistor，TFT)广泛用于液晶显示设备及有机电激发光(Electro Luminescence：EL)显示设备等中。
作为薄膜晶体管之半导体膜材料，氧化物半导体受到关注。其中，使用In-Ga-Zn-O(IGZO(氧化铟镓锌))等非晶质氧化物半导体之薄膜晶体管受到关注。
又，薄膜晶体管之闸极绝缘层例如专利文献1所记载，藉由CVD(Chemical VaporDeposition(化学气相沉积))法成膜。近年来，要求显示设备进一步高性能化，从而寻求一种高绝缘性能、高可靠性之薄膜晶体管。
[先前技术文献]
[专利文献]
[专利文献1]日本特开2017-107952号公报
发明内容
本发明之一态样系一种晶体管，其具有闸极电极、闸极绝缘膜、半导体膜、源极电极及汲极电极之薄膜晶体管，且上述闸极绝缘膜系交替积层SiOx膜与SiCyNz膜而成之积层膜，构成上述积层膜之膜之总数为3层以上18层以下，构成上述积层膜之各膜之膜厚为25nm以上150nm以下。
附图说明
图1系本实施形态之薄膜晶体管之一例之剖面的示意图。
图2系表示实施例1中制造之薄膜晶体管之晶体管特性之图。
图3系表示实施例2中制造之薄膜晶体管之晶体管特性之图。
图4系表示实施例3中制造之薄膜晶体管之晶体管特性之图。
图5系表示实施例4中制造之薄膜晶体管之晶体管特性之图。
图6系表示比较例1中制造之薄膜晶体管之晶体管特性之图。
图7系表示比较例2中制造之薄膜晶体管之晶体管特性之图。
具体实施方式
＜薄膜晶体管＞
本实施形态系具有闸极电极、闸极绝缘膜、半导体膜、源极电极及汲极电极之薄膜晶体管。
于本实施形态中，闸极绝缘膜系交替积层SiOx膜与SiCyNz膜而成之积层膜。
图1所示之薄膜晶体管1系形成于基板11之表面之底闸极型薄膜晶体管。薄膜晶体管1具备闸极电极12、闸极绝缘膜13、半导体膜14、源极电极15a及汲极电极15b。
以下对各构成进行说明。
《基板》
基板11之材料可例举：金属、结晶质材料、非晶质材料、导体、半导体、绝缘体、纤维、玻璃、陶瓷、沸石、塑料、热硬化性及热塑性材料。又，基板11亦可为光学组件、涂装基板、膜等。
作为结晶性材料，可例举：单晶质材料、多晶质材料或部分晶质材料。
作为热塑性材料，可例举：聚丙烯酸酯、聚碳酸酯、聚胺基甲酸酯、聚苯乙烯、纤维素聚合物、聚烯烃、聚酰胺、聚酰亚胺、聚酯、聚苯、聚乙烯、聚对苯二甲酸乙二酯、聚萘二甲酸乙二酯、聚丙烯、乙烯-乙烯基共聚物(ethylene-vinyl copolymer)、聚氯乙烯等。该等材料亦可经掺杂。
于本实施形态中，作为基板11之材质，较佳为聚酰亚胺或聚萘二甲酸乙二酯。
聚酰亚胺之软化点为290℃。聚萘二甲酸乙二酯之软化点为120℃。
于本实施形态中，基板11较佳为具有可挠性之基板。此处，可挠性系指即便对基板11施加自重程度之力亦不剪断或断裂，而可使基板11弯曲之性质。
又，因自重程度之力而弯曲之性质亦属于可挠性。于本实施形态中，基板11之可挠性根据基板11之材质、大小、厚度、或温度等环境等等发生变化。
作为具有可挠性之基板11，较佳为由树脂材料构成之基板。
再者，作为基板11，可使用1片长条状之基板。又，于本实施形态中，关于基板11，亦可设为将复数个单位基板连接而形成为长条状之构成。
《闸极电极》
闸极电极12形成于基板11之表面。闸极电极12具有导电性。作为构成闸极电极12之材料，并无特别限定。于本实施形态中，可例举：Al、Mo、Cu、Ti、Au、Ni等。
闸极电极12可为单独使用该等材料之积层体，亦可为并用2种以上该等材料之积层体。
又，亦可使用包含该等材料之合金。作为闸极电极12中使用之合金，可例举镍与磷之合金。
作为闸极电极12之形状，并无特别限定，就通道长度及通道宽度之控制性之观点而言，较佳为将薄膜晶体管之通道长度方向及通道宽度方向作为长宽之俯视方形。
作为闸极电极12之大小，只要为可确保薄膜晶体管之通道长度及通道宽度之大小即可。
此处，薄膜晶体管之通道长度方向系指薄膜晶体管之源极电极15a及汲极电极15b之对向方向。
又，该薄膜晶体管之通道宽度方向系指与薄膜晶体管之通道长度方向正交且与基板11之表面平行之方向。
闸极电极12之平均厚度可例举50nm以上500nm以下、100nm以上400nm以下。
再者，为了使闸极绝缘膜13之覆盖性变得良好，闸极电极12之厚度方向之剖面可设为朝基板11扩张之锥形。作为使闸极电极12成为锥形之情形时之倾斜角度，较佳为30°以上40°以下。
《闸极绝缘膜》
闸极绝缘膜13以覆盖闸极电极12之方式形成于基板11之一面。于本实施形态中，将基板11中之设置有闸极电极12之面设为上主面。于本实施形态中，闸极绝缘膜13系交替形成SiOx膜与SiCyNz膜而成之积层膜。
SiOx膜之x较佳为1.7以上2.4以下，更佳为1.9以上2.1以下。
SiCyNz膜之y较佳为1.0以上3.5以下，更佳为1.0以上2.0以下。SiCyNz膜之z较佳为超过0且为1.0以下，更佳为0.2以上0.7以下。
构成积层膜之膜之总数为3层以上18层以下，较佳为4层以上16层以下。于本实施形态中，构成积层膜之膜之总数可为奇数，亦可为偶数，但偶数更佳。
于构成积层膜之膜之总数为奇数之情形时，较佳为以与半导体膜14相接之层成为SiOx膜之方式形成。即，较佳为自基板11之侧依序具备SiOx膜、SiCyNz膜、SiOx膜。
积层膜较佳为于闸极电极12之上依序交替形成SiCyNz膜、SiOx膜。又，较佳为以与半导体膜14相接之层成为SiOx膜之方式形成。
即，于底闸极型之情形时，积层膜较佳为以半导体膜14侧之最上层成为SiOx膜之方式形成。
于顶闸极型之情形时，较佳为以半导体膜14侧之最下层成为SiOx膜之方式形成。
SiOx膜对于水分(H2O)或氢(H2)之类的对薄膜晶体管特性造成影响之杂质，具有阻隔性。而且，于本实施形态中，藉由制成上述层构成之积层膜，而SiOx膜之界面增加。该等杂质被截留于各界面中。因此，阻隔性提升，杂质变得不易扩散至半导体膜。其结果为，可实现可靠性较高之装置。又，藉由使积层膜具有SiCyNz膜，可制成被赋予挠性从而对应力之耐性亦得到提升之装置。
作为藉由电浆CVD装置成膜SiO2系薄膜之习知方法，就提高闸极绝缘膜之绝缘性之观点而言，可例举于200℃至300℃左右之高温下成膜之方法。又，可例举必须进行高温下之后退火处理之方法。
若如习知方法而必须进行高温下之热处理，则存在基板之材质之选择性变低，从而无法使用树脂制之基板等问题。
根据本实施形态，藉由设为交替形成SiCyNz膜与SiOx膜而成之复合绝缘膜，即使不经由高温热处理亦可于例如未达200℃之处理温度下制成高品质之闸极绝缘膜。
此外，藉由制成上述层构成之积层膜，可使闸极绝缘膜之膜应力降低。因此，亦可适用于可重复弯曲之可挠性基板。
构成积层膜之各膜之厚度分别为25nm以上150nm以下，较佳为26nm以上90nm以下，更佳为27nm以上80nm以下。
若构成积层膜之各膜之厚度为上述下限值以上，则可发挥较高之绝缘性。又，若构成积层膜之各膜之厚度为上述上限值以下，则可使迟滞变得更小或消失，从而可获得可靠性较高之装置。
于本实施形态中，积层膜之总膜厚较佳为500nm以下。又，构成积层膜之各膜之膜厚较佳为大致相同。各层之厚度只要根据膜之总数适当调整即可。于本实施形态中，构成积层膜之各膜之膜厚较佳为大致相同。
闸极绝缘膜13只要可被覆闸极电极12，则其形状无限定，例如闸极绝缘膜13亦可覆盖基板11之整面。
闸极绝缘膜为交替形成SiOx膜与SiCyNz膜而成之积层膜，构成上述积层膜之膜之总数为3层以上18层以下，构成上述积层膜之各膜之膜厚为25nm以上150nm以下，上述情况可藉由以下方法确认。
构成闸极绝缘膜之各层中之氧原子之浓度可藉由使用拉瑟福德逆散射谱法及氢前向散射分析法之组成分析进行测定。有时将拉瑟福德逆散射谱法简写为“RBS”，将氢前向散射分析法简写为“HFS”。
藉由RBS或HFS，亦可测定构成闸极绝缘膜之各层中之硅原子浓度及碳原子浓度。
作为构成闸极绝缘膜之各层中所存在之杂质之氢原子浓度可藉由HFS进行测定。
RBS系对测定对象照射高速离子(He+、H+等)，对因测定对象之原子核而受到弹性(拉塞福)散射之入射离子的一部分测定散射离子之能量及产量。散射离子之能量根据对象原子之质量及位置(深度)而有所不同。因此，根据散射离子之能量与产量，可获得测定对象之深度方向之元素组成。
藉由对测定对象照射高速离子(He+等)，测定对象中之氢因弹性反冲而朝前方散射，HFS系利用上述现象，根据反冲氢之能量与产量，获得元素之深度分布。
藉由利用RBS或HFS测定硅原子浓度及氧原子浓度，可确认SiOx膜之存在。又，藉由利用RBS或HFS测定硅原子浓度、碳原子浓度及氮原子浓度，可确认SiCyNz膜之存在。藉由确认该等之分布，可确认是否为交替形成SiOx膜与SiCyNz膜而成之积层膜。又，可确认构成积层膜之膜之总数。
《半导体膜》
作为构成半导体膜14之半导体材料，可例示载子移动率较高、相对较容易成膜之IGZO(In-Ga-Zn-O系)、透明非晶质氧化物半导体(TAOS(Transparent Amorphous OxideSemiconductor))、氧化锌(ZnO)、氧化镍(NiO)、氧化锡(SnO2)、氧化钛(TiO2)、氧化钒(VO2)、氧化铟(In2O3)、钛酸锶(SrTiO3)等。
又，可使用有机半导体作为构成半导体膜14之半导体材料。作为有机半导体材料，可使用p型半导体、富勒烯类或n型半导体。
作为p型半导体，可例举：铜酞青(CuPc)、稠五苯、红萤烯、稠四苯及P3HT(聚(3-己基噻吩-2,5-二基))(poly(3-hexylthiophene-2,5-diyl))等。
作为富勒烯类，可例举C60。
作为n型半导体，可例举PTCDI-C8H(N,N'-二辛基-3,4,9,10-苝四甲酸二酰亚胺)(N,N'-dioctyl-3,4,9,10-perylene tetracarboxylic diimide)之类的苝衍生物等。
作为构成半导体膜14之半导体材料，其中可溶性稠五苯或有机半导体聚合物可溶于有机溶剂。因此，可利用湿式步骤形成半导体膜。作为可溶性稠五苯，可例举TIPS稠五苯(6,13-双(三异丙基硅烷基乙炔基)稠五苯)(6,13-Bis(triisopropylsilylethynyl)pentacene)。
作为有机半导体聚合物，可例举聚(3-己基噻吩-2,5-二基)(P3HT)等。
作为有机溶剂，较佳使用甲苯。
《源极电极及汲极电极》
源极电极15a及汲极电极15b覆盖闸极绝缘膜13之一部分，并且于薄膜电晶体1之通道之两端与半导体膜14电性连接。
根据闸极电极12及源极电极15a间之电压以及源极电极15a及汲极电极15b间之电压，薄膜晶体管1之汲极电流流过该源极电极15a及汲极电极15b之间。
作为构成源极电极15a及汲极电极15b之材料，只要具有导电性，则并无特别限定，例如可使用与闸极电极12相同之材料。
作为源极电极15a及汲极电极15b之平均厚度，可例举100nm以上400nm以下、150nm以上300nm以下。
作为源极电极15a及汲极电极15b之对向距离，亦即薄膜晶体管1之通道长度，可例举5μm以上50μm以下、10μm以上30μm以下。
作为源极电极15a及汲极电极15b之通道宽度方向之长度，亦即薄膜晶体管1之通道宽度，可例举100μm以上300μm以下、150μm以上250μm以下。
虽对于以底闸极型薄膜晶体管作为薄膜晶体管1之情形进行了说明，亦可以顶闸极型薄膜晶体管作为其他态样。
(薄膜晶体管之特性)
作为本实施形态之薄膜晶体管之阈值电压之下限，较佳为-1V，更佳为0V。
另一方面，作为该薄膜晶体管之阈值电压之上限，较佳为3V，更佳为2V。
＜电子装置＞
本实施形态为包含上述本实施形态之薄膜晶体管之电子装置。作为电子装置，可例举液晶显示组件等显示组件。
＜薄膜晶体管之制造方法＞
本实施形态系关于薄膜晶体管之制造方法。
本实施形态之薄膜晶体管之制造方法具有成膜闸极绝缘膜之步骤，即，藉由电浆CVD法交替形成SiOx膜与SiCyNz膜，从而形成闸极绝缘膜。
闸极绝缘膜成膜步骤中之成膜温度为未达构成基板之材质之软化点之温度。
本实施形态之薄膜晶体管之制造方法较佳为依序具备闸极电极成膜步骤、闸极绝缘膜成膜步骤、半导体膜成膜步骤、源极及汲极电极成膜步骤以及退火步骤。
＜闸极电极成膜步骤＞
闸极电极成膜步骤中，于基板11之表面，成膜闸极电极12。
具体而言，首先于基板11之表面，藉由公知之方法例如溅镀法，以所需膜厚形成导电膜。作为藉由溅镀法形成导电膜时之条件，并无特别限定，例如可设为如下条件：基板温度20℃以上50℃以下、成膜功率密度3W/cm2以上4W/cm2以下、压力0.1Pa以上0.4Pa以下、载体气体Ar。
接着，对该导电膜进行图案化，藉此形成闸极电极12。作为图案化之方法，并无特别限定，例如可使用于进行光蚀刻之后进行湿式蚀刻之方法。此时，较佳为将闸极电极12之剖面蚀刻为朝基板11扩张之锥形，以便使闸极绝缘膜13之覆盖性变得良好。
＜闸极绝缘膜成膜步骤＞
闸极绝缘膜成膜步骤中，以覆盖闸极电极12之方式，于基板11之表面侧成膜闸极绝缘膜13。
具体而言，首先依序实施于基板11之上形成SiCyNz膜之SiCyNz膜形成步骤及于SiCyNz膜之上形成SiOx膜之SiOx膜形成步骤。藉由交替地反复进行SiCyNz膜形成步骤及SiOx膜形成步骤，可形成交替积层SiCyNz膜与SiOx膜而成之积层膜。
SiCyNz膜与SiOx膜例如可使用日本专利第5967983号中记载之膜形成装置，并藉由化学气相沉积(Chemical Vapor Deposition：CVD)法进行成膜。
[SiCyNz膜形成步骤]
SiCyNz膜形成步骤系使用原料气体并藉由电浆CVD法，于基板11之上形成SiCyNz膜。作为SiCyNz膜形成步骤中使用之原料气体，可例举由有机硅化合物及含有氢原子之化合物构成之原料气体。具体而言，可使用包含六甲基二硅氮烷之原料气体。六甲基二硅氮烷简写为“HMDS”。
具体而言，例如藉由向成膜室导入氢气与氩气之混合气体及HMDS等原料气体，形成SiCyNz膜。原料气体之导入速度可例举3sccm以上100sccm以下。
较佳为混合气体与原料气体同时导入至成膜室。混合气体之导入速度可例举20sccm以上1000sccm以下。
藉由一面导入混合气体及原料气体一面产生电浆，而于基板11之表面进行表面反应，从而于基板11之上形成SiCyNz膜。
[SiOx膜形成步骤]
SiOx膜成步骤系使用原料气体并藉由电浆CVD法，于SiCyNz膜之上形成SiOx。作为SiOx膜形成步骤中使用之原料气体，可例举由有机硅化合物及含有氧原子之化合物构成之原料气体。具体而言，可使用包含六甲基二硅氮烷之原料气体。将六甲基二硅氮烷记载为“HMDS”。
具体而言，例如藉由向成膜室导入氧气及HMDS等原料气体，形成SiOx膜。原料气体之导入速度可例举3sccm以上20sccm以下。
氧气之导入速度可例举20sccm以上1000sccm以下。
藉由一面导入氧气及原料气体一面产生电浆，而于SiCyNz膜之表面进行表面反应，从而于SiCyNz膜之上形成SiOx膜。
再者，亦可于基板11之上形成SiCyNz膜之前，以任意步骤于基板11之上形成基底膜。若形成基底膜，则可使闸极电极与SiCyNz膜、基板与SiCyNz膜之密接性提升。
于本实施形态中，作为可以任意步骤形成之基底膜，可例举藉由电浆CVD法形成且至少包含硅原子及氧原子之膜。基底膜较佳为氧原子之浓度为10～35元素％。
于本实施形态中，闸极绝缘膜成膜步骤于未达构成上述基板之材质之软化点之温度下实施。
具体而言，较佳为较构成上述基板之材质之软化点低20℃以上之温度，更佳为较构成上述基板之材质之软化点低40℃以上之温度。
于本实施形态中，藉由制成交替形成SiCyNz膜与SiOx膜而成之复合绝缘膜，而可进行较构成基板之材质之软化点低之低温成膜。
＜半导体膜成膜步骤＞
半导体膜成膜步骤中，于闸极绝缘膜13之表面且于闸极电极12之正上方，成膜半导体膜14。
具体而言，于闸极绝缘膜13之表面形成半导体层之后，对该半导体层进行图案化，藉此形成半导体膜14。
(半导体层之形成)
具体而言，首先例如使用公知之溅镀装置，藉由溅镀法于闸极绝缘膜13之表面形成半导体层。藉由使用溅镀法，可容易地形成成分及膜厚之面内均匀性优异之半导体层。
溅镀法中使用之溅镀靶可例举包含In、Ga、Zn之氧化物靶(IGZO靶)。
作为藉由溅镀法形成半导体层时之条件，并无特别限定，例如可设为如下条件：基板温度20℃以上50℃以下、成膜功率密度2W/cm2以上3W/cm2以下、压力0.1Pa以上0.3Pa以下、载体气体Ar。又，作为氧源，可使环境气体中含有氧。作为环境气体中之氧之含量，可设为3体积％以上5体积％以下。
再者，形成半导体层之方法并不限定于溅镀法，亦可使用涂布法等化学成膜法。
(图案化)
接着，藉由对该半导体层进行图案化，形成半导体膜14。作为半导体薄层之图案化之方法，并无特别限定，例如可使用进行光蚀刻之后进行湿式蚀刻之方法。
＜源极及汲极电极成膜步骤＞
源极及汲极电极成膜步骤中，成膜源极电极15a及汲极电极15b，上述源极电极15a及汲极电极15b于薄膜晶体管之通道两端与半导体膜14电性连接。
具体而言，首先于基板11之表面，藉由公知之方法例如溅镀法，以所需膜厚形成导电膜。作为藉由溅镀法形成导电膜时之条件，并无特别限定，例如可设为如下条件：基板温度20℃以上50℃以下、成膜功率密度3W/cm2以上4W/cm2以下、压力0.1Pa以上0.4Pa以下、载体气体Ar。
接着，对该导电膜进行图案化，藉此形成源极电极15a及汲极电极15b。作为图案化之方法，并无特别限定，例如可使用于进行光蚀刻之后进行湿式蚀刻之方法。
＜退火步骤＞
较佳为包含退火步骤，该退火步骤系于闸极绝缘膜形成之后，进而于300℃以下之温度下进行退火。
退火温度更佳为200℃以下。
退火步骤较佳为于上述温度下进行10分钟以上8小时以下。
[实施例]
以下对实施例进行进一步具体说明，但本发明并不限定于以下实施例。
＜实施例1＞
[闸极电极成膜步骤]
将膜厚125μm之聚酰亚胺膜(软化点：290℃)用作基板11。将具有与闸极电极对应之图案之金属屏蔽(厚度0.08mm之SUS430)载置于经洗净之基板11之一面，并藉由电阻加热式之真空蒸镀法成膜闸极电极12之形成材料亦即导电膜(Al膜：50nm)。藉此，于基板11上形成闸极电极12。
[闸极绝缘膜成膜步骤]
接着，以覆盖闸极电极12之方式，于基板11之上主面之整面形成闸极绝缘膜13。闸极绝缘膜13系使用化学气相沉积(Chemical Vapor Deposition：CVD)法，并藉由以下步骤交替形成SiOx膜与SiCyNz膜而成。
[闸极绝缘膜成膜步骤]
闸极绝缘膜成膜步骤系以覆盖闸极电极12之方式于基板11之表面侧成膜闸极绝缘膜13。
SiCyNz膜与SiOx膜系使用日本专利第5967983号中记载之膜形成装置，并藉由化学气相沉积(Chemical Vapor Deposition：CVD)法进行成膜。
[SiCyNz膜形成步骤]
使用原料气体并藉由电浆CVD法，于基板11之上形成SiCyNz膜。于SiCyNz膜形成步骤中，使用HMDS气体作为原料气体。
向成膜室导入氢气与氩气之混合气体及HMDS气体，形成SiCyNz膜。原料气体之导入速度设为3～100sccm。
混合气体与原料气体同时导入至成膜室。混合气体之导入速度设为20～1000sccm。
藉由一面导入混合气体及原料气体一面产生电浆，而于基板11之上形成SiCyNz膜。以电浆功率1～20kW产生电浆直至SiCyNz膜成为既定厚度。
[SiOx膜形成步骤]
使用原料气体并藉由电浆CVD法，于SiCyNz膜之上形成SiOx。于SiOx膜形成步骤中，原料气体使用HMDS气体。
藉由向成膜室导入氧气及HMDS气体，形成SiOx膜。HMDS气体之导入速度设为10～100sccm。
氧气之导入速度设为20～1000sccm。
藉由一面导入氧气及原料气体一面产生电浆，而于SiCyNz膜之上形成SiOx膜。以电浆功率1～20kW产生电浆直至SiOx膜成为既定厚度。
闸极绝缘膜成膜步骤之成膜温度设为82℃。
于实施例1中，将1组SiCyNz膜形成步骤与SiOx膜形成步骤算作1次，实施2次，从而成膜4层构成之闸极绝缘膜。此处，将1组SiCyNz膜形成步骤与SiOx膜形成步骤算作1次。
藉由RBS或HFS对实施例1中制造之4层构成之闸极绝缘膜13进行分析，结果于所形成之SiCyNz膜中，y为1.0以上2.0以下，z为0.2以上0.7以下。于所形成之SiOx膜中，x为1.9以上2.1以下。
藉由RBS或HFS对实施例1中制造之4层构成之闸极绝缘膜13进行分析，结果为自闸极电极12之侧起，膜厚100nm之SiCyNz膜、膜厚100nm之SiOx膜、膜厚100nm之SiCyNz膜、膜厚100nm之SiOx膜之4层构成。
[半导体膜成膜步骤]
接着，于上述闸极绝缘膜13之上形成半导体膜14。
作为半导体膜14之形成材料之氧化物半导体膜藉由使用InGaZnO靶[In2O3-Ga2O3-(ZnO)2]之溅镀法而形成，该InGaZnO靶中，In：Ga：Zn之原子组成比为2：2：1。再者，半导体膜14以与闸极电极12相同之方式使用金属屏蔽进行图案化。
藉此，形成厚度20nm之InGaZnO膜。
[源极电极及汲极电极成膜步骤]
接着，藉由电阻加热式之真空蒸镀法，形成源极电极15a及汲极电极15b之材料亦即导电膜(Al膜：50nm)。再者，该成膜亦透过金属屏蔽进行，而获得具有所需图案形状之源极电极15a及汲极电极15b。
源极电极15a及汲极电极15b以各自与闸极绝缘膜13及半导体膜14重迭之方式形成。
以半导体膜14之一部分于源极电极15a及汲极电极15b之间露出之方式形成。
[退火步骤]
闸极绝缘膜形成之后，进而于105℃以下之温度下实施8小时之退火步骤。藉此获得实施例1之薄膜晶体管。
＜实施例2＞
将1组SiCyNz膜形成步骤与SiOx膜形成步骤算作1次，实施4次，从而形成8层构成之闸极绝缘膜13，该8层构成之闸极绝缘膜13自闸极电极12之侧起为膜厚50nm之SiCyNz膜、膜厚50nm之SiOx膜、膜厚50nm之SiCyNz膜、膜厚50nm之SiOx膜、膜厚50nm之SiCyNz膜、膜厚50nm之SiOx膜、膜厚50nm之SiCyNz膜、膜厚50nm之SiOx膜，除此之外，以与实施例1相同之方式制造薄膜晶体管。
＜实施例3＞
将1组SiCyNz膜形成步骤与SiOx膜形成步骤算作1次，实施7次，自闸极电极12之侧起依序交替形成膜厚30nm之SiCyNz膜与膜厚30nm之SiOx膜，从而形成14层构成之闸极绝缘膜13，除此之外，以与实施例1相同之方式制造薄膜晶体管。
＜实施例4＞
依序实施SiOx膜形成步骤、SiCyNz膜形成步骤及SiOx膜形成步骤，形成3层构成之闸极绝缘膜13，该3层构成之闸极绝缘膜13自闸极电极12之侧起为膜厚50nm之SiOx膜、膜厚300nm之SiCyNz膜、膜厚50nm之SiOx膜，除此之外，以与实施例1相同之方式制造薄膜晶体管。
＜比较例1＞
形成膜厚400nm之SiCyNz膜之闸极绝缘膜13，除此之外，以与实施例1相同之方式制造薄膜晶体管。
＜比较例2＞
将1组SiCyNz膜形成步骤与SiOx膜形成步骤算作1次，实施10次，自闸极电极12之侧起依序交替形成膜厚20nm之SiCyNz膜与膜厚20nm之SiOx膜，从而形成20层构成之闸极绝缘膜13，除此之外，以与实施例1相同之方式制造薄膜晶体管。
＜薄膜晶体管特性之评价＞
对实施例1～4、比较例1～2中制造之薄膜晶体管特性进行评价。
使用半导体参数-分析仪装置(Keithley公司制造之4200A-SCS)，对实施例1～4、比较例1～2中制造之薄膜晶体管实施晶体管性能评价。
将源极-汲极电极间之电压Vds设为10V，使闸极电压自Vg＝-10V变化为+20V，对电流-电压特性(传输特性)进行评价。
将该结果示于图2～图7，实施例1～4之结果分别示于图2～5。比较例1～2之结果分别示于图6～7。
图2～7中，纵轴表示汲极电流，横轴表示闸极电压。
图2～图5所示之实施例1～4之阈值电压之下限值处于0V附近，阈值电压之负向偏移得到抑制。此外，图2～图5所示之实施例1～4获得迟滞较小之良好薄膜晶体管特性。
其中，可确认，图3所示之实施例2、图4所示之实施例3不产生迟滞，初始特性之可靠性较高。
另一方面，如图6所示，比较例1之阈值电压之下限值向负侧偏移。又，图7所示之比较例2动作不良。认为其原因在于，构成闸极绝缘膜之各层之厚度过薄。
[符号说明]
1：薄膜晶体管
11：基板
12：闸极电极
13：闸极绝缘膜
14：半导体膜(氧化物半导体)
15a：源极电极
15b：汲极电极

Claims (11)

1.一种晶体管，其具有闸极电极、闸极绝缘膜、半导体膜、源极电极及汲极电极，且
上述闸极绝缘膜系交替形成SiOx膜与SiCyNz膜而成之积层膜；
构成上述积层膜之膜之总数为3层以上18层以下；
构成上述积层膜之各膜之膜厚为25nm以上150nm以下。
2.如请求项1之晶体管，其中上述SiOx膜中之x为1.7以上2.4以下。
3.如请求项1或2之晶体管，其中上述SiCyNz膜中之y为1.0以上3.5以下，z为超过0且为1.0以下。
4.如请求项1至3中任一项之晶体管，其中上述积层膜之总膜厚为500nm以下。
5.如请求项1至4中任一项之晶体管，其中上述积层膜之与上述半导体膜相接之层为SiOx膜。
6.如请求项1至5中任一项之晶体管，其中构成上述积层膜之各膜之膜厚大致相同。
7.如请求项1至6中任一项之晶体管，其形成于具有可挠性之基板之上。
8.如请求项1至7中任一项之晶体管，其形成于由树脂材料构成之基板之上。
9.一种电子装置，其包含如请求项1至8中任一项之晶体管。
10.一种晶体管之制造方法，其制造如请求项1至8中任一项之电晶体，且
具有闸极绝缘膜形成步骤，该闸极绝缘膜形成步骤中，藉由电浆CVD法交替形成上述SiOx膜与上述SiCyNz膜，从而形成上述闸极绝缘膜；
上述闸极绝缘膜形成步骤中之成膜温度系未达构成基板之材质之软化点之温度。
11.如请求项10之晶体管之制造方法，其包含退火步骤，该退火步骤系于上述闸极绝缘膜形成步骤之后，进而于未达上述软化点之温度下进行退火。
CN202180014587.XA 2020-02-20 2021-02-17 晶体管、电子装置及晶体管之制造方法 Pending CN115136323A (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2020027134 2020-02-20
JP2020-027134 2020-02-20
PCT/JP2021/005865 WO2021166940A1 (ja) 2020-02-20 2021-02-17 トランジスタ、電子デバイス及びトランジスタの製造方法

Publications (1)

Publication Number Publication Date
CN115136323A true CN115136323A (zh) 2022-09-30

Family

ID=77391236

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202180014587.XA Pending CN115136323A (zh) 2020-02-20 2021-02-17 晶体管、电子装置及晶体管之制造方法

Country Status (6)

Country Link
US (1) US20220384657A1 (zh)
JP (1) JPWO2021166940A1 (zh)
KR (1) KR20220143028A (zh)
CN (1) CN115136323A (zh)
TW (1) TW202201781A (zh)
WO (1) WO2021166940A1 (zh)

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7417254B2 (en) * 2005-01-14 2008-08-26 Au Optronics Corp. Switching device for a pixel electrode and methods for fabricating the same
US11626279B2 (en) * 2012-03-09 2023-04-11 Versum Materials Us, Llc Compositions and methods for making silicon containing films
JP6004459B1 (ja) 2015-12-08 2016-10-05 国立大学法人 奈良先端科学技術大学院大学 薄膜トランジスタとその製造方法および前記薄膜トランジスタを有する半導体装置
KR102465559B1 (ko) * 2015-12-28 2022-11-11 엘지디스플레이 주식회사 박막 트랜지스터 기판 및 이를 이용한 표시장치
TWI697096B (zh) * 2016-06-14 2020-06-21 聯華電子股份有限公司 半導體元件及其製作方法

Also Published As

Publication number Publication date
KR20220143028A (ko) 2022-10-24
JPWO2021166940A1 (zh) 2021-08-26
US20220384657A1 (en) 2022-12-01
TW202201781A (zh) 2022-01-01
WO2021166940A1 (ja) 2021-08-26

Similar Documents

Publication Publication Date Title
US8502217B2 (en) Oxide semiconductor device including insulating layer and display apparatus using the same
US7795613B2 (en) Structure with transistor
EP2348531B1 (en) Thin film transistor and method of manufacturing the same
KR101980196B1 (ko) 트랜지스터와 그 제조방법 및 트랜지스터를 포함하는 전자소자
KR101927579B1 (ko) 전이금속 디칼코게나이드 박막 트랜지스터 및 그 제조방법
KR101694270B1 (ko) 고속전자센서용 기판 및 그 제조방법
CN104465783A (zh) 薄膜晶体管及其制造方法
US20150053970A1 (en) Display substrate including a thin film transistor and method of manufacturing the same
US9396940B2 (en) Thin film semiconductors made through low temperature process
Perez-Tomas et al. Giant bulk photovoltaic effect in solar cell architectures with ultra-wide bandgap Ga2O3 transparent conducting electrodes
KR20110072270A (ko) 트랜지스터와 그 제조방법 및 트랜지스터를 포함하는 전자소자
KR20170021560A (ko) 그래핀 아일랜드들을 포함하는 채널층을 구비한 그래핀 전자소자 및 그 제조방법
US9123588B2 (en) Thin-film transistor circuit substrate and method of manufacturing the same
TWI508171B (zh) 半導體元件結構及其製造方法
KR101587129B1 (ko) 양방향성 트랜지스터 및 그 제조방법
JP6260326B2 (ja) 薄膜トランジスタ装置及びその製造方法
CN111226307B (zh) 氧化物半导体薄膜、薄膜晶体管和溅射靶
KR101625207B1 (ko) 박막 트랜지스터 및 그 제조방법
CN115136323A (zh) 晶体管、电子装置及晶体管之制造方法
KR20100010888A (ko) Ｚｔｏ 박막의 제조방법, 이를 적용한 박막 트랜지스터 및 박막 트랜지스터의 제조방법
WO2023153509A1 (ja) 薄膜トランジスタ、および薄膜トランジスタの製造方法
KR101361440B1 (ko) 금속박막을 확산소스로 이용하는 투명 박막트랜지스터 및 그 제조방법
KR102151101B1 (ko) 산화물 반도체 박막 트랜지스터
CN208045507U (zh) 一种氧化锌薄膜晶体管
Yang et al. Solution-processable low-voltage carbon nanotube field-effect transistors with high-k relaxor ferroelectric polymer gate insulator

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination