CN115116973A - 具有多种类型底部填充物的封装件及其形成方法 - Google Patents

具有多种类型底部填充物的封装件及其形成方法 Download PDF

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CN115116973A
CN115116973A CN202210294799.4A CN202210294799A CN115116973A CN 115116973 A CN115116973 A CN 115116973A CN 202210294799 A CN202210294799 A CN 202210294799A CN 115116973 A CN115116973 A CN 115116973A
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package
underfill
package component
assembly
component
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黄冠育
郭立中
黄松辉
侯上勇
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本公开总体涉及具有多种类型底部填充物的封装件及其形成方法。一种方法包括:将第一封装组件接合在第二封装组件之上,在第一封装组件和第二封装组件之间散布第一底部填充物,并且将第三封装组件接合在第二封装组件之上。第二底部填充物在第三封装组件与第二封装组件之间。第一底部填充物和第二底部填充物是不同类型的底部填充物。

Description

具有多种类型底部填充物的封装件及其形成方法
技术领域
本公开总体涉及具有多种类型底部填充物的封装件及其形成方法。
背景技术
集成电路封装件可以具有多个封装组件(例如接合在一起的器件管芯和封装衬底),以便增加功能性和集成度。由于多个封装组件的不同材料之间的差异,可能会发生翘曲(warpage)。随着封装件的尺寸的增加,翘曲变得更加严重。
发明内容
根据本公开的一个实施例,提供了一种形成封装件的方法,包括:将第一封装组件接合在第二封装组件之上;在所述第一封装组件与所述第二封装组件之间散布第一底部填充物;以及将第三封装组件接合在所述第二封装组件之上,其中,第二底部填充物在所述第三封装组件与所述第二封装组件之间,并且其中,所述第一底部填充物和所述第二底部填充物是不同类型的底部填充物。
根据本公开的另一实施例,提供了一种封装件,包括:第一封装组件;第二封装组件,位于所述第一封装组件之上并接合到所述第一封装组件;第一底部填充物,位于所述第二封装组件与所述第一封装组件之间的第一间隙中;第三封装组件,位于所述第一封装组件之上并接合到所述第一封装组件;以及第二底部填充物,位于所述第三封装组件与所述第一封装组件之间的第二间隙中,其中,所述第一底部填充物与所述第二底部填充物为不同类型的底部填充物。
根据本公开的又一实施例,提供了一种封装件,包括:中介层;第一管芯,通过第一多个凸块接合到所述中介层;第二管芯,通过第二多个凸块接合到所述中介层;第一底部填充物层,包括在所述第一管芯和所述中介层之间的第一部分,其中,所述第一底部填充物层将所述第一多个凸块包围;第二底部填充物层,包括在所述第二管芯和所述中介层之间的第二部分,其中,所述第二底部填充物层将所述第二多个凸块包围,并且其中,所述第一底部填充物层的第一热膨胀系数(CTE)不同于所述第二底部填充物层的第二CTE;以及密封剂,将所述第一管芯和所述第二管芯密封,其中,所述密封剂进一步将所述第一底部填充物层和所述第二底部填充物层包围。
附图说明
当结合附图阅读时,从以下详细描述可以最好地理解本公开的各方面。需要注意的是,根据行业中的标准做法,各种特征并未按比例绘制。事实上,为了讨论的清楚起见,各种特征的尺寸可能被任意地放大或缩小了。
图1-图12、图13A、图13B和图13C示出了根据一些实施例的在形成包括多种类型的底部填充物的封装件中的中间阶段的截面图。
图14-图17示出了根据一些实施例的包括多种类型的底部填充物的封装件的顶视图。
图18-图23、图24A、图24B和图24C示出了根据一些实施例的在形成包括多种类型的底部填充物的封装件中的中间阶段的剖截面图。
图25-图28示出了根据一些实施例的包括多种类型的底部填充物的封装件的顶视图。
图29示出了根据一些实施例的包括多种类型的底部填充物的封装件的截面图。
图30示出了根据一些实施例的包括多种类型的底部填充物的封装件的顶视图。
图31示出了根据一些实施例的用于形成封装件的工艺流程。
具体实施方式
下面的公开内容提供了用于实现本发明的不同特征的许多不同的实施例或示例。下文描述了组件和布置的具体示例以简化本公开。当然,这些仅是示例而不意图是限制性的。例如,在下面的描述中,在第二特征上方或之上形成第一特征可以包括以直接接触的方式形成第一特征和第二特征的实施例,并且还可以包括可以在第一特征和第二特征之间形成附加特征,使得第一特征和第二特征可以不直接接触的实施例。此外,本公开可以在各个示例中重复附图标记和/或字母。该重复是出于简单和清楚的目的,并且其本身不指示所讨论的各种实施例和/或配置之间的关系。
此外,本文可以使用空间相关术语(例如,“下方”、“之下”、“低于”、“以上”、“上部”等),以易于描述图中所示的一个元件或特征相对于另外(一个或多个)元件或(一个或多个)特征的关系。这些空间相关术语意在涵盖器件在使用或操作中除了图中所示朝向之外的不同朝向。装置可以以其他方式定向(旋转90度或处于其他朝向),并且本文中所用的空间相关描述符同样可被相应地解释。
提供了一种包括多种类型的底部填充物的封装件及其形成方法。根据本公开的一些实施例,诸如器件管芯和封装件之类的多个封装组件被接合到诸如中介层(interposer)之类的另一封装组件。彼此不同的第一类型底部填充物和第二类型底部填充物被散布在多个封装组件中的第一封装组件和第二封装组件下方。不同的底部填充物可以选自非导电膜(NCF)、毛细管底部填充物、模制底部填充物等。通过采用不同类型的底部填充物,减少了封装件的翘曲,并且降低了大封装组件下方间隙的填充难度。本文讨论的实施例旨在提供示例,以使得能够制造或使用本公开的主题,并且本领域普通技术人员将容易理解在保持在不同实施例的预期范围内的同时可以进行的修改。在各种视图和说明性实施例中,相同的附图标记用于表示相同的元素。尽管方法实施例可以被讨论为以特定顺序执行,但是其他方法实施例可以以任何逻辑顺序执行。
在随后的讨论中,在各种实施例中采用多种类型的底部填充物,例如NCF、毛细管底部填充物和模制底部填充物。本文中讨论了一些类型的底部填充物的特性。这些底部填充物可以包括类似的材料。这些差异通过比较和它们的使用而更容易区分,这也将在对随后讨论的工艺的描述中讨论。根据一些实施例,每一种底部填充物(NCF、毛细管底部填充物和模制底部填充物)可以包括基材,并且可以包括或不包括可以是混合在基材中的填料颗粒的形式的填料。基材可以是树脂、环氧树脂和/或聚合物。一些示例基材包括环氧胺、环氧酐、环氧苯酚、异氰酸酯、丙烯酸酯、甲基丙烯酸酯、聚酯、聚丙烯腈等,或它们的组合。填料是非传导性的,并且可以包括二氧化硅、氧化铝、氮化硼等,它们可以是球形颗粒的形式。
根据一些实施例,毛细管底部填充物以可流动材料的形式散布,并且然后固化为固体。毛细管底部填充物中的填料颗粒也可包括不同的尺寸/直径,范围可在约0.1μm和约20μm之间。填料的体积百分比可以在0%和约80%之间的范围内。毛细管底部填充物的热膨胀系数(被称为CTE1,在低于相应玻璃化转变温度时测得)可在约15ppm和约50ppm之间的范围内。毛细管底部填充物还可以具有在约50ppm和约250ppm之间的范围内的CTE(被称为CTE2,在高于相应玻璃化转变温度时测得)。毛细管底部填充物的模量值(在低于相应玻璃化转变温度的温度下测得)可以在约2GPa和约15GPa之间的范围内,而它们的模量值(在高于相应玻璃化转变温度的温度下测得)可以在约0.01GPa和约0.5GPa之间的范围内。毛细管底部填充物的玻璃化转变温度可以在约60℃和约250℃之间的范围内。毛细管底部填充物(在25℃下)的粘度可以在约2Pa·s和约100Pa·s之间的范围内。NCF(在100℃下)的粘度可以在约0.01Pa·s和约0.3Pa·s之间的范围内。
根据一些实施例,NCF在使用时是固体膜。NCF中的填料颗粒也可以包括不同的尺寸/直径,范围可在约0.1μm和约20μm之间。填料的体积百分比可以在0%和约60%之间的范围内。NCF的CTE1值(在低于相应玻璃化转变温度时测得)可以在约20ppm和约70ppm之间的范围内。NCF还可以具有在约60ppm和约250ppm之间的范围内的CTE2值(在高于相应玻璃化转变温度时测得)。NCF的模量值(在低于相应玻璃化转变温度的温度下测得)可以在约1GPa和约10GPa之间的范围内,而它们的模量值(在高于相应玻璃化转变温度的温度下测得)可以在约0.01GPa和约0.5GPa之间的范围内。NCF的玻璃化转变温度可以在约60℃和约250℃之间的范围内。
根据一些实施例,模制底部填充物在被散布以形成封装件时是可流动的,并且然后固化为固体。模制底部填充物中的填料颗粒也可以包括不同的尺寸/直径,范围可在约0.1μm和约20μm之间。填料的体积百分比可以在0%和约97%之间的范围内。毛细管底部填充物的CTE1值(在低于相应玻璃化转变温度的温度下测得)在约3ppm和约30ppm之间的范围内。模制底部填充物也可具有在约10ppm和约100ppm之间的范围内的CTE2值(在高于相应玻璃化转变温度时测得)。模制底部填充物的模量值(在低于相应玻璃化转变温度的温度下测得)可以在约5GPa和约30GPa之间的范围内,而它们的模量值(在高于相应玻璃化转变温度的温度下测得)可以在约0.1GPa和约2GPa之间的范围内。模制底部填充物的玻璃化转变温度可以在约100℃和约250℃之间的范围内。模制底部填充物(在25℃下)的粘度可以在约50Pa·s和约1000Pa·s之间的范围内。
根据一些实施例,当毛细管底部填充物、NCF和/或模制底部填充物中的两者或更多者用于同一封装件时,尽管这些底部填充物可以(或可以不)包括相同的材料,但它们的成分(例如基材的类型、填料的类型、和/或基材与填料的比例)彼此不同。因此,不同底部填充物的特性彼此不同。例如,NCF的CTE可以大于(固化的)毛细管底部填充物的CTE,而该毛细管底部填充物的CTE又大于(固化的)模制底部填充物的CTE。模制底部填充物的粘度高于毛细管底部填充物的粘度。因此,毛细管底部填充物可以用于填充小间隙和大封装组件下方的间隙,而模制底部填充物可以用于填充较大间隙并可用于包围封装组件。由于NCF是在接合前预先施加的(如图2和图4所示),因此NCF也可以用于填充小间隙和大封装组件下方的间隙。模制底部填充物中填料的体积百分比可以大于毛细管底部填充物中填料的体积百分比,而该毛细底部填充物中填料的体积百分比也可以大于NCF中填料的体积百分比。模制底部填充物的模量值可以大于毛细管底部填充物和NCF的模量值。
图1-图12、图13A、图13B和图13C示出了根据一些实施例的在形成包括多种类型的底部填充物的封装件中的中间阶段的截面图。相应的工艺也示意性地反映在图31所示的工艺流程中。
参考图1,形成晶圆20,该晶圆包括多个封装组件22。晶圆20可以是器件晶圆、重构晶圆(其中封装有器件管芯)等。每个封装组件22可以是器件管芯,其中封装有(一个或多个)器件管芯的封装件,包括多个集成电路(或器件管芯)、集成为系统的片上系统(SoC)管芯,等等。封装组件22中的器件管芯可以是或可以包括逻辑管芯、存储器管芯、输入-输出管芯、集成无源器件(IPD)等,或其组合。例如,封装组件22中的逻辑器件管芯可以是中央处理单元(CPU)管芯、图形处理单元(GPU)管芯、移动应用管芯、微控制单元(MCU)管芯、基带(BB)管芯、应用处理器(AP)管芯,等等。封装组件22中的存储器管芯可以包括静态随机存取存储器(SRAM)管芯、动态随机存取存储器(DRAM)管芯等。例如,封装组件22可以包括高性能存储器(HBM)堆叠,这些堆叠可以包括形成管芯堆叠的存储器管芯以及密封这些存储器管芯的密封剂(例如模制化合物)。封装组件22中的器件管芯可以包括半导体衬底和互连结构。
电连接件24形成在晶圆20的顶表面。根据一些实施例,电连接件24可以包括非焊料金属特征24A和在非焊料金属特征24A之上的焊料区域24B,该非焊料金属特征可以包括金属焊盘、金属柱等。根据一些实施例,晶圆20被分割,例如沿着划片线30锯切晶圆20,以使封装组件22彼此分离。
根据替代实施例,在该阶段不分割晶圆20。而是,如图2所示,将NCF 28贴附(层压)在晶圆20之上。相应工艺在如图31所示的工艺流程200中被图示为工艺202。根据一些实施例,NCF 28是预成型的固体(且柔性)膜,例如通过将NCF 28压在晶圆20上而使其粘附到晶圆20上。电连接件24因而被压入NCF 28。根据替代实施例,NCF 28作为可流动材料被散布到晶圆20上,并且然后固化为固体膜。NCF 28可以将电连接件24嵌入其中,其中NCF 28的顶表面高于电连接件24的顶端。根据一些实施例,在贴附NCF 28之后,晶圆20与NCF 28一起被分割,例如,沿着划片线30锯切晶圆20。相应工艺在如图31所示的工艺流程200中被图示为工艺204。因此,如图1和图2所示,单个封装组件22可以包括也可以不包括NCF 28。
参照图3,提供了封装组件32,该封装组件包括其中的各封装组件34。封装组件32可以是晶圆。根据一些实施例,封装组件32包括衬底36和在衬底36之上的互连结构41。根据一些实施例,衬底36是半导体衬底,其可以是硅衬底。根据替代实施例,衬底36是电介质衬底。互连结构41可以包括多个电介质层和其中的导电特征(例如金属线、过孔(via)、接合焊盘等)。电介质层和导电特征分别使用电介质层38和接合焊盘42来表示。
根据一些实施例,封装组件32包括中介层晶圆。封装组件34因此也可被称为中介层34,其可以包括延伸到半导体衬底36中的贯穿过孔(through-via)40。根据其他实施例,另一种类型的封装组件32例如是重构晶圆、封装衬底带等。相应地,封装组件34可以是封装件、封装衬底等。在随后的讨论中,封装组件34作为示例被称为中介层,而它们也可以是其他类型。
参照图4,封装组件22被接合到封装组件34。虽然示出了一组封装组件22,但也可以贴附多组封装组件22,其中每组被贴附到相应的封装组件34。每个封装组件22可以具有上述任何结构和电路,并且同一组中的封装组件22的结构可以彼此相同或彼此不同。如上所述,每个封装组件22因此可以选自器件晶圆、封装件、IPD等。一些封装组件(表示为22A)具有贴附在其上的NCF 28。因此,封装组件22A被压靠在中介层34上,使得电连接件24穿过相应NCF 28以接触电连接件42。NCF 28可以从相应上面的封装组件22和下面的中介层34之间的间隙中挤出。根据一些实施例,一些封装组件(表示为22B)没有贴附到它们的NCF。在整个说明书中,字母A、B和C可用于区分封装组件。字母用于区分将置于封装组件下面的底部填充物的类型,而不是用于区分封装组件的类型/电路。
接合工艺包括将封装组件22A和22B贴附到相应的封装组件34之上。接下来,如图5所示,执行回流工艺以将封装组件22A和22B接合至中介层34。用于接合封装组件22A和22B的相应工艺在如图31所示的工艺流程200中被图示为工艺206和208。由于加压以及进一步由于回流工艺中的加热,NCF 28的在间隙之外的部分可能具有凸状/圆形顶表面和侧壁。
参照图6,毛细管底部填充物44被散布,并且随后固化。相应工艺在如图31所示的工艺流程200中被图示为工艺210。毛细管底部填充物44通过毛细管流向封装组件22B和中介层22之间的间隙,并且当相邻封装组件22之间的间隙较窄(例如小于约300μm)时向这些间隙爬升。当间隙较宽时,例如宽于约300μm,毛细管底部填充物44可能无法爬升到封装组件22B的顶表面。虚线44T示意性地示出了相应毛细管底部填充物44的顶表面。由于固化中发生的收缩,所以毛细管底部填充物44可以具有凹状侧壁表面,如参考图13C能够发现的那样。
图7示出了封装组件22被密封在密封剂48中。相应工艺在如图31所示的工艺流程200中被图示为工艺212。密封剂48还可以包括基材和填料。根据一些实施例,密封剂48包括模制化合物,其可以由与毛细管底部填充物44不同的材料(例如不同的基材和/或不同的填料)形成。密封剂48可以具有比毛细管底部填充物和模制底部填充物两者都更高的粘度,如前面段落所述。根据替代实施例,密封剂48由在前面的段落中讨论过的模制底部填充物形成或包括在前面的段落中讨论过的模制底部填充物,因此不再重复其材料和特性。根据毛细管底部填充物44的顶表面(如虚线顶表面44T所示)低于封装组件22的顶表面的一些实施例,密封剂48也可以对间隙的上部进行填充,这些上部高于顶表面44T。
在散布密封剂48之后,执行固化工艺以使密封剂48固化。根据替代实施例,在同一固化工艺中使毛细管底部填充物44和密封剂48固化。执行诸如化学机械抛光(CMP)工艺或机械抛光工艺之类的平坦化工艺以去除密封剂48的在封装组件22之上的多余部分。封装组件22的衬底(例如,半导体衬底)可以被暴露。所得结构称为重构晶圆50。
参照图8,重构晶圆50被放置在载体52之上。相应工艺在如图31所示的工艺流程200中被图示为工艺214。载体52可以是玻璃载体、有机载体等。离型膜54被涂覆在载体52上以将重构晶圆50贴附到载体52。离型膜54可以由基于聚合物的材料(例如光热转换(LTHC)材料)形成,其可以在随后的工艺中与载体52一起从重构晶圆50去除。根据本公开的一些实施例,离型膜54包括涂覆在载体52上的环氧基热离型材料。
图9和图10示出了背面互连结构的形成。相应工艺在如图31所示的工艺流程200中被图示为工艺216。参考图9,根据一些实施例,可以对薄衬底36执行背面研磨工艺,直到暴露贯穿过孔40。接下来,衬底36可以通过蚀刻而轻微凹陷,使得贯穿过孔40从衬底36的背面突出。然后在衬底36上沉积诸如氧化硅、氮化硅、氮氧化硅之类的电介质材料,接着进行平坦化工艺以使电介质材料和贯穿过孔40的顶表面齐平。剩余的电介质材料被示为电介质层56。
接下来,参照图10,形成(一个或多个)电介质层58和导电特征60(包括RDL和/或金属焊盘)以电连接到贯穿过孔40。根据本公开的一些实施例,电介质层58由诸如氧化硅之类的氧化物、诸如氮化硅之类的氮化物等形成。导电特征60可以通过电镀形成,或者替代地,通过镶嵌工艺形成。可以包括接合焊盘、金属柱、焊料区域和/或类似物的电连接件62形成在导电特征60之上并电连接到该导电特征。
接下来,根据一些实施例,重构晶圆50可以与载体52脱接合。相应工艺在如图31所示的工艺流程200中被图示为工艺218。根据一些实施例,诸如激光束之类的光束投射在离型膜54上,并且离型膜54在光束的热量下分解。重构晶圆50因而从载体52释放出来。在随后的工艺中,重构晶圆50可以放置在切割带(未示出)上,并且通过锯切工艺沿着划片线64进行分割,使得重构晶圆50被分离为分立封装件50’。相应工艺在如图31所示的工艺流程200中被图示为工艺220。
图11图示了封装件50’接合在另一封装组件66上。相应工艺在如图31所示的工艺流程200中被图示为工艺222。根据一些实施例,封装组件66是晶圆级组件,其中包括多个相同的封装组件66’。例如,封装组件66可以是封装衬底带,其中包括多个封装衬底66’。封装衬底66’可以是包括芯的有芯封装衬底,或者可以是其中没有芯的无芯封装衬底。根据替代实施例,封装组件66可以是另一种类型,例如中介层晶圆、重构晶圆等。封装组件66中可以没有诸如晶体管和二极管之类的有源器件。封装组件66也可以没有(或可以包括)无源器件,例如电容器、电感器、电阻器等。
封装组件66包括多个电介质层68。根据一些实施例,电介质层68可以包括干膜,例如味之素堆积膜(ABF)、聚苯并恶唑(PBO)、聚酰亚胺等。当电介质层68包括芯时,电介质材料可以包括环氧树脂、树脂、玻璃纤维、预浸料、玻璃、模制化合物、塑料、其组合和/或其多层。在电介质层68中形成再分配线70,该再分配线可包括金属线/焊盘和过孔、金属管等。再分配线70被互连以在封装组件66中形成贯穿连接。封装组件66还可包括电连接件,例如在其底部的焊料区域72。
图12示出了底部填充物74的散布。相应工艺在如图31所示的工艺流程200中被图示为工艺224。然后使底部填充物74固化。根据一些实施例,底部填充物74由与毛细管底部填充物44相同或不同的底部填充物形成。
图13A图示了热界面材料76贴附到封装件50’的顶表面上。相应工艺在如图31所示的工艺流程200中被图示为工艺226。热界面材料76可以作为可流动材料散布到封装件50’上,或者作为层压在封装件50’上的预成型膜。粘合剂环78可以散布在封装组件66’上。然后可以放置散热器80(其也可以是金属盖),并且将其贴附到热界面材料76,并且在可能的情况下将其贴附到粘合剂环78。相应工艺在如图31所示的工艺流程200中被图示为工艺228。封装组件66’可以从相应封装组件66分割出来,从而形成多个封装件82,每个封装件包括封装组件66’、接合在其上的封装件50’和散热器80。
图14示出了根据一些实施例的封装件50’的顶视图,其中,在图13A中示出了图14中的参考截面13A-13A。封装组件22A可在下方具有NCF28。封装组件22B可以是诸如SOC管芯之类的大封装组件。因此,从封装组件22B之一的一侧散布毛细管底部填充物44,并使其在封装组件22B两者下方流动。毛细管底部填充物44可以向封装组件22B与其相邻的封装组件22A之间的间隙爬升。密封剂48将封装组件22A和22B包围,并且可以进一步填充相邻的封装组件22A和22B之间的宽间隙。
图13B示出了根据一些实施例的图14中的参考截面13B-13B。如图13B所示,每个封装组件22A被图示为在下方具有NCF 28。在相邻的封装组件22A下方的NCF 28可以彼此接触或彼此间隔开。图13C示出了根据一些实施例的图14中的参考截面13C-13C。如图13A和13C所示,虚线44T表示根据一些实施例的毛细管底部填充物44的顶表面,其中密封剂48高于顶表面44T,并且与毛细管底部填充物44接触。根据替代实施例,毛细管底部填充物44延伸至与封装组件22A和22B的顶表面相同的高度,并且不存在虚线44T。
图15示出了根据本公开的替代实施例的封装件50’的顶视图。该实施例类似于图14中所示的实施例,不同之处在于,两个封装组件22B的组合占据封装件50’的中间区域,并延伸至靠近封装件50’的相反边缘。毛细管底部填充物44被散布在封装组件22B下方并将其包围。两列封装组件22A可以置于封装组件22B的相反侧上,其中NCF 28在封装组件22A下方。
图16示出了根据本公开的替代实施例的封装件50’的顶视图。该实施例类似于图15中所示的实施例,不同之处在于,四个封装组件22B的组合占据封装件50’的中间区域,并延伸至靠近封装件50’的相反边缘。毛细管底部填充物44被散布在封装组件22B下方并将其包围。两列封装组件22A在封装组件22B的相反侧上,其中NCF 28在封装组件22A下方。封装组件22B右侧的封装组件22A小于封装组件22B左侧的封装组件22A。
图17示出了根据本公开的替代实施例的封装件50’的顶视图。该实施例类似于图14中所示的实施例,不同之处在于,大封装组件22A在中间,其中NCF 28在封装组件22A下方。封装组件22B被分配为将封装组件22A包围。毛细管底部填充物44被散布在每个封装组件22B下方并将其包围。
图18-图23和图24A示出了根据本公开的一些实施例的封装件的形成中的中间阶段的截面图。这些实施例类似于前述实施例,不同之处在于,代替使用NCF与毛细管底部填充物的组合,使用毛细管底部填充物与模制底部填充物的组合,而不使用NCF。除非另有说明,否则这些实施例中的组件的材料和形成过程基本上与图1-图12、图13A、图13B和图13C所示的前述实施例中用相同附图标记表示的相同组件相同。因此,可以在针对前述实施例的讨论中找到关于图18-图23和图24A中所示的组件的形成过程和材料的细节。
图18示出了封装组件22B和22C(统称为封装组件22)接合在封装组件32之上。封装组件22B和22C中的每一者可以是器件管芯、封装件、IPD或类似物。封装组件32可以是中介层晶圆,而它也可以是另一种类型。
参照图19,毛细管底部填充物44被散布。根据一些实施例,封装组件22B与其相邻封装组件22C之间的间隙较大,和/或封装组件22C与相应下方的封装组件32部分之间的间隙较大,因此毛细管底部填充物44被限制在封装组件22B周围,并且不会流到封装组件22C下面。根据替代实施例,封装组件22B首先被接合到封装组件32,并且毛细管底部填充物44被散布,接着封装组件22C被接合到封装组件32。
图20示出了模制底部填充物84的散布,该模制底部填充物流到封装组件22C和相应下方的封装组件32部分之间的间隙。模制底部填充物84还将封装组件22B和22C包围,并且被散布得高于封装组件22B和22C的顶表面。根据一些实施例,毛细管底部填充物44在模制底部填充物84被散布之前固化。根据替代实施例,毛细管底部填充物44和模制底部填充物84在同一固化工艺中被固化。在模制底部填充物84的固化之后,执行诸如CMP工艺或机械抛光工艺之类的平坦化工艺以去除模制底部填充物84的多余部分。因而可以使封装组件22B和22C的衬底(例如半导体衬底)暴露。由此形成重构晶圆50。
参考图21,重构晶圆50通过离型膜54放置在载体52之上。根据一些实施例,可以对薄衬底36执行背面研磨工艺,直到贯穿过孔40被暴露。然后形成电介质层56,如图22所示。然后形成(一个或多个)电介质层58,并且在电介质层58中形成导电特征60(包括RDL和/或金属焊盘)以电连接到贯穿过孔40。形成电连接件62,其可包括接合焊盘、金属柱、焊料区域和/或类似物。用于形成这些特征的细节已经在前面的实施例中讨论过,在此不再重复。
接下来,重构晶圆50可以与载体52脱接合。在随后的工艺中,重构晶圆50可以放置在切割带(未示出)上,并且通过锯切工艺沿着划片线64进行分割,使得重构晶圆50被分离为分立封装件50’。
图23示出了封装件50’接合到另一封装组件66上,该封装组件66可以包括封装组件66’。接下来,如图24A所示,热界面材料76形成在封装件50’之上。粘合剂环78也被散布,并且加热环(或金属盖)80可以贴附到热界面材料76和粘合剂环78。
图25示出了根据一些实施例的封装件50’的顶视图。参考截面24A-24A、24B-24B和24C-24C分别在图24A、图24B和图24C中示出。根据一些实施例,如图25所示,两个封装组件22B彼此相邻放置,其中毛细管底部填充物44被散布在封装组件22B下方并将其包围。封装组件22C可以放置在封装组件22B周围。根据一些实施例,封装组件22B的面积很大,并且模制底部填充物难以流过封装组件22B与下方封装组件34之间的间隙。因此,使用粘度比模制底部填充物84低的毛细管底部填充物44。
图26示出了根据本公开的替代实施例的封装件50’的顶视图。该实施例类似于图25中所示的实施例,不同之处在于,两个封装组件22B的组合延伸至靠近封装件50’的相反边缘。毛细管底部填充物44被散布在封装组件22B下方并将其包围。两列封装组件22C放置在封装组件22B的相反侧上,其中模制底部填充物84在封装组件22C下方延伸,并将封装组件22B和22C包围。
图27示出了根据本公开的替代实施例的封装件50’的顶视图。该实施例类似于图26所示的实施例,不同之处在于,封装组件22B有四个,并且封装组件22B左右两侧上的封装组件22C的数量彼此不同。毛细管底部填充物44被散布在封装组件22B下方并将其包围。模制底部填充物84在封装组件22C下方延伸,并且可以延伸到每个封装组件22C的多侧。右侧列比左侧列具有更多且更小的封装组件22C。
图28示出了根据本公开的替代实施例的封装件50’的顶视图。该实施例类似于图14所示的实施例,不同之处在于,大封装组件22C在封装件50’的中间,其中模制底部填充物84延伸到封装组件22C下方。封装组件22B被分配在封装组件22C周围。毛细管底部填充物44将封装组件22B包围并延伸到这些封装组件下方。模制底部填充物84也被散布得将封装组件22C和22B包围。
图29示出了根据一些实施例的封装件82的截面图。在这些实施例中,NCF 28在封装组件22A下方,并且毛细管底部填充物44在封装组件22B下方延伸。毛细管底部填充物44还将封装组件22A和22B包围。封装件50’中可能有也可能没有模制底部填充物和/或模制化合物。
图30示出了根据一些实施例的封装件50’的顶视图。根据这些实施例,NCF、毛细管底部填充物和模制底部填充物全部都被使用。NCF 28在封装组件22A下方。毛细管底部填充物44在封装组件22B下方延伸并将其包围。模制底部填充物84在封装组件22C下方延伸,并进一步将封装组件22A、22B和22C包围。封装件50’中可能没有任何模制化合物。
在上述实施例中,根据本公开的一些实施例讨论了一些工艺和特征以形成三维(3D)封装件。还可以包括其他特征和工艺。例如,可以包括测试结构以帮助对3D封装或3DIC器件进行验证测试。测试结构可以包括例如形成在再分配层中或在衬底上的测试焊盘,该测试焊盘允许测试3D封装或3DIC、使用探针和/或探针卡等。验证测试可以对中间结构以及最终结构执行。此外,本文公开的结构和方法可以与结合了已知良好管芯的中间验证的测试方法结合使用,以增加良率并降低成本。
本公开的实施例具有一些有利特征。随着封装件和器件管芯尺寸的增加,在不引起空隙的情况下完全填充封装组件之间的间隙变得越来越困难。此外,随着底部填充物的体积和面积越来越大,由于底部填充物在固化工艺中的收缩,因此封装件的翘曲变得更加严重。本公开的实施例使用不同类型的底部填充物的混合来减少空隙问题和翘曲问题。例如,NCF在被应用时是固体,因此不会导致收缩。此外,一些底部填充物(例如毛细管底部填充物)可以首先固化以释放一些应力,随后散布和固化其他类型的底部填充物,例如模制底部填充物。
根据本公开的一些实施例,一种方法包括:将第一封装组件接合在第二封装组件之上;在第一封装组件与第二封装组件之间散布第一底部填充物;并且将第三封装组件接合在第二封装组件之上,其中,第二底部填充物在第三封装组件与第二封装组件之间,并且其中,第一底部填充物和第二底部填充物是不同类型的底部填充物。在一个实施例中,第二底部填充物包括非导电膜。在一个实施例中,该方法还包括:将非导电膜贴附在第三封装组件上,其中,在贴附非导电膜之后将第三封装组件接合到第二封装组件,并且其中,非导电膜对第三封装组件与第二封装组件之间的间隙进行填充。在一个实施例中,当贴附非导电膜时,非导电膜是固体膜。在一个实施例中,第一底部填充物包括毛细管底部填充物,并且该方法还包括:将第一封装组件和第三封装组件模制在模制化合物中。在一个实施例中,第二底部填充物包括模制底部填充物,并且该方法还包括:在第三封装组件和第二封装组件之间散布模制底部填充物。在一个实施例中,该方法还包括:将非导电膜贴附在第四封装组件之上;以及将第四封装组件接合在第二封装组件之上。在一个实施例中,第一底部填充物和第二底部填充物具有不同的热膨胀系数。在一个实施例中,第一底部填充物和第二底部填充物彼此接触。
根据本公开的一些实施例,一种封装件包括第一封装组件;在第一封装组件之上并接合到第一封装组件的第二封装组件;在第二封装组件与第一封装组件之间的第一间隙中的第一底部填充物;在第一封装组件之上并接合到第一封装组件的第三封装组件;以及在第三封装组件与第一封装组件之间的第二间隙中的第二底部填充物,其中,第一底部填充物与第二底部填充物为不同类型的底部填充物。在一个实施例中,第一底部填充物包括毛细管底部填充物或模制底部填充物,并且第二底部填充物包括非导电膜。在一个实施例中,第一底部填充物包括位于第一间隙之外的第一延伸部分,并且第一延伸部分包括凹状侧壁,并且第二底部填充物包括位于第二间隙之外的第二延伸部分,并且第二延伸部分包括凸状且弯曲的侧壁。在一个实施例中,该封装件还包括在其中模制第二封装组件和第三封装组件的模制化合物,其中,该模制化合物的成分不同于第一底部填充物和第二底部填充物的成分。在一个实施例中,该封装件还包括在第一封装组件之上并接合到第一封装组件的第四封装组件;以及在第四封装组件与第一封装组件之间的第三间隙中的第三底部填充物,其中,第一底部填充物、第二底部填充物和第三底部填充物是不同类型的底部填充物。在一个实施例中,第一底部填充物与第二底部填充物实体接触。
根据本公开的一些实施例,一种封装件包括:中介层;第一管芯,通过第一多个凸块接合到中介层;第二管芯,通过第二多个凸块接合到中介层;第一底部填充物层,包括在第一管芯和中介层之间的第一部分,其中,第一底部填充物层将第一多个凸块包围;第二底部填充物层,包括在第二管芯和中介层之间的第二部分,其中,第二底部填充物层将第二多个凸块包围,并且其中,第一底部填充物层的第一CTE不同于第二底部填充物层的第二CTE;以及密封剂,该密封剂将第一管芯和第二管芯密封,其中,密封剂进一步将第一底部填充物层和第二底部填充物层包围。在一个实施例中,密封剂包括的材料不同于第一底部填充物层和第二底部填充物层两者的材料。在一个实施例中,第一底部填充物层不同于密封剂,而第二底部填充物层与密封剂相同。在一个实施例中,第一底部填充物层和第二底部填充物层还包括彼此实体接触以形成可区分界面的延伸部分。在一个实施例中,第一底部填充物层包括凹状侧壁,并且第二底部填充物层包括凸状侧壁。
前面概述了若干实施例的特征,以使本领域技术人员可以更好地理解本公开的各方面。本领域技术人员应当理解,他们可以容易地使用本公开作为设计或修改其他工艺和结构的基础,以实现与本文介绍的实施例相同的目的和/或实现相同的优点。本领域技术人员还应该认识到,这样的等效构造并不脱离本公开的精神和范围,并且他们可以在不脱离本公开的精神和范围的情况下对本文进行各种改变、替换和变更。
示例1是一种形成封装件的方法,包括:将第一封装组件接合在第二封装组件之上;在所述第一封装组件与所述第二封装组件之间散布第一底部填充物;以及将第三封装组件接合在所述第二封装组件之上,其中,第二底部填充物在所述第三封装组件与所述第二封装组件之间,并且其中,所述第一底部填充物和所述第二底部填充物是不同类型的底部填充物。
示例2是示例1所述的方法,其中,所述第二底部填充物包括非导电膜。
示例3是示例2所述的方法,还包括:将所述非导电膜贴附在所述第三封装组件上,其中,在贴附所述非导电膜之后将所述第三封装组件接合到所述第二封装组件,并且其中,所述非导电膜对所述第三封装组件与所述第二封装组件之间的间隙进行填充。
示例4是示例3所述的方法,其中,当贴附所述非导电膜时,所述非导电膜是固体膜。
示例5是示例1所述的方法,其中,所述第一底部填充物包括毛细管底部填充物,并且所述方法还包括:将所述第一封装组件和所述第三封装组件模制在模制化合物中。
示例6是示例5所述的方法,其中,所述第二底部填充物包括模制底部填充物,并且所述方法还包括:在所述第三封装组件与所述第二封装组件之间散布所述模制底部填充物。
示例7是示例6所述的方法,还包括:将非导电膜贴附在第四封装组件上;以及将所述第四封装组件接合在所述第二封装组件之上。
示例8是示例1所述的方法,其中,所述第一底部填充物和所述第二底部填充物具有不同的热膨胀系数。
示例9是示例1所述的方法,其中,所述第一底部填充物和所述第二底部填充物彼此接触。
示例10是一种封装件,包括:第一封装组件;第二封装组件,位于所述第一封装组件之上并接合到所述第一封装组件;第一底部填充物,位于所述第二封装组件与所述第一封装组件之间的第一间隙中;第三封装组件,位于所述第一封装组件之上并接合到所述第一封装组件;以及第二底部填充物,位于所述第三封装组件与所述第一封装组件之间的第二间隙中,其中,所述第一底部填充物与所述第二底部填充物为不同类型的底部填充物。
示例11是示例10所述的封装件,其中,所述第一底部填充物包括毛细管底部填充物或模制底部填充物,并且所述第二底部填充物包括非导电膜。
示例12是示例11所述的封装件,其中,所述第一底部填充物包括位于所述第一间隙之外的第一延伸部分,并且所述第一延伸部分包括凹状侧壁,并且所述第二底部填充物包括位于所述第二间隙之外的第二延伸部分,并且所述第二延伸部分包括凸状且弯曲的侧壁。
示例13是示例11所述的封装件,还包括:在其中模制所述第二封装组件和所述第三封装组件的模制化合物,其中,所述模制化合物的成分不同于所述第一底部填充物和所述第二底部填充物的成分。
示例14是示例10所述的封装件,还包括:第四封装组件,位于所述第一封装组件之上并接合到所述第一封装组件;以及第三底部填充物,位于所述第四封装组件与所述第一封装组件之间的第三间隙中,其中,所述第一底部填充物、所述第二底部填充物和所述第三底部填充物是不同类型的底部填充物。
示例15是示例10所述的封装件,其中,所述第一底部填充物与所述第二底部填充物实体接触。
示例16是一种封装件,包括:中介层;第一管芯,通过第一多个凸块接合到所述中介层;第二管芯,通过第二多个凸块接合到所述中介层;第一底部填充物层,包括在所述第一管芯和所述中介层之间的第一部分,其中,所述第一底部填充物层将所述第一多个凸块包围;第二底部填充物层,包括在所述第二管芯和所述中介层之间的第二部分,其中,所述第二底部填充物层将所述第二多个凸块包围,并且其中,所述第一底部填充物层的第一热膨胀系数(CTE)不同于所述第二底部填充物层的第二CTE;以及密封剂,将所述第一管芯和所述第二管芯密封,其中,所述密封剂进一步将所述第一底部填充物层和所述第二底部填充物层包围。
示例17是示例16所述的封装件,其中,所述密封剂包括的材料不同于所述第一底部填充物层和所述第二底部填充物层两者的材料。
示例18是示例16所述的封装件,其中,所述第一底部填充物层不同于所述密封剂,而所述第二底部填充物层与所述密封剂相同。
示例19是示例16所述的封装件,其中,所述第一底部填充物层和所述第二底部填充物层还包括彼此实体接触以形成可区分界面的延伸部分。
示例20是示例16所述的封装件,其中,所述第一底部填充物层包括凹状侧壁,并且所述第二底部填充物层包括凸状侧壁。

Claims (10)

1.一种形成封装件的方法,包括:
将第一封装组件接合在第二封装组件之上;
在所述第一封装组件与所述第二封装组件之间散布第一底部填充物;以及
将第三封装组件接合在所述第二封装组件之上,其中,第二底部填充物在所述第三封装组件与所述第二封装组件之间,并且其中,所述第一底部填充物和所述第二底部填充物是不同类型的底部填充物。
2.根据权利要求1所述的方法,其中,所述第二底部填充物包括非导电膜。
3.根据权利要求2所述的方法,还包括:
将所述非导电膜贴附在所述第三封装组件上,其中,在贴附所述非导电膜之后将所述第三封装组件接合到所述第二封装组件,并且其中,所述非导电膜对所述第三封装组件与所述第二封装组件之间的间隙进行填充。
4.根据权利要求3所述的方法,其中,当贴附所述非导电膜时,所述非导电膜是固体膜。
5.根据权利要求1所述的方法,其中,所述第一底部填充物包括毛细管底部填充物,并且所述方法还包括:将所述第一封装组件和所述第三封装组件模制在模制化合物中。
6.根据权利要求5所述的方法,其中,所述第二底部填充物包括模制底部填充物,并且所述方法还包括:在所述第三封装组件与所述第二封装组件之间散布所述模制底部填充物。
7.根据权利要求6所述的方法,还包括:
将非导电膜贴附在第四封装组件上;以及
将所述第四封装组件接合在所述第二封装组件之上。
8.根据权利要求1所述的方法,其中,所述第一底部填充物和所述第二底部填充物具有不同的热膨胀系数。
9.一种封装件,包括:
第一封装组件;
第二封装组件,位于所述第一封装组件之上并接合到所述第一封装组件;
第一底部填充物,位于所述第二封装组件与所述第一封装组件之间的第一间隙中;
第三封装组件,位于所述第一封装组件之上并接合到所述第一封装组件;以及
第二底部填充物,位于所述第三封装组件与所述第一封装组件之间的第二间隙中,其中,所述第一底部填充物与所述第二底部填充物为不同类型的底部填充物。
10.一种封装件,包括:
中介层;
第一管芯,通过第一多个凸块接合到所述中介层;
第二管芯,通过第二多个凸块接合到所述中介层;
第一底部填充物层,包括在所述第一管芯和所述中介层之间的第一部分,其中,所述第一底部填充物层将所述第一多个凸块包围;
第二底部填充物层,包括在所述第二管芯和所述中介层之间的第二部分,其中,所述第二底部填充物层将所述第二多个凸块包围,并且其中,所述第一底部填充物层的第一热膨胀系数(CTE)不同于所述第二底部填充物层的第二CTE;以及
密封剂,将所述第一管芯和所述第二管芯密封,其中,所述密封剂进一步将所述第一底部填充物层和所述第二底部填充物层包围。
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Families Citing this family (2)

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Publication number Priority date Publication date Assignee Title
US11837586B2 (en) * 2021-02-26 2023-12-05 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of forming thereof
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Family Cites Families (66)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000286302A (ja) * 1999-03-31 2000-10-13 Towa Corp 半導体チップ組立方法及び組立装置
US6546620B1 (en) * 2000-06-29 2003-04-15 Amkor Technology, Inc. Flip chip integrated circuit and passive chip component package fabrication method
US6356453B1 (en) * 2000-06-29 2002-03-12 Amkor Technology, Inc. Electronic package having flip chip integrated circuit and passive chip component
US6833628B2 (en) 2002-12-17 2004-12-21 Delphi Technologies, Inc. Mutli-chip module
KR20050001159A (ko) 2003-06-27 2005-01-06 삼성전자주식회사 복수개의 플립 칩들을 갖는 멀티칩 패키지 및 그 제조방법
US20050196907A1 (en) * 2003-09-19 2005-09-08 Glenn Ratificar Underfill system for die-over-die arrangements
US7119449B2 (en) 2003-12-08 2006-10-10 Delphi Technologies, Inc. Enhancement of underfill physical properties by the addition of thermotropic cellulose
TWI301657B (en) * 2006-01-27 2008-10-01 Siliconware Precision Industries Co Ltd Flip-chip semiconductor device and method for fabricating the same
US7656042B2 (en) * 2006-03-29 2010-02-02 Taiwan Semiconductor Manufacturing Co., Ltd. Stratified underfill in an IC package
US7915080B2 (en) * 2008-12-19 2011-03-29 Texas Instruments Incorporated Bonding IC die to TSV wafers
US8797057B2 (en) 2011-02-11 2014-08-05 Taiwan Semiconductor Manufacturing Company, Ltd. Testing of semiconductor chips with microbumps
US8779599B2 (en) * 2011-11-16 2014-07-15 Taiwan Semiconductor Manufacturing Company, Ltd. Packages including active dies and dummy dies and methods for forming the same
KR101274460B1 (ko) * 2011-11-22 2013-06-18 삼성전기주식회사 반도체 패키지 및 그 제조 방법
US9006004B2 (en) * 2012-03-23 2015-04-14 Taiwan Semiconductor Manufacturing Company, Ltd. Probing chips during package formation
US9443783B2 (en) 2012-06-27 2016-09-13 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC stacking device and method of manufacture
US9136159B2 (en) * 2012-11-15 2015-09-15 Amkor Technology, Inc. Method and system for a semiconductor for device package with a die-to-packaging substrate first bond
US9040349B2 (en) 2012-11-15 2015-05-26 Amkor Technology, Inc. Method and system for a semiconductor device package with a die to interposer wafer first bond
US9299649B2 (en) 2013-02-08 2016-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. 3D packages and methods for forming the same
US8993380B2 (en) 2013-03-08 2015-03-31 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for 3D IC package
JP6069142B2 (ja) * 2013-09-11 2017-02-01 デクセリアルズ株式会社 アンダーフィル材、及びこれを用いた半導体装置の製造方法
US9530762B2 (en) 2014-01-10 2016-12-27 Taiwan Semiconductor Manufacturing Company Limited Semiconductor package, semiconductor device and method of forming the same
US9281254B2 (en) 2014-02-13 2016-03-08 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming integrated circuit package
US9425126B2 (en) 2014-05-29 2016-08-23 Taiwan Semiconductor Manufacturing Company, Ltd. Dummy structure for chip-on-wafer-on-substrate
US9496189B2 (en) 2014-06-13 2016-11-15 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked semiconductor devices and methods of forming same
US9349614B2 (en) 2014-08-06 2016-05-24 Invensas Corporation Device and method for localized underfill
KR20160019252A (ko) * 2014-08-11 2016-02-19 앰코 테크놀로지 코리아 주식회사 반도체 디바이스의 제조 방법
US9899238B2 (en) * 2014-12-18 2018-02-20 Intel Corporation Low cost package warpage solution
US9461018B1 (en) 2015-04-17 2016-10-04 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out PoP structure with inconsecutive polymer layer
US9666502B2 (en) 2015-04-17 2017-05-30 Taiwan Semiconductor Manufacturing Company, Ltd. Discrete polymer in fan-out packages
US9735131B2 (en) 2015-11-10 2017-08-15 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-stack package-on-package structures
US10872879B2 (en) * 2015-11-12 2020-12-22 Amkor Technology Singapore Holding Pte. Ltd. Semiconductor package and manufacturing method thereof
US10163867B2 (en) * 2015-11-12 2018-12-25 Amkor Technology, Inc. Semiconductor package and manufacturing method thereof
JP2017112241A (ja) 2015-12-17 2017-06-22 ルネサスエレクトロニクス株式会社 半導体装置
US10026716B2 (en) 2016-04-15 2018-07-17 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC formation with dies bonded to formed RDLs
US10535632B2 (en) * 2016-09-02 2020-01-14 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package structure and method of manufacturing the same
US10141253B2 (en) * 2016-11-14 2018-11-27 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
US10636715B2 (en) * 2017-11-06 2020-04-28 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package and method of fabricating the same
KR102467030B1 (ko) * 2018-01-17 2022-11-14 삼성전자주식회사 반도체 패키지 및 그 패키지를 포함한 반도체 장치
KR102397902B1 (ko) 2018-01-29 2022-05-13 삼성전자주식회사 반도체 패키지
JP2019153767A (ja) * 2018-02-28 2019-09-12 日立化成株式会社 半導体装置及びその製造方法
KR20190125888A (ko) * 2018-04-30 2019-11-07 에스케이하이닉스 주식회사 반도체 다이들을 스택하는 방법
KR102607055B1 (ko) * 2018-05-11 2023-11-30 삼성전자주식회사 반도체 패키지 시스템
US11469206B2 (en) * 2018-06-14 2022-10-11 Intel Corporation Microelectronic assemblies
US11075133B2 (en) 2018-06-29 2021-07-27 Taiwan Semiconductor Manufacturing Company, Ltd. Underfill structure for semiconductor packages and methods of forming the same
KR102566974B1 (ko) 2018-07-11 2023-08-16 삼성전자주식회사 반도체 패키지
US11984439B2 (en) * 2018-09-14 2024-05-14 Intel Corporation Microelectronic assemblies
US11328936B2 (en) * 2018-12-21 2022-05-10 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and formation method of package structure with underfill
KR102480379B1 (ko) 2019-01-29 2022-12-23 주식회사 엘지화학 반도체 패키지의 제조방법
KR102677834B1 (ko) * 2019-03-26 2024-06-21 삼성전자주식회사 반도체 패키지
KR102661833B1 (ko) * 2019-04-17 2024-05-02 삼성전자주식회사 반도체 패키지
KR20200140654A (ko) * 2019-06-07 2020-12-16 삼성전자주식회사 반도체 패키지 및 그 제조 방법
US11735533B2 (en) 2019-06-11 2023-08-22 Intel Corporation Heterogeneous nested interposer package for IC chips
US11688634B2 (en) * 2019-07-30 2023-06-27 Intel Corporation Trenches in wafer level packages for improvements in warpage reliability and thermals
US11587905B2 (en) * 2019-10-09 2023-02-21 Industrial Technology Research Institute Multi-chip package and manufacturing method thereof
US20210125946A1 (en) * 2019-10-24 2021-04-29 Advanced Semiconductor Engineering, Inc. Electronic device package and method for manufacturing the same
KR102715474B1 (ko) * 2019-11-15 2024-10-11 삼성전자주식회사 언더 필 물질 층을 포함하는 반도체 패키지 및 그 형성방법
US11545438B2 (en) * 2019-12-25 2023-01-03 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages and methods of forming the same
US11671010B2 (en) * 2020-02-07 2023-06-06 Taiwan Semiconductor Manufacturing Company, Ltd. Power delivery for multi-chip-package using in-package voltage regulator
US11658094B2 (en) * 2020-02-13 2023-05-23 Samsung Electronics Co., Ltd. Semiconductor package
KR102707682B1 (ko) * 2020-03-19 2024-09-19 삼성전자주식회사 반도체 모듈
US11515229B2 (en) * 2020-03-31 2022-11-29 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and manufacturing method thereof
KR20210138223A (ko) * 2020-05-12 2021-11-19 삼성전자주식회사 반도체 패키지
TW202147539A (zh) * 2020-06-03 2021-12-16 南韓商三星電子股份有限公司 半導體封裝
KR20220007192A (ko) * 2020-07-10 2022-01-18 삼성전자주식회사 언더필이 구비된 반도체 패키지 및 이의 제조 방법
KR20220007340A (ko) * 2020-07-10 2022-01-18 삼성전자주식회사 언더필을 갖는 패키지 구조물
US11404379B2 (en) * 2020-11-17 2022-08-02 International Business Machines Corporation Structure and method for bridge chip assembly with capillary underfill

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