CN115116853A - Method for reducing breakdown leakage current of radiation-resistant bar-shaped grid MOSFET - Google Patents
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- 238000000034 method Methods 0.000 title claims abstract description 26
- 230000015556 catabolic process Effects 0.000 title claims abstract description 21
- 230000005855 radiation Effects 0.000 title claims abstract description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 28
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 238000001259 photo etching Methods 0.000 claims abstract description 18
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 14
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 14
- 238000004519 manufacturing process Methods 0.000 claims abstract description 12
- 230000003471 anti-radiation Effects 0.000 claims abstract description 10
- 229910052681 coesite Inorganic materials 0.000 claims abstract description 9
- 238000005260 corrosion Methods 0.000 claims abstract description 9
- 230000007797 corrosion Effects 0.000 claims abstract description 9
- 229910052906 cristobalite Inorganic materials 0.000 claims abstract description 9
- 229910052682 stishovite Inorganic materials 0.000 claims abstract description 9
- 229910052905 tridymite Inorganic materials 0.000 claims abstract description 9
- 229910052751 metal Inorganic materials 0.000 claims abstract description 7
- 239000002184 metal Substances 0.000 claims abstract description 7
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 6
- 230000003647 oxidation Effects 0.000 claims abstract description 6
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 6
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 6
- 239000001301 oxygen Substances 0.000 claims abstract description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 6
- 230000005669 field effect Effects 0.000 claims abstract description 5
- 239000004065 semiconductor Substances 0.000 claims abstract description 5
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 4
- 150000004706 metal oxides Chemical class 0.000 claims abstract description 4
- 239000012535 impurity Substances 0.000 claims description 14
- 238000000137 annealing Methods 0.000 claims description 9
- 239000000463 material Substances 0.000 claims description 8
- 229910052785 arsenic Inorganic materials 0.000 claims description 6
- 238000002513 implantation Methods 0.000 claims description 6
- 238000002347 injection Methods 0.000 claims description 4
- 239000007924 injection Substances 0.000 claims description 4
- 229910052698 phosphorus Inorganic materials 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 3
- 238000002955 isolation Methods 0.000 claims description 3
- 238000001465 metallisation Methods 0.000 claims description 3
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 2
- 238000001459 lithography Methods 0.000 claims description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 2
- 239000000126 substance Substances 0.000 claims description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims 1
- 239000011574 phosphorus Substances 0.000 claims 1
- 230000008569 process Effects 0.000 abstract description 7
- 238000002360 preparation method Methods 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000005865 ionizing radiation Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000000407 epitaxy Methods 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- JJWKPURADFRFRB-UHFFFAOYSA-N carbonyl sulfide Chemical compound O=C=S JJWKPURADFRFRB-UHFFFAOYSA-N 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000000191 radiation effect Effects 0.000 description 1
- 230000002787 reinforcement Effects 0.000 description 1
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
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- H—ELECTRICITY
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
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Abstract
The invention discloses a method for reducing breakdown leakage current of an anti-radiation strip-shaped grid MOSFET (metal oxide semiconductor field effect transistor), belonging to the field of MOSFET preparation.A substrate is provided, and an epitaxial layer is formed on the surface of the substrate; making a hardmaster self-aligned layer shape; manufacturing a P well and an N + source contact end; carrying out low-temperature wet oxygen oxidation SiO2 growth; carrying out photoetching and corrosion on the polycrystalline silicon to form a polycrystalline gate control end; and carrying out photoetching and corrosion on the P + body contact end and the metal to finally form the MOSFET. According to the invention, the design and manufacturing treatment of a dumbbell pattern of a hardmark self-alignment layer is carried out on the breakdown leakage problem of the radiation-resistant bar-shaped gate MOSFET to form the dumbbell pattern, and the process of self-aligning the P well and the N + source contact end is carried out, so that the P well surrounds the N + source contact end in all directions, and the breakdown leakage problem between the source and the drain is eliminated.
Description
Technical Field
The invention relates to the technical field of MOSFET (metal oxide semiconductor field effect transistor) preparation, in particular to a method for reducing breakdown leakage current of an anti-radiation strip grid MOSFET.
Background
The radiation-resistant power MOSFET device, in addition to meeting the conventional electrical parameter requirements, also has the radiation-resistant capability of bearing various Ionizing radiations, high-energy particles, cosmic rays and the like in space for a long time, so that the threshold voltage, the drain terminal breakdown voltage, the gate terminal breakdown voltage and the like of the power MOSFET device are all affected by the Ionizing radiation, and therefore, the device applied to the field of aerospace should have the capability of resisting Total Ionizing radiation (TID) and Single Event Effect (SEE).
The radiation hardened (radiation hardened) process is suitable for power MOSFET design and fabrication in radiation resistant applications. In an MOSFET device applied in a space environment, the total dose radiation effect is an important limitation that the device loses normal functions when used in the space environment, and the total dose effect is that when gamma rays pass through a silicon dioxide dielectric layer in a device structure region, an epitaxial region and a substrate region, electrons in the silicon dioxide dielectric layer can move to the positive electrode of the silicon dioxide dielectric layer under the action of an electric field after obtaining certain energy, and particularly at a gate oxide position, the threshold voltage becomes small, even the device leaks electricity, so that the device cannot be controlled by the voltage of a driving circuit, and the normal switching function is lost.
In the manufacturing process of the MOSFET power device, a lower resistivity is needed to be used as a substrate material sheet, and the MOSFET power device is manufactured by performing epitaxy on the substrate material sheet according to the resistivity and the thickness required by epitaxy. As shown in fig. 1, since a MOSFET power device using a commercial conventional self-aligned hardmark gate oxide process does not perform total dose reinforcement on the device in an irradiation environment, threshold shift or leakage occurs, and the requirement of radiation resistance in circuit application cannot be met.
Disclosure of Invention
The invention aims to provide a method for reducing breakdown leakage current of an anti-radiation strip-shaped gate MOSFET (metal oxide semiconductor field effect transistor), which aims to solve the problem that the breakdown leakage current is easy to occur in the manufacturing process of the conventional strip-shaped anti-radiation MOSFET power device.
In order to solve the technical problem, the invention provides a method for reducing breakdown leakage current of an anti-radiation strip gate MOSFET, which comprises the following steps:
providing a substrate, and forming an epitaxial layer on the surface of the substrate;
making a morphology of a Hardmask self-alignment layer;
manufacturing a P well and an N + source contact end;
carrying out low-temperature wet oxygen oxidation SiO2 growth;
carrying out photoetching and corrosion on the polycrystalline silicon to form a polycrystalline gate control end;
and carrying out photoetching and corrosion on the P + body contact end and the metal to finally form the MOSFET.
In one embodiment, fabricating a hardmark self-aligned layer profile comprises:
forming a dumbbell shape of the hardmark self-alignment layer according to the pattern of the hardmark self-alignment photomask; wherein the content of the first and second substances,
the material of the hardcast self-alignment layer is stable and reliable and is silicon nitride or silicon dioxide material.
In one embodiment, fabricating the P-well and N + source contact terminals includes:
performing P-well photoetching on the hardmaster self-alignment layer to finish injecting P-type impurities and performing high-temperature annealing treatment to form a dumbbell-shaped P-well;
performing an N + photomask pattern on the hardmaster self-alignment layer to form an N + source contact end pattern;
injecting N-type impurities according to the pattern of the N + photomask and carrying out high-temperature annealing treatment to form an N + source contact end; the P well surrounds the N + source contact end in an omnibearing manner;
the P-type impurity comprises B and BF2, and the implantation dosage is 1E12-5E14cm -2 The energy is 70-5000 KeV;
the N-type impurity comprises P, As, and the implantation dosage is 5E14-1E16cm -2 The energy is 50-80 KeV.
In one embodiment, performing low temperature wet oxygen oxidation SiO2 growth comprises:
firstly, forming a polycrystalline pattern according to the pattern of the Poly photomask;
and growing the gate oxide SiO2 at 800-1000 deg.C to a thickness of 30-1000 nm.
In one embodiment, performing the P + body contact and metal lithography and etching to form the MOSFET includes:
forming a pattern of the contact end of the P + body according to the pattern of the P + photomask;
injecting P-type impurities, and performing high-temperature annealing treatment after injection to form a P + body contact end;
and depositing a dielectric isolation layer, completing contact hole and metal deposition photoetching, and connecting out an N + source contact end, a P + body contact end and a polycrystalline grid control end to form a complete structure of the VDMOS power device.
In one embodiment, the P-type impurity is implanted at a dose of 5E14-5E15cm -2 The energy is 50-100 KeV.
In one embodiment, the substrate has high energy and low resistivity, and the material is silicon or arsenic, and the resistivity of the substrate is 0.002-0.004 ohm-cm;
the epitaxial layer has a resistivity of 0.3-24 Ω -cm and a thickness of 3-50 μm.
The invention provides a method for reducing breakdown leakage current of an anti-radiation bar-shaped grid MOSFET (metal-oxide-semiconductor field effect transistor), which comprises the steps of providing a substrate, and forming an epitaxial layer on the surface of the substrate; making a hardmaster self-aligned layer shape; manufacturing a P well and an N + source contact end; carrying out low-temperature wet oxygen oxidation SiO2 growth; carrying out photoetching and corrosion on the polycrystalline silicon to form a polycrystalline gate control end; and carrying out photoetching and corrosion on the P + body contact end and the metal to finally form the MOSFET.
The invention has the following beneficial effects:
(1) designing and manufacturing a dumbbell pattern of a hardmark self-alignment layer to solve the problem of breakdown leakage of the radiation-resistant bar-shaped grid MOSFET, forming the dumbbell pattern, carrying out a self-alignment process of a P well and an N + source contact end, realizing omnibearing surrounding of the P well to the N + source contact end, and eliminating the problem of breakdown leakage between a source and a drain;
(2) the processing technology is simple, the controllability is strong, and the operability is strong.
Drawings
FIG. 1 is a schematic diagram of a conventional radiation-resistant hardmark self-aligned dielectric layer;
FIG. 2 is a schematic flow chart of a method for reducing leakage current of radiation-resistant bar gate MOSFET;
FIG. 3 is a schematic diagram of the patterning of a hardmark according to the pattern of a hardmark self-aligned dielectric layer mask;
FIG. 4 is a schematic diagram of a P-well mask pattern for forming a P-well;
FIG. 5 is a schematic diagram of forming an N + source contact terminal;
FIG. 6 is a schematic diagram of forming a Poly gate control pattern;
FIG. 7 is a schematic illustration of forming a P + body contact end;
FIG. 8 is a schematic view of forming a contact hole;
FIG. 9 is a graph showing a comparison of source-drain breakdown leakage for two types of radiation-resistant stripe gate MOSFETs.
Detailed Description
The following describes a method for reducing breakdown leakage current of a radiation-resistant bar gate MOSFET according to the present invention with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
The invention provides a method for reducing breakdown leakage current of an anti-radiation bar-shaped grid MOSFET, the flow of which is shown in figure 2, and the method comprises the following steps:
step S21, providing a substrate, and forming an epitaxial layer on the surface of the substrate;
step S22, making a pattern of a hardcast photomask to form a hardcast self-aligned dielectric layer appearance;
s23, manufacturing a pattern of a P-well photomask to form a P-well shape;
s24, making a pattern of an N + photomask to form an N + source contact end morphology;
step S25, growing gate oxide SiO 2;
step S26, carrying out photoetching and corrosion on the polycrystalline silicon to form a polycrystalline gate control end;
and step S27, manufacturing a P + body contact and a metal control end to form the MOSFET device.
Firstly, providing a substrate, wherein the substrate has the characteristic of high energy and low resistivity, the material of the substrate can be silicon or arsenic, and the resistivity is 0.002-0.004 Ω · cm in the embodiment taking the silicon substrate as an example; forming an epitaxial layer on the surface of the substrate, wherein the resistivity of the epitaxial layer is 3-24 omega-cm, and the thickness of the epitaxial layer is 3-50 mu m;
performing hardcast photomask photoetching according to the device requirements, forming a dumbbell design appearance of the hardcast self-aligned dielectric layer according to the pattern of the hardcast photomask 1, wherein the dimension a is equal to the dimension b as shown in figure 3;
performing photoetching of a P well according to the requirements of the device, firstly forming the P well according to the pattern of a P well photomask 2, wherein the dimension c is equal to d as shown in FIG. 4;
the implantation dosage is 1E12-5E14cm -2 B, BF2 and other P-type impurities with energy of 70-5000KeV are subjected to high-temperature annealing treatment after injection is finished and used for forming the dumbbell-shaped P well;
carrying out photoetching on an N + source contact end according to the requirements of a device, and firstly forming the shape of the N + source contact end according to the pattern of an N + source contact end photomask 3, wherein the size e is equal to the sizes c and d as shown in FIG. 5;
the implantation dosage is 5E14-1E16cm -2 And P, As with energy of 50-80KeV, and performing high-temperature annealing treatment to form N + source contact terminal.
Carrying out polycrystal control end according to the requirements of the device, and forming a polycrystal pattern according to the pattern of the Poly 4 photomask, as shown in FIG. 6;
growing gate oxide SiO2 at 800-1000 deg.C, and completing the photoetching and etching process of polysilicon to form a control end of polycrystalline gate;
forming a pattern of the P + body contact end according to the pattern of the P +5 photomask by performing the P + body contact end according to the requirements of the device, as shown in FIG. 7;
carrying out P-type B, BF2Implanting impurities at a dose of 5E14-5E15cm -2 The energy is 50-100KeV, and high-temperature annealing treatment is carried out after injection is finished to form a P + body contact end;
and depositing a dielectric isolation layer to complete a contact hole and metal deposition photoetching, and connecting an N + source contact end, a P + body contact end and a polycrystalline grid control end to form a complete structure of the VDMOS power device.
The preparation of the anti-radiation strip-shaped gate VDMOS reinforced process device is formed through the seven main process procedures. Due to the design of the hardcast self-aligned dielectric layer of the anti-radiation strip-shaped gate VDMOS, a dumbbell shape is formed, the back P well is in a dumbbell shape, and self-aligned manufacturing of the end head which completely comprises the N + source end is achieved. The dumbbell-shaped P well covers the two sides of the N + source end completely, so that the inconsistency of the field intensity curvature radius of the electric field of the source-drain breakdown leakage end is eliminated, the current path of the source-drain breakdown leakage is cut off finally, and the leakage is reduced, as shown in fig. 9.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (7)
1. A method for reducing the breakdown leakage current of a radiation-resistant bar gate MOSFET (metal oxide semiconductor field effect transistor), comprising the following steps:
providing a substrate, and forming an epitaxial layer on the surface of the substrate;
making a hardmaster self-aligned layer shape;
manufacturing a P well and an N + source contact end;
carrying out low-temperature wet oxygen oxidation SiO2 growth;
carrying out photoetching and corrosion on the polycrystalline silicon to form a polycrystalline gate control end;
and carrying out photoetching and corrosion on the P + body contact end and the metal to finally form the MOSFET.
2. The method of claim 1, wherein fabricating a hardmark self-aligned layer profile comprises:
forming a dumbbell shape of the hardmark self-alignment layer according to the pattern of the hardmark self-alignment photomask; wherein the content of the first and second substances,
the material of the hardcast self-alignment layer is stable and reliable and is silicon nitride or silicon dioxide material.
3. The method of claim 2, wherein the step of forming the P-well and N + source contact terminals comprises:
performing P-well photoetching on the hardmaster self-alignment layer to finish injecting P-type impurities and performing high-temperature annealing treatment to form a dumbbell-shaped P-well;
performing an N + photomask pattern on the hardmaster self-alignment layer to form an N + source contact end pattern;
injecting N-type impurities according to the pattern of the N + photomask and carrying out high-temperature annealing treatment to form an N + source contact end; the P well surrounds the N + source contact end in an omnibearing manner;
the P-type impurity comprises B and BF2, and the implantation dosage is 1E12-5E14cm -2 The energy is 70-5000 KeV;
the N-type impurity comprises P, As, and the implantation dosage is 5E14-1E16cm -2 The energy is 50-80 KeV.
4. The method of claim 3, wherein the performing of the low temperature wet oxygen oxidation SiO2 growth comprises:
firstly, forming a polycrystalline pattern according to the pattern of a Poly photomask;
and growing the gate oxide SiO2 at 800-1000 deg.C to a thickness of 30-1000 nm.
5. The method of claim 4, wherein the P + body contact terminal and metal lithography and etching are performed to form the MOSFET by:
forming a pattern of the contact end of the P + body according to the pattern of the P + photomask;
injecting P-type impurities, and performing high-temperature annealing treatment after injection to form a P + body contact end;
and depositing a dielectric isolation layer, completing contact hole and metal deposition photoetching, and connecting out an N + source contact end, a P + body contact end and a polycrystalline grid control end to form a complete structure of the VDMOS power device.
6. The method of claim 5, wherein the P-type impurity is implanted at a dose of 5E14-5E15cm -2 The energy is 50-100 KeV.
7. The method for reducing leakage current after breakdown of an anti-radiation bar gate MOSFET as claimed in claim 1, wherein said substrate has high energy and low resistivity, and is made of silicon, doped with phosphorus or arsenic, and has a resistivity of 0.002-0.004 Ω -cm;
the epitaxial layer has a resistivity of 0.3-24 Ω -cm and a thickness of 3-50 μm.
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