JP2011134972A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve short-channel characteristics of a P-type FET having a channel region composed of a semiconductor including Ge while preventing the occurrence of reverse short-channel characteristics. <P>SOLUTION: The semiconductor device includes the P-type FET formed on a semiconductor substrate 100. The P-type FET is formed on the semiconductor substrate 100, and includes a first semiconductor layer 103 formed on the semiconductor substrate 100 and including Ge, a second semiconductor layer 104 formed on the first semiconductor layer 103 and including Ge having lower concentration than the first semiconductor layer 103, a gate electrode 110a formed on the second semiconductor layer 104 with a gate insulating film 107a interposed therebetween, p-type extension regions 111a formed at both positions of the second semiconductor layer 104 by the gate electrode 110a, and n-type impurity regions 152 provided in the first semiconductor layer 103 and formed under the p-type extension regions 111a. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The technology disclosed in the present specification relates to a P-channel field effect transistor (P-type FET) having a channel region made of a semiconductor containing germanium (Ge) and a method for manufacturing the same.

  As the design rules of semiconductor devices are reduced, the degree of circuit integration has dramatically improved, and more than 100 million field effect transistors (FETs) can be mounted on one chip. In order to realize a high-performance transistor, not only reduction of the gate length but also reduction of the gate insulating film is required. Conventionally, a silicon oxide film or a silicon oxynitride film, which is a nitride film thereof, has been used as the gate insulating film. However, if the EOT (Equivalent Oxide Thickness) is a thin film region of 2 nm or less, the gate leakage current increases. This causes a problem that the power consumption of the circuit increases.

  Therefore, in order to realize an EOT thin film while reducing a gate leakage current, attention is focused on a high dielectric constant gate insulating film. For example, a transistor having a high dielectric constant gate insulating film / metal gate electrode structure in which a gate electrode containing a metal material such as titanium nitride or tantalum nitride is combined with a high dielectric constant gate insulating film for further EOT thinning Much research and development has been done.

  One of the problems in realizing the high dielectric constant gate insulating film / metal gate electrode structure is the threshold voltage control of the transistor. In silicon electrodes that have been used conventionally, the work function of the gate electrode is adjusted by impurity ion implantation, and threshold voltages suitable for the N-type FET and P-type FET are realized. Specifically, for N-type FETs, the work function is reduced by implanting n-type impurities such as arsenic and phosphorus into the silicon electrode, and for P-type FETs, p-type such as boron is used for the silicon electrode. The work function is increased by injecting impurities. On the other hand, the threshold voltage control of a transistor is a big problem because work function control by impurity implantation cannot be performed for a metal electrode.

As a measure for controlling the threshold voltage of the P-type FET, particularly for reducing the threshold voltage, the channel region of the transistor is Si _1-x Ge _x (0 <x ≦ 1) compared to conventional silicon (Si). ) (Hereinafter sometimes simply referred to as “SiGe”) (see Non-Patent Document 1).

  FIG. 8A is a diagram schematically showing a cross-sectional shape of the P-type FET described in Non-Patent Document 1. FIG. The P-type FET is provided on the semiconductor substrate 500, the SiGe layer 504a having a thickness of about 50 nm provided on the active region 500a of the semiconductor substrate 500, and the gate insulating film 507a sandwiched between the SiGe layer 504a. Of the gate electrode 510a, the p-type extension region 511a and the n-type pocket impurity region 512a provided in the regions located on both sides of the gate electrode 510a in the SiGe layer 504a, the active region 500a, and the SiGe layer 504a P-type source / drain regions 514a provided on both sides of the gate electrode 510a and outside the extension region 511a when viewed from the gate electrode 510a. Of the SiGe layer 504a, a region directly below the gate electrode 510a is an n-type SiGe layer 504, and a channel region is formed in the n-type SiGe layer 504.

  The gate insulating film 507a is composed of a lower gate insulating film 505a and an upper gate insulating film 506a, and the gate electrode 510a is composed of a lower gate electrode 508a and an upper gate electrode 509a.

  The mechanism for reducing the threshold voltage by configuring the channel region with SiGe is as follows.

The band gap of Si is 1.12 eV, whereas the band gap of Ge is as small as 0.66 eV, and the band gap of Si _1-x Ge _x (0 <x ≦ 1), which is a mixed crystal thereof, is According to the Ge composition ratio x, it continuously changes from 0.66 eV to 1.12 eV. Since the electron affinity of Si and Ge is almost the same, the fluctuation of the band gap of Si _1-x Ge _x (0 <x ≦ 1) accompanying the change of the composition ratio x is mainly due to the fluctuation of the energy of the valence band. to cause. That is, the energy of the valence band of Si _1-x Ge _x (0 <x ≦ 1) is higher than the energy of the valence band of Si. As a result, the threshold voltage can be reduced by configuring the channel with SiGe. According to Non-Patent Document 1, a reduction in threshold voltage of about 250 to 300 mV has been reported by forming a channel in a part of the n-type SiGe layer 504.

H. R. Harris et al., Symp. VLSI Technology, p.154, 2007. Sumitomo & Matsumoto, Journal of The Electrochemical Society, 155 (4), H210-H212 (2008)

  However, when the SiGe layer is used for the channel, there is a problem that the Vt roll-off (hereinafter sometimes referred to as short channel characteristics) of the transistor is likely to deteriorate.

  In the conventional semiconductor device shown in FIG. 8A, an n-type pocket impurity region is provided around the extension region 511a in order to improve the short channel characteristic, that is, the characteristic that the threshold voltage rapidly decreases when the gate length is shortened. 512a is provided.

  FIG. 8B is a diagram showing the relationship between the threshold voltage Vt and the gate length Lg in the conventional semiconductor device. Here, a semiconductor device in which a channel region is made of Si, a semiconductor device in which a channel region is made of SiGe, a pocket impurity region containing a high concentration impurity, and a channel region is made of SiGe, and a low concentration The simulation result about each of the semiconductor devices provided with the pocket impurity region containing an impurity is shown.

  From the result shown in FIG. 8B, in the semiconductor device in which the channel region is made of Si, the threshold voltage is almost constant over a wide gate length range. It was found that in the semiconductor device provided, as the gate length decreased, the threshold voltage decreased and the short channel characteristics deteriorated.

  As a result of investigation by the inventors of the present application, in the SiGe layer, the impurity diffusion coefficient in the pocket impurity region is larger than in the Si layer, the impurity in the pocket impurity region diffuses during the activation annealing, and the impurity concentration is increased. It was thought to have occurred because of the decline. According to Non-Patent Document 2, when the Ge concentration increases by 25%, the diffusion coefficient of arsenic (As) increases by an order of magnitude.

  Here, when the impurity concentration in the pocket impurity region is increased, the short channel characteristics can be improved to some extent as shown in FIG. However, in this case, since the amount of impurities diffusing from the pocket impurity region to the lower side of the gate electrode increases, a phenomenon (inverse short channel characteristic) in which the threshold voltage increases once when the gate length is short occurs. End up.

  In particular, in the SiGe layer, since the diffusion of impurities in the pocket impurity region increases, the diffusion of the pocket impurity to the lower portion of the gate electrode becomes remarkable, and the reverse short channel characteristic appears strongly.

  That is, by increasing the pocket impurity concentration, it is possible to reduce fluctuations in threshold voltage due to fluctuations in gate dimensions (improvement of short channel characteristics), but in short transistors (that is, transistors having a short gate length). It is considered that it is not easy to suppress the fluctuation of the threshold voltage while suppressing the increase of the threshold voltage as a whole.

  An object of the present invention is to improve short channel characteristics while suppressing the occurrence of reverse short channel characteristics in a P-type FET having a channel region formed of a semiconductor containing Ge.

  A semiconductor device as an example of the present invention is a semiconductor device including a P-channel transistor formed on a semiconductor substrate, and the P-channel transistor is formed on the semiconductor substrate and contains germanium. One semiconductor layer, a second semiconductor layer formed on the first semiconductor layer and containing germanium at a lower concentration than the first semiconductor layer, and a first semiconductor layer on the second semiconductor layer. A first gate electrode formed with a gate insulating film interposed therebetween, and a p-type first extension formed on a portion of the second semiconductor layer located on both sides of the first gate electrode. A region and an n-type impurity region provided at least in the first semiconductor layer and formed below the first extension region.

  According to the above-described configuration, the short channel effect can be suppressed, for example, the leakage current between the source and the drain can be reduced by providing the n-type impurity region below the first extension region. In addition, the diffusion coefficient of n-type impurities in the SiGe layer increases as the Ge concentration increases. Therefore, by making the Ge concentration contained in the second semiconductor layer lower than the Ge concentration in the first semiconductor layer, the diffusion of the n-type impurity in the n-type impurity region into the region below the gate electrode is suppressed. Therefore, even when the gate length is short, the occurrence of an inverse short channel effect such as an increase in threshold voltage can be suppressed.

  On the other hand, the diffusion coefficient of the p-type impurity contained in the first extension region decreases as the Ge concentration in the semiconductor layer increases. Therefore, the diffusion of the p-type impurity is suppressed in the first semiconductor layer having a Ge concentration higher than that of the second semiconductor layer, so that the junction between the first extension region and the n-type impurity region is compared with the conventional semiconductor device. The depth of the part can be reduced. Therefore, the short channel effect can be effectively suppressed. Further, since the second semiconductor layer made of SiGe is provided below the gate electrode, the threshold voltage of the P-type FET can be lowered as compared with the case where the gate electrode is provided on the silicon substrate.

  A method for manufacturing a semiconductor device according to an example of the present invention includes: a step of forming a first semiconductor layer containing germanium on a semiconductor substrate; and a lower concentration than the first semiconductor layer on the first semiconductor layer. Forming a second semiconductor layer containing germanium, forming a gate electrode on the second semiconductor layer with a gate insulating film interposed therebetween, and using the gate electrode as a mask, A step of implanting p-type impurity ions into the semiconductor layer to form an extension implantation region; and applying heat treatment to the semiconductor substrate to activate impurities in the extension implantation region, so that the gate of the second semiconductor layer is activated. Forming a p-type extension region in regions located on both sides of the electrode.

  According to this method, an n-type impurity region for forming an n-type impurity region is provided by providing a first semiconductor layer containing Ge and a second semiconductor layer containing Ge at a lower concentration than the first semiconductor layer. Impurities can be prevented from diffusing into a portion of the second semiconductor layer located below the gate electrode during the manufacturing process. Further, by suppressing the p-type impurity in the extension implantation region from diffusing into the first semiconductor layer, the depth of the junction between the extension region and the n-type impurity region can be reduced, and the short channel effect can be achieved. It is possible to manufacture a semiconductor device in which the above is suppressed. For this reason, even when the gate length is shortened, the effect of reducing the threshold voltage by using the second semiconductor layer containing Ge as a channel can be exhibited.

  According to the semiconductor device according to the example of the present invention, in the P-type FET, it is possible to improve the short channel characteristic while suppressing the occurrence of the reverse short channel characteristic. Therefore, by using the semiconductor layer containing Ge as the channel. The threshold voltage reduction effect can be maintained even when the gate length is shortened.

(A) is sectional drawing which shows the semiconductor device which concerns on embodiment which is an example of this invention, (b) is a figure which shows the relationship between the gate length and threshold voltage in the said semiconductor device and the conventional semiconductor device. is there. (A)-(c) is sectional drawing which shows typically the manufacturing method of the semiconductor device shown in FIG. (A)-(c) is sectional drawing which shows typically the manufacturing method of the semiconductor device shown in FIG. (A)-(c) is sectional drawing which shows typically the manufacturing method of the semiconductor device shown in FIG. (A) is sectional drawing which shows the modification of the semiconductor device shown to Fig.1 (a), (b) is the relationship between the gate length and threshold voltage in the semiconductor device which concerns on the said modification, and the conventional semiconductor device. FIG. (A)-(c) is sectional drawing which shows typically the manufacturing method of the semiconductor device which concerns on the modification shown to Fig.5 (a). (A)-(c) is sectional drawing which shows typically the manufacturing method of the semiconductor device which concerns on the modification shown to Fig.5 (a). (A) is a figure which shows typically the cross-sectional shape of P-type FET of a nonpatent literature 1, (b) shows the relationship between the threshold voltage Vt and the gate length Lg in the conventional semiconductor device. FIG.

  FIG. 1A is a cross-sectional view showing a semiconductor device according to an embodiment which is an example of the present invention.

  The semiconductor device of this embodiment includes a semiconductor substrate 100 in which a P-type FET region and an N-type FET region are formed, an n-well region 100a formed in the P-type FET region of the semiconductor substrate 100, and an n-well region 100a. An active region 102a which is a portion surrounded by the element isolation region 101, a p well region 100b formed in an N-type FET region of the semiconductor substrate 100, and an element isolation region 101 of the p well region 100b. An active region 102b, a P-type FET provided on the P-type FET region (on the active region 102a) of the semiconductor substrate 100, and an N-type FET region (on the active region 102b) of the semiconductor substrate 100. N-type FET. Here, the active region 102a includes an n well region 100a formed in the semiconductor substrate 100, a first semiconductor layer 103 containing germanium (Ge) formed on the n well region 100a, and a first semiconductor layer. 103 and a second semiconductor layer 104 containing germanium at a lower concentration than the first semiconductor layer 103. The active region 102 b has a p-well region 100 b formed in the semiconductor substrate 100.

  The P-type FET includes a gate electrode 110a formed on the second semiconductor layer 104 in the active region 102a with a gate insulating film 107a interposed therebetween, a sidewall spacer 113a formed on a side surface of the gate electrode 110a, A p-type extension region 111a formed in a portion of the second semiconductor layer 104 located on both sides of the gate electrode 110a and a p-type extension region provided in the first semiconductor layer 103 at least in the active region 102a. An n-type impurity region 152 formed under 111a and the active region 102a are formed on both sides of the gate electrode 110a and at a portion located outside the p-type extension region 111a when viewed from the gate electrode 110a. p-type source / drain regions 114a.

  Note that in this specification, “source / drain region” means “source region or drain region”. If one of the source / drain regions provided with the gate electrode interposed therebetween is a source region, the other is If one is a drain region, the other is a source region. The p-type impurity concentration of the p-type source / drain region 114a includes a higher concentration of p-type impurities than the p-type extension region 111a.

  The atomic concentration of Ge in the first semiconductor layer 103 (100 fraction of Ge atoms in atoms constituting the crystal lattice) is, for example, 50%, and the atomic concentration of Ge in the second semiconductor layer 104 is, for example, 25. %. Hereinafter, simply referring to “Ge concentration” in this specification means the atomic concentration of Ge.

  The gate insulating film 107a includes, for example, a silicon oxide film 105a having a thickness of 1 nm and a high dielectric constant insulating film 106a provided on the silicon oxide film 105a and having a thickness of 2 nm. The high dielectric constant insulating film 106a is made of, for example, a metal oxide that is a high dielectric constant insulator such as hafnium (Hf) oxide. Here, the “high dielectric constant insulator” means a substance having a dielectric constant higher than that of the silicon nitride film.

  The gate electrode 110a includes a lower gate electrode 108a made of a metal or a conductive metal compound provided on the gate insulating film 107a, and an upper gate electrode 109a made of polysilicon or the like provided on the lower gate electrode 108a. Has been. The lower gate electrode 108a is made of, for example, titanium nitride (TiN). The film thickness of the lower gate electrode 108a is, for example, about 10 nm, and the film thickness of the upper gate electrode 109a is, for example, about 100 nm. The width of the gate electrode 110a in the gate length direction is about 40 nm, and the width of the sidewall spacer 113a is about 40 nm, for example.

  The p-type extension region 111a is located immediately below the sidewall spacer 113a and overlaps the end of the gate electrode 110a in the gate length direction in plan view.

  A portion of the n-type impurity region 152 located below the p-type extension region 111a is an n-type pocket region 112a. The n-type pocket region 112 a extends to the inner side of the p-type extension region 111 a in the first semiconductor layer 103 and extends to the lower part of the second semiconductor layer 104. A portion of the n-type impurity region 152 located immediately below the gate electrode 110a (ie, the n-type lower SiGe layer 103a) is located under the p-type extension region 111a in the n-type impurity region 152 and in the first semiconductor layer 103. The n-type impurity concentration is lower than the portion (n-type pocket region 112a) provided inside. Further, the n-type impurity concentration of the portion of the n-type pocket region 112a provided in the second semiconductor layer 104 is lower than the p-type extension region 111a in the n-type pocket region 112a and the first semiconductor layer. The n-type impurity concentration of the portion provided in the layer 103 is lower. Note that the junction interface between the p-type extension region 111 a and the n-type pocket region 112 a is located at a depth of, for example, 20 nm from the upper surface of the second semiconductor layer 104.

  Further, a portion of the second semiconductor layer 104 located immediately below the gate electrode 110a is an n-type upper SiGe layer 104a containing an n-type impurity at the same concentration as the n-type lower SiGe layer 103a. The n-type upper SiGe layer 104a becomes a channel region during the operation of the P-type FET.

The n-type impurity concentration of the portion of the n-type pocket region 112a provided in the first semiconductor layer 103 is 3 × 10 ¹⁸ atoms / cm ³ , for example, and the n-type lower SiGe layer 103a and the n-type upper SiGe layer 104a The n-type impurity concentration is, for example, 1 × 10 ¹⁷ atoms / cm ³ . Note that a portion of the n-type pocket region 112a located in the first semiconductor layer 103 and below the p-type extension region 111a has an n-type impurity concentration peak.

  On the other hand, the active region 102b in the N-type FET region of the semiconductor substrate 100 is not provided with a Ge-containing semiconductor layer such as a SiGe layer.

  The N-type FET includes a gate electrode 110b formed on the active region 102b with a gate insulating film 107b interposed therebetween, a sidewall spacer 113b formed on a side surface of the gate electrode 110b, and an active region 102b (semiconductor substrate 100). ), An n-type extension region 111b formed in a portion located on both sides of the gate electrode 110b, and a p-type pocket region 112b formed in a portion of the active region 102b located under the n-type extension region 111b; The n-type source region / drain region 114b is formed on a part of the active region 102b on both sides of the gate electrode 110b and outside the n-type extension region 111b when viewed from the gate electrode 110b. Yes.

  In the example shown in FIG. 1A, a portion of the active region 102b immediately below the gate electrode 110b is a channel region.

  The gate insulating film 107b is composed of a silicon oxide film 105b and a high dielectric constant insulating film 106b formed on the silicon oxide film 105b and made of a metal oxide or the like.

  The gate electrode 110b includes a lower gate electrode 108b made of a metal or a conductive metal compound provided on the gate insulating film 107b, and an upper gate electrode 109b made of polysilicon or the like provided on the lower gate electrode 108b. Has been. The lower gate electrode 108b is made of, for example, TiN.

  FIG. 1B is a diagram showing the relationship between the gate length and the threshold voltage in the semiconductor device of this embodiment and the conventional semiconductor device. In this figure, (1) the semiconductor device of this embodiment in which a gate electrode is provided on the laminated SiGe layer shown in FIG. 1A, and (2) a conventional semiconductor device in which a gate electrode is provided on a single-layer SiGe layer. And (3) a simulation result for a conventional semiconductor device in which a gate electrode is provided on a general Si substrate.

  Since the semiconductor device of this embodiment has a channel region made of SiGe, the threshold voltage when compared with the same gate length (Lg) is greatly reduced as shown in FIG. ing. For this reason, the on-current of the semiconductor device can be improved.

  In addition, since the n-type pocket region 112a is provided in the P-type FET, the leakage current between the source and the drain is effectively reduced. In particular, p-type impurities (for example, boron) are more difficult to diffuse when the Ge concentration in the SiGe layer is higher. In the P-type FET of this embodiment, the diffusion of the p-type impurity contained in the p-type extension region 111a is suppressed in the first semiconductor layer 103 having a high Ge concentration, so the p-type extension region 111a and the n-type pocket region 112a. PN junction position can be made shallower. For this reason, the short channel characteristic in the P-type FET is greatly improved as compared with the conventional semiconductor device having a single-layer SiGe layer.

  Further, the diffusion coefficient of the n-type impurity in the SiGe layer increases as the Ge concentration in the SiGe layer increases. Here, in the semiconductor device of this embodiment, since the Ge concentration of the second semiconductor layer 104 including the stacked SiGe layer and including the channel region is lower than the Ge concentration of the first semiconductor layer 103, n Impurities such as arsenic (As) and phosphorus (P) implanted to form the mold pocket region 112a are difficult to diffuse into the channel region during heat treatment. For this reason, as shown by the line (1) in FIG. 1B, the threshold voltage fluctuates in a wider gate length range than the conventional semiconductor device having the single-layer SiGe layer (line (2)). It is getting smaller.

  As described above, in the semiconductor device of this embodiment, the n-type pocket region 112a is formed mainly in the first semiconductor layer 103 having a high Ge concentration, thereby suppressing the occurrence of the short channel effect in the P-type FET and the gate. Even in a short length range, the variation in threshold voltage can be reduced. For this reason, in the semiconductor device of this embodiment, when a large number of P-type FETs are provided, even if the gate length varies, the threshold voltage does not easily vary, and the threshold voltage can be easily controlled. It has become. Further, the effect of reducing the threshold voltage by using the SiGe channel in the P-type FET can be maintained even in the P-type FET having a small gate length.

  Note that the film thickness of each layer and the Ge concentration in the first semiconductor layer 103 and the second semiconductor layer 104 are not limited to the above-described examples, and are adjusted according to the threshold voltage to be set and the degree of deterioration of the short channel characteristics. Can be arbitrarily selected.

  For example, the Ge concentration in the first semiconductor layer 103 may be greater than 0% and 100% or less, and the Ge concentration in the second semiconductor layer 104 may be lower than the Ge concentration in the first semiconductor layer 103. 0% or more and less than 100%. However, from the viewpoint of threshold voltage reduction, the Ge concentration of the second semiconductor layer 104 is preferably 10% or more. Further, diffusion of pocket impurities (impurities implanted to form the n-type pocket region 112a) into the region below the gate electrode 110a is suppressed, and the junction position of the p-type extension region 111a with the n-type pocket region 112a is shallow. In view of this, the Ge concentration in the first semiconductor layer 103 is desirably 10% or more higher than the Ge concentration in the second semiconductor layer 104. The thickness of the first semiconductor layer 103 is preferably in the range of 5 nm to 20 nm in order to maintain the effect of suppressing short channel characteristics due to pocket impurities.

  In the above example, the p-type extension region 111a is formed in the second semiconductor layer 104, and the impurity concentration peak of the n-type pocket region 112a is formed in the first semiconductor layer 103. The formation position of the region 111a and the peak position of the impurity concentration of the n-type pocket region 112a are not limited thereto. For example, the p-type extension region 111a may be formed not only in the second semiconductor layer 104 but also in the first semiconductor layer 103, and the peak position of the impurity concentration of the n-type pocket region 112a is the second position. The semiconductor layer 104 may be present. Even in the latter case, since the n-type impurity for forming the pocket region is less likely to diffuse into the region below the gate electrode 110a as compared with the conventional semiconductor device, the reverse short channel effect is suppressed.

  Note that the n-type impurity introduced into the n-type pocket region 112a may be arsenic, phosphorus, or both. The p-type impurity contained in the p-type extension region 111a and the p-type source / drain region 114a may be boron, for example.

  In the above example, the silicon oxide film 105a is formed on the second semiconductor layer 104. However, after forming a thin Si layer epitaxially grown on the second semiconductor layer 104, for example, The silicon oxide film 105a may be formed by oxidizing the upper part. By forming the Si layer, the film quality of the silicon oxide film 105a can be improved, and it is possible to suppress deterioration of characteristics of the P-type FET such as mobility deterioration. However, if the Si layer is too thick, a channel is formed not only in the second semiconductor layer made of SiGe but also in the Si layer, and the threshold voltage reduction effect is reduced. For this reason, it is desirable that the thickness of the Si layer exceeds 0 nm and is 3 nm or less.

  In addition, the strain state of the first semiconductor layer 103 and the second semiconductor layer 104 is not particularly limited, but appropriate strain is applied to both layers in order to effectively reduce the threshold voltage. Is desirable. Such strain can be applied by various methods. For example, the lattice of the SiGe layer is distorted by epitaxially growing the first semiconductor layer 103 and the second semiconductor layer 104 on the semiconductor substrate 1 made of silicon. be able to.

  Further, the constituent materials and film thicknesses of the silicon oxide film 105a, the high dielectric constant insulating film 106a, the lower gate electrode 108a, the upper gate electrode 109a, the sidewall spacer 113a, and the like are not limited to the contents described above. The configuration of these members does not affect the effect obtained by the configuration of the present embodiment.

-Manufacturing method of semiconductor device according to this embodiment-
2A to 2C, 3A to 3C, and 4A to 4C are cross-sectional views schematically showing a method for manufacturing the semiconductor device shown in FIG. . 2A to 2C show both the P-type FET region and the N-type FET region when forming the CMOS structure for easy understanding, but FIGS. 3A to 3C and FIG. a) to (c) show only the P-type FET region.

  First, as shown in FIG. 2A, after forming an n-well region 100a and a p-well region 100b on a semiconductor substrate 100 made of silicon or the like and containing n-type impurities such as phosphorus and arsenic, STI (Shallow Trench Isolation) is formed. The active regions 102a and 102b are formed by forming the element isolation region 101 by the method.

  Next, a protective film 150 is formed on the entire surface of the semiconductor substrate 100. As the protective film 150, for example, a silicon oxide film having a thickness of about 10 nm is used. Subsequently, an opening is provided in the upper portion of the P-type FET region of the protective film 150 by known lithography and etching with hydrofluoric acid or the like. This protective film 150 is formed for the purpose of inhibiting the growth of the SiGe layer.

  Next, as shown in FIG. 2B, Si etching 151 is performed using the protective film 150 as a mask, and the semiconductor substrate 100 is thinned by the thickness of an SiGe layer to be formed later (for example, 30 nm). Specifically, the exposed P-type FET region is etched by heat-treating the semiconductor substrate 100 at 850 degrees in a hydrogen chloride (HCl) atmosphere.

  Next, as shown in FIG. 2C, a first semiconductor layer 103 made of non-doped SiGe with a Ge concentration of 50% on the P-type FET region of the semiconductor substrate 100 (active region 102a), and a Ge concentration of A 25% non-doped second semiconductor layer 104 is formed. The film thickness of the first semiconductor layer 103 is, for example, 10 nm, and the film thickness of the second semiconductor layer 104 is, for example, 20 nm. Here, the SiGe layers constituting the first semiconductor layer 103 and the second semiconductor layer 104 are epitaxially grown by a CVD (Chemical Vapor Deposition) method or the like.

When forming the SiGe layer, for example, monosilane (SiH ₄ ) is used as a silicon-based source gas. As germanium-based source gas, for example, monogermane (GeH ₄ ) is used. Using these mixed gases, a SiGe layer is deposited under conditions of 550 ° C. in an atmosphere of hydrogen or nitrogen gas. The Ge concentration is adjusted by controlling the flow rate of the germanium-based source gas during deposition. By increasing the flow rate of the germanium-based source gas, a SiGe layer containing Ge at a higher concentration is formed.

  Next, as shown in FIG. 3A, after the protective film 150 (not shown) is removed by hydrofluoric acid treatment, the surface of the second semiconductor layer 104 is oxidized with ozone to form silicon having a thickness of 1 nm. An oxide film 105 is formed, and a high dielectric constant insulating film 106 made of hafnium oxide or the like having a thickness of 2 nm is formed on the silicon oxide film 105. Subsequently, a TiN film 108 having a thickness of 10 nm is formed on the high dielectric constant insulating film 106, and a polysilicon film 109 having a thickness of 100 nm is formed thereon.

  Thereafter, as shown in FIG. 3B, resist patterning and dry etching are performed, so that the gate insulating film 107a composed of the silicon oxide film 105a and the high dielectric constant insulating film 106a, the lower gate electrode 108a, and the upper gate are formed. A gate electrode 110a composed of the electrode 109a is formed. The gate dimension (gate length) of the gate electrode 110a is, for example, 40 nm.

  Next, as shown in FIG. 3C, p-type extension implantation region 111A is formed by implanting boron into second semiconductor layer 104 using gate electrode 110a as a mask. Further, arsenic is implanted into the first semiconductor layer 103 using the gate electrode 110a as a mask, thereby forming an n-type pocket implantation region 112A. Either the p-type extension implantation region 111A or the n-type pocket implantation region 112A may be formed first.

In this step, boron ion implantation is performed under the conditions of an acceleration energy of 0.5 keV, a dose of 5 × 10 ¹⁴ atoms / cm ² , and a tilt angle of 0 degree (implantation depth Rp = 4 nm). The arsenic ion implantation is performed under the conditions of an acceleration energy of 25 keV, a dose amount of 3 × 10 ¹³ atoms / cm ² , a tilt angle of 15 degrees, and four rotations (implantation depth Rp = 25 nm).

  Next, as shown in FIG. 4A, after a silicon nitride film having a thickness of about 40 nm is formed on the substrate (semiconductor device being fabricated), the entire surface is etched back by dry etching, so that the gate electrode is formed. A side wall spacer 113a made of a silicon nitride film having a width of 40 nm is formed on the side surface.

Next, as shown in FIG. 4B, p-type source / drain implantation regions 114A are formed by implanting p-type impurities into the active region 102a using the gate electrode 110a and the sidewall spacer 113a as a mask. Boron is used as an impurity for implantation, and ion implantation is performed under conditions of an acceleration energy of 1.5 keV and a dose of 4 × 10 ¹⁵ atoms / cm ² , so that the first semiconductor layer 103, the second semiconductor layer 104, and A p-type source / drain implantation region 114 A is formed on the semiconductor substrate 100.

  Next, as shown in FIG. 4C, spike annealing is performed under the conditions of 1000 ° C. and 0 seconds to activate the impurities introduced by ion implantation. By this annealing, boron in the p-type extension implantation region 111A is diffused to form the p-type extension region 111a, and arsenic in the n-type pocket implantation region 112A is diffused to contact the p-type extension region 111a. 112a is formed. Also, the p-type source / drain implantation region 114A becomes a p-type source / drain region 114a. Note that the depth of the junction between the p-type extension region 111a and the n-type pocket region 112a from the upper surface of the second semiconductor layer 104 is about 20 nm.

  In this step, since the diffusion of boron is suppressed by the first semiconductor layer 103 having a high Ge concentration, the depth of the junction between the p-type extension region 111a and the n-type pocket region 112a is the same as that of the second semiconductor layer 104. It is almost the same as the film thickness. Further, arsenic in the n-type pocket implantation region 112 </ b> A is prevented from being diffused upward by the second semiconductor layer 104, and is mainly diffused in the first semiconductor layer 103.

  Note that the n-type impurity contained in the n-well region 100a and the n-type pocket implantation region 112A is included in the gate of the first semiconductor layer 103 due to the heat applied during the epitaxial growth shown in FIG. By diffusing to a portion located below the electrode 110a, an n-type lower SiGe layer 103a is formed, and an n-type impurity is diffused to a portion located below the gate electrode 110a in the second semiconductor layer 104. Then, the n-type upper SiGe layer 104a is formed.

  Thus, in the method of this embodiment, a stacked SiGe layer having a lower Ge concentration and a lower upper Ge concentration is formed on the semiconductor substrate 100. This suppresses the diffusion of pocket impurities into the lower region of the gate electrode 110a during the activation annealing. Further, since diffusion of extension impurities into the lower SiGe layer (first semiconductor layer 103) is suppressed, the junction depth of the p-type extension region 111a is set to the upper SiGe layer (second semiconductor layer 104). It can be as shallow as the thickness. As a result, the short channel characteristics can be improved while suppressing the occurrence of reverse short channel characteristics, and the threshold voltage reduction effect by applying the SiGe channel can be maintained even in a transistor having a short gate length. become.

  The formation conditions of the first semiconductor layer 103 and the second semiconductor layer 104, the p-type extension implantation region 111A, the n-type pocket implantation region 112A, and the p-type source / drain implantation region 114A described above are formed. Ion implantation conditions, activation annealing conditions, and the like are examples, and are not limited to these conditions.

In the above example, boron and arsenic are ion-implanted for the purpose of forming the p-type extension implantation region 111A and the n-type pocket implantation region 112A, respectively, but it is not limited thereto. In addition to boron, BF ₂ can be used as an impurity for forming the p-type extension region 111a. An example of the impurity for forming the n-type pocket region 112a is phosphorus.

  In the above description, a silicon oxide film is used as an example of the protective film 150. However, the protective film 150 is not limited to this as long as it prevents the SiGe layer from being deposited and can be easily removed. For example, a silicon nitride film can be used as the protective film 150. In this case, the protective film 150 can be removed by using hot phosphoric acid.

  In the step shown in FIG. 2B, the method of etching the P-type FET region of the semiconductor substrate 100 is described as an example in which the semiconductor substrate 100 is exposed to an HCl atmosphere at a high temperature, but is not limited thereto. For example, the semiconductor substrate 100 may be etched using a reactive ion etching method.

  Note that although an example in which a silicon oxide film is formed over the second semiconductor layer 104 has been described, a Si layer may be formed over the second semiconductor layer 104 by a CVD method or the like. By forming the Si layer, the film quality of the silicon oxide film 105a can be improved as compared with the case where the silicon oxide film 105a is formed over the second semiconductor layer 104, and deterioration of mobility and the like can be suppressed. it can. However, if the Si layer is too thick, a channel is formed in the Si layer and the effect of reducing the threshold voltage is reduced. Therefore, the thickness of the Si layer is desirably 3 nm or less.

  Although a method for manufacturing a P-type FET has been described here, when a CMOS structure is formed, an N-type FET having a known silicon channel is formed on the same substrate as the P-type FET as shown in FIG. It is desirable to do.

-Modification of n-type impurity region-
In the semiconductor device shown in FIG. 1A, the concentration of the n-type impurity contained in the portion of the n-type impurity region 152 located below the p-type extension region 111a is such that the gate electrode 110a of the n-type impurity region 152 It is higher than the concentration of the n-type impurity contained in the portion located below. On the other hand, a semiconductor device in which the impurity concentration in the portion of the n-type impurity region 152 provided in the first semiconductor layer 103 is substantially uniform will be described below.

  FIG. 5A is a cross-sectional view showing a modification of the semiconductor device shown in FIG. In this figure, the same or corresponding layers or members as those of the semiconductor device shown in FIG.

  As shown in FIG. 5A, in the semiconductor device according to this modification, as in the semiconductor device shown in FIG. 1A, the first semiconductor layer 103 made of SiGe is formed on the active region 102a of the semiconductor substrate 100. And a second semiconductor layer 104 made of SiGe having a Ge concentration lower than that of the first semiconductor layer 103 is provided. However, the spread of the n-type impurity region 152 to the second semiconductor layer 104 and the semiconductor substrate 100 is smaller than that of the semiconductor device shown in FIG. This is because, as will be described later, since in-situ doping is performed using a CVD method, impurities can be introduced with good controllability. In addition, the concentration of the n-type impurity contained in the portion of the n-type impurity region 152 formed in the first semiconductor layer 103 is almost uniform although there is some variation due to thermal diffusion. In particular, the impurity concentration in the n-type impurity region 152 in the first semiconductor layer 103 and below the gate electrode 110a is uniform.

The n-type impurity concentration of the first semiconductor layer 103 is, for example, 3 × 10 ¹⁸ atoms / cm ³ , and the n-type impurity concentration in the n-type upper SiGe layer 204 is, for example, 1 × 10 ¹⁷ atoms / cm ³ . As described above, the n-type impurity concentration in the n-type upper SiGe layer 204, which is a portion located below the gate electrode 110 a in the second semiconductor layer 104, is greater than the n-type impurity concentration in the first semiconductor layer 103. It can be low. The n-type impurity contained in the n-type impurity region 152 (and the first semiconductor layer 103) is, for example, arsenic, but may be phosphorus.

  FIG. 5B is a diagram showing the relationship between the gate length and the threshold voltage in the semiconductor device according to this variation and the conventional semiconductor device. In this figure, (1) the semiconductor device of this modification in which a gate electrode is provided on the laminated SiGe layer shown in FIG. 5A, and (2) a conventional semiconductor device in which a gate electrode is provided on a single-layer SiGe layer. And (3) a simulation result for a conventional semiconductor device in which a gate electrode is provided on a general Si substrate.

  Also in this configuration, since the channel is formed in the second semiconductor layer 104 made of SiGe, the threshold voltage can be greatly reduced as compared with the semiconductor device having the Si channel (see FIG. 5B). . In addition, the portion of the n-type impurity region 152 located below the p-type extension region 111a has a threshold voltage abrupt as the gate length is shortened, similar to the n-type pocket region 112a shown in FIG. Short channel effects such as a significant decrease and the generation of a leakage current between the source and drain can be effectively suppressed. This can be seen from FIG. 5B that if the gate length Lg is greater than or equal to a predetermined value, the threshold voltage variation is much smaller than that of the conventional semiconductor device over a wide gate length range. .

  In addition, since the Ge concentration of the second semiconductor layer 104 is lower than the Ge concentration of the first semiconductor layer 103, the amount of n-type impurities diffused into the second semiconductor layer 104 is small. Similar to the semiconductor device shown in FIG. 1A, the reverse short channel characteristics are improved (see FIG. 5B). Further, since the diffusion amount of the p-type impurity into the first semiconductor layer 103 is also relatively small, the depth of the junction between the p-type extension region 111a and the n-type impurity region 152 is compared with the conventional semiconductor device. Can be shallow.

  Note that the semiconductor device according to this modification has substantially the same configuration as that of the semiconductor device shown in FIG. For example, the gate insulating film 107a is composed of a silicon oxide film 105a having a thickness of 1 nm and a high dielectric constant insulating film 106a having a thickness of 2 nm, the gate electrode 110a is made of TiN, and the lower gate electrode 108a having a thickness of 10 nm. And an upper gate electrode 109a made of polysilicon and having a thickness of 100 nm.

  The width of the gate electrode 110a in the gate length direction is 40 nm, and the width of the sidewall spacer 113a provided on the side surface of the gate electrode 110a is 40 nm. Further, the Ge concentration in the first semiconductor layer 103 is 50%, and the Ge concentration in the second semiconductor layer 104 is 25%.

  The film thickness of the first semiconductor layer 103 is, for example, 10 nm, and the film thickness of the second semiconductor layer 104 is, for example, 20 nm. The depth of the junction between the p-type extension region 111 a and the n-type impurity region 152 is 20 nm from the upper surface of the second semiconductor layer 104, which is approximately the same as the thickness of the second semiconductor layer 104.

-Manufacturing method of semiconductor device according to modification-
6A to 6C and FIGS. 7A to 7C are cross-sectional views schematically showing a method for manufacturing a semiconductor device according to this modification.

  First, by forming an n-well region 100a in an n-type semiconductor substrate 100 made of silicon or the like by a process similar to the process shown in FIG. 2A, an element isolation region (not shown) is formed. An active region 102a is formed.

Next, as shown in FIG. 6A, arsenic is added to the active region 102a of the semiconductor substrate 100 at a concentration of, for example, 3 × 10 ¹⁸ atoms / cm ³ , is made of SiGe, and has a thickness of 10 nm. The semiconductor layer 103 and the second semiconductor layer 104 made of non-doped SiGe and having a thickness of 20 nm are sequentially epitaxially grown. For example, the Ge concentration in the first semiconductor layer 103 is 50%, and the Ge concentration in the second semiconductor layer 104 is 25%. The epitaxial growth of the first semiconductor layer 103 and the second semiconductor layer 104 is performed by, for example, a CVD method.

For example, monosilane (SiH ₄ ) is used as the silicon-based source gas. As germanium-based source gas, for example, monogermane (GeH ₄ ) is used. Using these mixed gases, a SiGe layer is deposited under conditions of 550 ° C. in an atmosphere of hydrogen or nitrogen gas. The Ge concentration is adjusted by controlling the flow rate of the germanium-based source gas during deposition. By increasing the flow rate of the germanium-based source gas, a SiGe layer containing Ge at a higher concentration is formed.

In addition, introduction of n-type impurities into the first semiconductor layer 103 is performed by in-situ doping using the CVD method. Specifically, arsenic is added into the first semiconductor layer 103 by adding arsine (AsH ₃ ) as a doping gas in addition to monosilane and monogermane when the SiGe layer constituting the first semiconductor layer 103 is deposited. Doping.

  Next, as shown in FIG. 6B, a gate insulating film 107a and a gate electrode 110a are formed.

  Specifically, the surface of the second semiconductor layer 104 is oxidized with ozone to form a 1 nm-thickness silicon oxide film, and the silicon oxide film is formed of a 2 nm-thick hafnium oxide or the like. A dielectric insulating film is formed. Subsequently, a TiN film having a thickness of 10 nm is formed on the high dielectric constant insulating film, and a polysilicon film having a thickness of 100 nm is formed thereon.

  After that, by performing resist patterning and dry etching, a gate insulating film 107a composed of a silicon oxide film 105a and a high dielectric constant insulating film 106a, and a gate electrode 110a composed of a lower gate electrode 108a and an upper gate electrode 109a Form. The gate dimension (gate length) of the gate electrode 110a is, for example, 40 nm.

Next, as shown in FIG. 6C, by using the gate electrode 110a as a mask, boron is implanted into the second semiconductor layer 104, thereby forming a p-type extension implantation region 111A. In this step, boron ion implantation is performed under the conditions of an acceleration energy of 0.5 keV, a dose of 5 × 10 ¹⁴ atoms / cm ² , and a tilt angle of 0 degree (implantation depth Rp = 4 nm). Thereby, the p-type extension implantation region is mainly formed in the second semiconductor layer 104 in the upper layer portion.

  Next, as shown in FIG. 7A, after a silicon nitride film having a thickness of about 40 nm is formed on the substrate (semiconductor device being fabricated), the entire surface is etched back by dry etching, so that the gate electrode is formed. A side wall spacer 113a made of a silicon nitride film having a width of 40 nm is formed on the side surface.

Next, as shown in FIG. 7B, a p-type source / drain implanted region 114A is formed by implanting p-type impurities into the active region 102a using the gate electrode 110a and the sidewall spacer 113a as a mask. Boron is used as an impurity for implantation, and ion implantation is performed under conditions of an acceleration energy of 1.5 keV and a dose of 4 × 10 ¹⁵ atoms / cm ² , so that the first semiconductor layer 103, the second semiconductor layer 104, and A p-type source / drain implantation region 114 A is formed on the semiconductor substrate 100.

  Next, as shown in FIG. 7C, spike annealing is performed under the conditions of 1000 ° C. and 0 seconds to activate the impurities introduced by ion implantation. By this annealing, boron in the p-type extension implantation region 111A is diffused to form the p-type extension region 111a. Also, the p-type source / drain implantation region 114A becomes a p-type source / drain region 114a. An n-type impurity region 152 is formed by diffusing the n-type impurity contained in the first semiconductor layer 103 to the periphery. Note that the depth of the junction between the p-type extension region 111a and the n-type impurity region 152 from the upper surface of the second semiconductor layer 104 is approximately the same as the thickness of the second semiconductor layer 104 (for example, about 20 nm). . This is because since the Ge concentration in the first semiconductor layer 103 is high, diffusion of boron into the first semiconductor layer 103 is suppressed.

  Further, the n-type impurity is diffused from the first semiconductor layer 103 to form the n-type upper SiGe layer 204 in the portion of the second semiconductor layer 104 located immediately below the gate electrode 110a by the heat treatment in this step. The

  According to the above method, in the step shown in FIG. 6A, since the n-type impurity is introduced into the first semiconductor layer 103 in the SiGe layer at a uniform concentration only by the in-situ doping, there is a variation in implantation. And crystal defects hardly occur. Therefore, the diffusion of n-type impurities into the upper surface portion of the second semiconductor layer 104 is suppressed, and the occurrence of the reverse short channel effect is effectively prevented. Therefore, the n-type impurity region 152 functioning as a pocket region can be further away from the upper surface of the second semiconductor layer 104 than the semiconductor device shown in FIG.

  Note that the method of introducing n-type impurities by ion implantation has a depth variation (ΔRp) with respect to the target implantation depth (Rp), and further defects in the semiconductor substrate 100 due to damage during ion implantation. May occur. On the other hand, in the method according to this modification, variations in the formation position of the n-type impurity region 152 functioning as the n-type pocket region can be suppressed.

  Further, as described above, since the depth of the junction between the p-type extension region 111a and the n-type impurity region 152 can be reduced, the short channel characteristics are also greatly improved. Therefore, the effect of reducing the threshold voltage by forming a channel in the SiGe layer can be maintained even in a transistor with a shortened gate length.

  Note that the thickness of each layer, the Ge concentration in the first semiconductor layer 103 and the second semiconductor layer 104, the n-type impurity concentration, and the like are not limited to the above-described examples, and the threshold voltage and short channel characteristics to be set It can be arbitrarily selected according to the degree of deterioration.

  Further, according to the above method, since the n-type impurity is introduced into the first semiconductor layer 103 by in-situ doping in the step shown in FIG. 6A, the n-type impurity is introduced by ion implantation. Compared to the case, the position and concentration of the n-type impurity region 152 can be controlled with higher accuracy. As a result, the short channel characteristics can be improved with higher accuracy than the semiconductor device shown in FIG.

  In addition, the thickness of the second semiconductor layer 104 is set to be approximately the same as the depth of the junction between the p-type extension region 111a and the n-type impurity region 152, and diffusion of extension impurities into the first semiconductor layer 103 is suppressed. As a result, the short channel characteristics can be further improved.

  The Ge concentration in the first semiconductor layer 103 may be more than 0% and not more than 100%. If the Ge concentration in the second semiconductor layer 104 is lower than the Ge concentration in the first semiconductor layer 103, the Ge concentration is 0. % Or more and less than 100%. However, from the viewpoint of threshold voltage reduction, the Ge concentration of the second semiconductor layer 104 is preferably 10% or more. Further, from the viewpoint of suppressing the diffusion of n-type impurities into the lower region of the gate electrode 110a and shallowing the junction position of the p-type extension region 111a with the n-type impurity region 152, the Ge concentration in the first semiconductor layer 103 is It is desirable that the Ge concentration in the second semiconductor layer 104 be 10% or higher. The film thickness of the first semiconductor layer 103 is preferably in the range of 5 nm to 20 nm in order to maintain the effect of suppressing the short channel characteristics by the n-type impurity region 152.

  In the above example, the p-type extension region 111a is formed in the second semiconductor layer 104. However, the peak position of the impurity concentration at the position where the p-type extension region 111a is formed is not limited to this. For example, the p-type extension region 111 a may be formed not only in the second semiconductor layer 104 but also in the first semiconductor layer 103.

  In the above-described method, the example in which the n-type impurity for suppressing the short channel effect is substantially uniformly included in the first semiconductor layer 103 has been described. However, in-situ doping of n-type impurity, ion implantation, You may carry out in combination. In this case, ion implantation of n-type impurities may be performed before and after the formation of the p-type extension implantation region 111A shown in FIG. Thereby, the position of the n-type impurity region 152 or the n-type pocket region and the freedom of setting the impurity concentration are increased, and the impurity distribution and the like can be easily optimized.

  In the above example, the silicon oxide film 105a is formed on the second semiconductor layer 104. However, after forming a thin Si layer epitaxially grown on the second semiconductor layer 104, for example, A silicon oxide film may be formed thereon. By forming the Si layer, the film quality of the silicon oxide film 105a can be improved, and it is possible to suppress deterioration of characteristics of the P-type FET such as mobility deterioration. However, if the Si layer is too thick, a channel is formed not only in the second semiconductor layer made of SiGe but also in the Si layer, and the threshold voltage reduction effect is reduced. For this reason, it is desirable that the thickness of the Si layer exceeds 0 nm and is 3 nm or less.

  In addition, the strain state of the first semiconductor layer 103 and the second semiconductor layer 104 is not particularly limited, but appropriate strain is applied to both layers in order to effectively reduce the threshold voltage. Is desirable.

  Further, the constituent materials and film thicknesses of the silicon oxide film 105a, the high dielectric constant insulating film 106a, the lower gate electrode 108a, the upper gate electrode 109a, the sidewall spacer 113a, and the like are not limited to the contents described above. The configuration of these members does not affect the effect obtained by the configuration of the present embodiment.

  In the above description, the P-type FET has been described. However, when a CMOS structure is formed, an N-type FET having a channel region made of Si is used as a P-type as in the semiconductor device shown in FIG. It is desirable to provide it on the same semiconductor substrate as the FET. In this case, the first semiconductor layer 103 and the second semiconductor layer 104 made of SiGe may be selectively formed on the P-type FET region by the steps shown in FIGS.

  Note that the formation conditions of the first semiconductor layer 103 and the second semiconductor layer 104 described above, the ion implantation conditions for forming the p-type extension implantation region 111A and the p-type source / drain implantation region 114A, and activation annealing. The conditions and the like are examples, and are not limited to these conditions.

In the above description, boron is ion-implanted to form the p-type extension region 111a. However, other ions may be implanted. For example, BF ₂ may be injected instead of boron. In addition, although arsine is used as a doping gas when forming the first semiconductor layer 103, phosphine (PH ₃ ) may be used without being limited thereto.

  As described above, the semiconductor device according to the above-described embodiment and its modification is used for an integrated circuit including a P-type FET that has been miniaturized.

100 semiconductor substrate 100a n-well region 100b p-well region 101 element isolation regions 102a and 102b active region 103 first semiconductor layer 103a n-type lower SiGe layer 104 second semiconductor layer 104a n-type upper SiGe layers 105, 105a and 105b silicon Oxide films 106, 106a, 106b High dielectric constant insulating films 107a, 107b Gate insulating films 108 TiN films 108a, 108b Lower gate electrodes 109 Polysilicon films 109a, 109b Upper gate electrodes 110a, 110b Gate electrodes 111A p-type extension implantation regions 111a p Type extension region 111b n type extension region 112A n type pocket implantation region 112a n type pocket region 112b p type pocket regions 113a and 113b Side wall spacer 114 p-type source / drain implant region 114a p-type source / drain regions 114b n-type source / drain regions 150 protective film 151 Si etch 152 n-type impurity regions 204 n-type upper SiGe layer

Claims (17)

A semiconductor device comprising a P-channel transistor formed on a semiconductor substrate,
The P-channel transistor is
A first semiconductor layer formed on the semiconductor substrate and containing germanium;
A second semiconductor layer formed on the first semiconductor layer and containing germanium at a lower concentration than the first semiconductor layer;
A first gate electrode formed on the second semiconductor layer with a first gate insulating film interposed therebetween;
A p-type first extension region formed in a portion of the second semiconductor layer located on both sides of the first gate electrode;
A semiconductor device having at least an n-type impurity region provided in the first semiconductor layer and formed below the first extension region. The semiconductor device according to claim 1,
The n-type impurity region is provided from under one of the first extension regions through a region under the first gate electrode and under the other first extension region,
The n-type impurity concentration of the portion of the first semiconductor layer located below the first extension region is the n-type impurity concentration of the portion of the first semiconductor layer located below the first gate electrode. A semiconductor device with a higher impurity concentration. The semiconductor device according to claim 2,
The n-type impurity region extends to a lower portion of the second semiconductor layer;
A portion of the n-type impurity region provided below the second semiconductor layer has an n-type impurity concentration below the first extension region of the n-type impurity region and the first semiconductor layer. A semiconductor device having an n-type impurity concentration lower than that of a portion provided therein. The semiconductor device according to claim 1,
The n-type impurity region is provided from below one of the first extension regions to below the first gate electrode and below the other first extension region,
A semiconductor device in which an n-type impurity concentration in a portion of the n-type impurity region provided in the first semiconductor layer is substantially uniform. In the semiconductor device according to any one of claims 1 to 4,
A semiconductor device in which strain is applied to the first semiconductor layer and the second semiconductor layer. In the semiconductor device according to any one of claims 1 to 5,
A semiconductor device in which an atomic concentration of germanium in the second semiconductor layer is 10% or more. In the semiconductor device according to claim 1,
A semiconductor device in which an atomic concentration of germanium in the first semiconductor layer is 10% or more higher than an atomic concentration of germanium in the second semiconductor layer. In the semiconductor device according to any one of claims 1 to 7,
A semiconductor device in which the film thickness of the first semiconductor layer is not less than 5 nm and not more than 20 nm. In the semiconductor device according to claim 1,
The P-channel transistor further includes a third semiconductor layer made of silicon provided between the second semiconductor layer and the first gate insulating film. The semiconductor device according to claim 9.
A semiconductor device in which the film thickness of the third semiconductor layer is 3 nm or less. In the semiconductor device according to claim 1,
A second gate electrode formed on the semiconductor substrate with a second gate insulating film interposed therebetween; and an n-type formed on a portion of the semiconductor substrate located on both sides of the second gate electrode. A semiconductor device further comprising an N-channel transistor including the second extension region. The semiconductor device according to claim 11,
A portion of the semiconductor substrate located below the second gate electrode is a semiconductor device made of silicon. In the semiconductor device according to any one of claims 1 to 12,
The first gate insulating film includes a high dielectric constant insulator material;
The first gate electrode includes a lower gate electrode made of metal or a conductive metal compound, and an upper gate electrode made of polysilicon and provided on the lower gate electrode. The semiconductor device according to any one of claims 1 to 13,
The thickness of the second semiconductor layer is a semiconductor device equal to the depth of the junction position between the first extension region and the n-type impurity region. Forming a first semiconductor layer containing germanium on a semiconductor substrate;
Forming a second semiconductor layer containing germanium at a lower concentration than the first semiconductor layer on the first semiconductor layer;
Forming a gate electrode on the second semiconductor layer with a gate insulating film interposed therebetween;
Implanting p-type impurity ions into the second semiconductor layer using the gate electrode as a mask to form an extension implantation region;
Applying heat treatment to the semiconductor substrate to activate impurities in the extension implantation region, and forming a p-type extension region in regions of the second semiconductor layer located on both sides of the gate electrode; A method for manufacturing a semiconductor device comprising: In the manufacturing method of the semiconductor device according to claim 15,
After forming the gate electrode and before forming the extension region, the method further comprises a step of implanting n-type impurity ions into the first semiconductor layer using the gate electrode as a mask to form a pocket implantation region.
In the extension region forming step, an n-type impurity in the pocket implantation region is activated to form an n-type impurity region in the first semiconductor layer and below the extension region. Production method. In the manufacturing method of the semiconductor device according to claim 15,
When forming the first semiconductor layer, n-type impurities are introduced by in-situ doping,
In the extension region forming step, the extension region is formed on the first semiconductor layer which is an n-type impurity region.

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