CN115103531A - Production process of multi-layer PCB (printed circuit board) of refined circuit - Google Patents
Production process of multi-layer PCB (printed circuit board) of refined circuit Download PDFInfo
- Publication number
- CN115103531A CN115103531A CN202210758580.5A CN202210758580A CN115103531A CN 115103531 A CN115103531 A CN 115103531A CN 202210758580 A CN202210758580 A CN 202210758580A CN 115103531 A CN115103531 A CN 115103531A
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- China
- Prior art keywords
- clad plate
- sided copper
- copper
- via hole
- hole
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/429—Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4614—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
- H05K3/4617—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination characterized by laminating only or mainly similar single-sided circuit boards
Abstract
The invention belongs to the generation and manufacturing of circuit boards, and particularly discloses a production process of a multi-layer PCB of a refined circuit, which comprises the following steps: step S1: processing a first via hole on the first single-sided copper-clad plate; step S2: coating a layer of conductive film on the first single-sided copper-clad plate; step S3: processing a second via hole on the first single-sided copper-clad plate; step S4: conducting treatment; step S5; copper plating treatment; s6: micro-etching treatment; step S7: stripping the conductive film; step S8: coating a layer of conductive film on the second single-sided copper-clad plate; step S9: processing a third via hole on the second single-sided copper-clad plate; step S10: superposing a second single-sided copper-clad plate on the first single-sided copper-clad plate, and keeping the third via hole aligned with the first via hole to form a via hole group; step S11: conducting treatment; step S12: copper plating treatment; step S13: micro-etching treatment; step S14: and stripping the conductive film. The invention can realize one-step electroplating molding of the through hole, and has good plating layer structure and better conductivity.
Description
Technical Field
The invention relates to the technical field of PCB manufacturing, in particular to a production process of a multi-layer PCB of a refined circuit.
Background
With the rapid development of the 5G technology, the multilayer circuit board develops towards the direction of fine circuits, and the requirements on the performance of the circuits such as line width, distance and the like are higher and higher. In the process of manufacturing the through hole of the refined circuit, the through hole of the upper layer plate is subjected to conductive and copper plating treatment, and the through hole which does not need to be plated also forms a part of electroplated layer, so that the layering phenomenon is easy to occur during the electroplating treatment of the combined hole, and the conductive performance of the through hole is reduced.
Disclosure of Invention
The invention aims to provide a production process of a multi-layer PCB of a refined circuit, which can realize one-step electroplating forming of a through hole, and has good plating layer structure and better conductivity.
The invention is realized by the following technical scheme:
a production process of a multi-layer PCB of a refined circuit comprises the following steps:
step S1: processing a first via hole on the first single-sided copper-clad plate;
step S2: coating a layer of conductive film on the first single-sided copper-clad plate;
step S3: processing a second via hole on the first single-sided copper-clad plate;
step S4: conducting treatment, namely attaching a conducting substance on the hole wall of the second conducting hole;
step S5; copper plating treatment is carried out, so that the inner wall of the second via hole is plated into a copper hole;
step S6: carrying out micro-etching treatment to remove copper deposited on the conductive film;
step S7: stripping the conductive film;
step S8: coating a layer of conductive film on the second single-sided copper-clad plate;
step S9: processing a third via hole on the second single-sided copper-clad plate;
step S10: superposing a second single-sided copper-clad plate on the first single-sided copper-clad plate, and keeping the third via hole aligned with the first via hole to form a via hole group;
step S11: conducting treatment, namely attaching a conducting substance on the hole wall of the communicating hole group;
step S12: copper plating treatment is carried out, so that the inner wall of the communicating hole group is electroplated into a copper hole;
step S13: carrying out micro-etching treatment to remove copper deposited on the conductive film;
step S14: and stripping the conductive film.
Optionally, before step S1, the method further includes dry film lamination, exposure, development, etching and film stripping for each single-sided copper-clad plate.
Optionally, the Cu wire line width of each single-sided copper-clad plate: more than or equal to 75 um;
cu wire spacing: more than or equal to 75 um;
thickness of the Cu wire: less than or equal to 18 um;
thickness: 0.2 mm.
Optionally, in step S10, before the second single-sided copper-clad plate is superimposed on the first single-sided copper-clad plate, the resin layer is coated around the orifice of the first via hole of the first single-sided copper-clad plate, then the second single-sided copper-clad plate is superimposed on the first single-sided copper-clad plate, and then the second single-sided copper-clad plate is placed into a freezing device for freezing treatment, so that the resin is solidified, and then the resin layer is subjected to hole breaking treatment by a drilling device, and then an air draft device is arranged above the via hole group to suck the resin waste residue generated during drilling.
Optionally, the thickness of the resin layer is 0.1-0.2 mm.
The technical scheme of the invention at least has the following beneficial effects:
according to the invention, the through holes formed by the independent holes and the through holes formed by the combined holes are respectively processed before and after the film is coated, so that the through holes formed by the combined holes are not coated when the through holes formed by the independent holes are electroplated, and thus, after the combined holes are formed at the later stage, the integrity of the holes can be ensured when one-step electroplating forming is realized, the layering phenomenon is avoided, and the good conductivity is ensured.
Drawings
FIG. 1 is a schematic structural diagram of a production process of a multi-layer PCB board with a refined circuit of the present invention;
icon: 100-a first single-sided copper-clad plate, 101-a first via hole, 110-a conductive film, 102-a second via hole, 200-a second single-sided copper-clad plate, 203-a third via hole, and 210-a conductive film.
Detailed Description
Example 1
A production process of a multi-layer PCB of a refined circuit comprises the following steps: the processing of the single-sided copper-clad plate is realized by the pretreatment processes of dry film pressing, exposure, development, etching and film stripping of each single-sided copper-clad plate, specific process parameters and process equipment are realized by utilizing the conventional technology in the field, and the embodiment is not described in detail. After the pretreatment process is completed, the following process steps are performed, referring to fig. 1, which specifically include:
step S1: the first via hole 101 is processed on the first single-sided copper-clad plate 100, and the via hole can be processed by adopting a mechanical drilling or laser drilling mode.
Step S2: a layer of conductive film 110 is coated on the first single-sided copper-clad plate 100.
Step S3: the second via hole 102 is processed on the first single-sided copper-clad plate 100, and the processing method of the second via hole 102 is the same as that of the first via hole 101.
Step S4: the conductive treatment is performed to attach a conductive material to the hole wall of the second via hole 102.
Step S5; the copper plating process is performed such that the inner wall of the second via hole 102 is plated with a copper hole.
Step S6: and microetching to remove copper deposited on the conductive film 110.
Step S7: the conductive film 110 is peeled off.
Step S8: and coating a conductive film 210 on the second single-sided copper-clad plate 200.
Step S9: and processing a third via hole 203 on the second single-sided copper-clad plate 200.
Step S10: and superposing the second single-sided copper-clad plate 200 on the first single-sided copper-clad plate 100, and keeping the third via hole 203 aligned with the first via hole 101 to form a via hole group.
Step S11: and (3) conducting treatment, namely attaching a conducting substance on the hole wall of the communicating hole group.
Step S12: and (4) copper plating treatment, so that the inner wall of the communicating hole group is electroplated into a copper hole.
Step S13: microetching removes the copper deposited on the conductive film 210.
Step S14: the conductive film 210 is peeled off.
According to the invention, through manufacturing the via hole on the first single-sided copper-clad plate 100, namely the next layer of plate material, different processing technologies are selected according to different types of the via hole, the first via hole 101 is processed in advance before being coated with the conductive film 110, so that the first via hole can be covered after being coated with the conductive film, and the second via hole 102 is processed after being coated with the film, so that the electroplating effect can be prevented from being influenced by the fact that the second via hole 102 is covered by the conductive film 110 during hole plating, meanwhile, the conductive film 110 is covered, and meanwhile, the first via hole 101 can be ensured not to be electroplated during plating of the second via hole 102. If a partial plating phenomenon occurs in the first via hole 101, a double plating layer is likely to occur when a via group is subsequently formed and then plating is performed, and a separation phenomenon is likely to occur, resulting in a problem that the conductivity of a plated hole is decreased. Therefore, in the first processing, the first via hole 101 and the second via hole 102 are realized by the pre-film coating processing and the post-peritoneum processing, respectively. After the first single-sided copper-clad plate 100 and the second single-sided copper-clad plate 200 are overlapped, the connecting hole group is electroplated, so that the completeness of a plating layer is effectively guaranteed, and the conductivity is good.
Example 2:
because the precision of the exposure machine is greatly improved, the exposure effect is deteriorated at the sharp position of the graph due to the diffraction facula phenomenon, and partial shadow areas which are not exposed are also irradiated by the light source, so that the chamfer position of the graph is distorted. For such distortion phenomena, in this embodiment, on the basis of embodiment 1, design research in terms of optical exposure compensation is considered in the film design stage, and the diffraction region is changed by modifying the exposure window design, so as to improve the pattern etching accuracy. The wire width of each Cu wire of the single-sided copper-clad plate is as follows: more than or equal to 75 um; cu wire spacing: more than or equal to 75 um; thickness of the Cu wire: less than or equal to 18 um; thickness: 0.2 mm.
Example 3:
on the basis of the embodiment 1, in step S10, before the second single-sided copper-clad plate 200 is superimposed on the first single-sided copper-clad plate 100, a resin layer is coated around the orifice of the first via hole 101 of the first single-sided copper-clad plate 100, then the second single-sided copper-clad plate 200 is superimposed on the first single-sided copper-clad plate 100, then the first single-sided copper-clad plate is placed into a freezing device for freezing treatment to solidify the resin, then the resin layer is subjected to hole breaking treatment by a drilling device, then an air draft device is arranged above the group of via holes, and resin waste residues generated during drilling are sucked. According to the embodiment, the resin layer is coated near the orifice, the thickness of the resin layer is 0.1-0.2mm, then the other single-sided copper-clad plate is overlapped, so that a compact structure can be formed at the connection part of the via holes of the two copper-clad plates, after cold-moving treatment, the resin can be quickly solidified, then holes are repaired by matching drilling equipment with air draft equipment, and then electroplating treatment is carried out, so that the integrity of the holes can be ensured, on one hand, the resin can play an insulating role, the interlayer part has good insulating property, especially for PCB (printed circuit board) of fine circuits, the circuit spacing is narrow, and if the defects of copper holes appear at the interlayer position after hole forming, the phenomena such as short circuit and the like at the position are easily caused; in addition, after the resin is molded, the holes and the interlayer are relatively isolated, the molded hole structure is more regular, and the conductive performance of the copper holes is also favorably ensured.
Claims (5)
1. A production process of a multi-layer PCB of a refined circuit is characterized by comprising the following steps:
step S1: processing a first via hole on the first single-sided copper-clad plate;
step S2: coating a layer of conductive film on the first single-sided copper-clad plate;
step S3: processing a second via hole on the first single-sided copper-clad plate;
step S4: conducting treatment, namely attaching a conducting substance on the hole wall of the second conducting hole;
step S5; copper plating treatment is carried out, so that the inner wall of the second via hole is plated into a copper hole;
step S6: carrying out micro-etching treatment to remove copper deposited on the conductive film;
step S7: stripping the conductive film;
step S8: coating a layer of conductive film on the second single-sided copper-clad plate;
step S9: processing a third via hole on the second single-sided copper-clad plate;
step S10: superposing a second single-sided copper-clad plate on the first single-sided copper-clad plate, and keeping the third via hole aligned with the first via hole to form a via hole group;
step S11: conducting treatment, namely attaching a conducting substance to the hole wall of the communicating hole group;
step S12: copper plating treatment is carried out, so that the inner wall of the communicating hole group is electroplated into a copper hole;
step S13: carrying out micro-etching treatment to remove copper deposited on the conductive film;
step S14: and stripping the conductive film.
2. The process for producing a multi-layer PCB board for refined circuits as recited in claim 1, further comprising, before step S1, dry film pressing, exposing, developing, etching and stripping each single-sided copper-clad board.
3. The production process of the multi-layer PCB board for the refined circuit as claimed in claim 1, wherein the line width of the Cu conducting wire of each single-sided copper-clad plate is as follows: more than or equal to 75 um;
cu wire spacing: more than or equal to 75 um;
thickness of the Cu wire: less than or equal to 18 um;
thickness: 0.2 mm.
4. The production process of the multi-layer PCB for the refined circuit as claimed in claim 1, wherein in step S10, before the second single-sided copper-clad plate is overlaid on the first single-sided copper-clad plate, the resin layer is coated around the hole of the first via hole of the first single-sided copper-clad plate, then the second single-sided copper-clad plate is overlaid on the first single-sided copper-clad plate, then the first single-sided copper-clad plate is placed into a freezing device for freezing treatment to solidify the resin, then the hole of the resin layer is broken through a drilling device, then an air draft device is arranged above the set of via holes, and the resin waste residue generated during drilling is sucked.
5. The process for producing a multi-layer PCB board with refined circuits as claimed in claim 4, wherein the thickness of the resin layer is 0.1-0.2 mm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210758580.5A CN115103531A (en) | 2022-06-30 | 2022-06-30 | Production process of multi-layer PCB (printed circuit board) of refined circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210758580.5A CN115103531A (en) | 2022-06-30 | 2022-06-30 | Production process of multi-layer PCB (printed circuit board) of refined circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN115103531A true CN115103531A (en) | 2022-09-23 |
Family
ID=83295216
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210758580.5A Pending CN115103531A (en) | 2022-06-30 | 2022-06-30 | Production process of multi-layer PCB (printed circuit board) of refined circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115103531A (en) |
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2022
- 2022-06-30 CN CN202210758580.5A patent/CN115103531A/en active Pending
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