CN115078977B - Diagnostic test device for analog circuit - Google Patents
Diagnostic test device for analog circuit Download PDFInfo
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- CN115078977B CN115078977B CN202210758358.5A CN202210758358A CN115078977B CN 115078977 B CN115078977 B CN 115078977B CN 202210758358 A CN202210758358 A CN 202210758358A CN 115078977 B CN115078977 B CN 115078977B
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/316—Testing of analog circuits
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y04—INFORMATION OR COMMUNICATION TECHNOLOGIES HAVING AN IMPACT ON OTHER TECHNOLOGY AREAS
- Y04S—SYSTEMS INTEGRATING TECHNOLOGIES RELATED TO POWER NETWORK OPERATION, COMMUNICATION OR INFORMATION TECHNOLOGIES FOR IMPROVING THE ELECTRICAL POWER GENERATION, TRANSMISSION, DISTRIBUTION, MANAGEMENT OR USAGE, i.e. SMART GRIDS
- Y04S10/00—Systems supporting electrical power generation, transmission or distribution
- Y04S10/50—Systems or methods supporting the power network operation or management, involving a certain degree of interaction with the load-side end user applications
- Y04S10/52—Outage or fault management, e.g. fault detection or location
Abstract
The invention is used for an analog circuit diagnosis detection device, an edge pulse compensation circuit receives preset edge pulses, the edge pulses are subjected to frequency multiplication and controllable delay under the triggering of a fault early warning signal, the edge pulses are added to a pin A of an OR gate Y2, a pin B of the OR gate Y2 is connected with pulses with regulated frequency at the position where a fault is located, a fault position pulse frequency modulation circuit receives signals output by a pulse detection circuit, when the pulse signals exist, the frequency of single frequency multiplication pulse at the position where the fault is located is changed by an oscillating circuit by the pulse frequency modulation circuit, the edge pulses after superposition compensation are output by the OR gate Y2, under the control of the pulse detection circuit, when the pulse signals exist, the pulse signals are closed by a delay trigger switch K1-2, the edge pulse feedback after superposition compensation is realized, and when the pulse signals do not exist, the thyristor VT2 which is conducted enters an oscilloscope, so that the full-scale sampling rate of the signals can be ensured, the sampling frequency can be locally increased, the storage depth can be met, and the interested signals can be selected.
Description
Technical Field
The invention belongs to the technical field of diagnosis and detection, and particularly relates to a diagnosis and detection device for an analog circuit.
Background
Because of inherent characteristics of continuous variable analog circuit element parameters, tolerance influence of element parameters, nonlinearity of circuit response and the like, the analog circuit fault diagnosis method is slow in development, the existing analog circuit fault diagnosis adopts an oscilloscope to collect analog circuit test point signals, then fault diagnosis and fault positioning are carried out according to experience or a built mathematical model, the oscilloscope accurately collects analog circuit test point signals to obtain the full view of the signals, especially the accurate restoration of the fault point signals is crucial, proper edge pulses are required to be set to ensure enough sampling rate, meanwhile, capturing and storing signals are triggered, the limitation of storage depth is met, and the signal of interest is selected, so that the analog circuit diagnosis detection device is required to be provided, the full view of the signals can be ensured, the storage depth can be met, and the signal of interest is selected.
Disclosure of Invention
Aiming at the situation, in order to overcome the defects of the prior art, the invention provides the diagnosis and detection device for the analog circuit, which is used for setting frequency multiplication sampling when a fault early warning signal exists, and carrying out oscillation frequency modulation on single frequency multiplication pulse of a fault position point, so that sufficient sampling rate can be ensured, the overall appearance of the signal can be obtained, the sampling frequency can be locally increased, the storage depth can be met, and the signal of interest can be selected.
The technical scheme is that the fault point detection circuit comprises an oscilloscope, wherein the oscilloscope captures an analog circuit detection signal under the triggering of an edge pulse, so that a fault point is detected and diagnosed, the edge pulse of the oscilloscope is generated by an edge pulse compensation circuit, a fault position pulse frequency modulation circuit and a pulse detection circuit, the edge pulse compensation circuit receives a preset edge pulse, an analog switch U1 acts under the triggering of a fault early warning signal, the edge pulse is doubled by a frequency doubling circuit, the pulse after the frequency doubling is delayed controllably by a pulse delay circuit, the pulse is added to a pin A of an OR gate Y2, a pin B of the OR gate Y2 is connected with a pulse with an adjusted frequency at the position of the fault output by the fault position pulse frequency modulation circuit, the pin Y of the OR gate Y2 outputs an edge pulse after superposition compensation, and the pulse detection circuit controls cyclic superposition compensation in a delayed mode and enters through a turned-on thyristor VT2 of the oscilloscope;
the fault position pulse frequency modulation circuit receives an output signal of the pulse detection circuit, the pulse signal triggers the switch K1-1 to be conducted, and after frequency multiplication of the position where the fault is located, the pulse enters an oscillating circuit formed by the D trigger U2, the U3 and the crystal oscillator U3, so that the oscillating circuit oscillates at the rising edge and the falling edge of a pulse frequency signal, the frequency of a single frequency multiplication pulse at the position where the fault is located is changed, and the single frequency multiplication pulse enters a pin B of the OR gate Y2;
the pulse detection circuit receives a fault position pulse signal, is detected by a pulse detection circuit consisting of NAND gates Y3 and Y4 as cores, when the pulse signal exists, the lower end of a resistor R7 discharges, an output voltage triggers a switch K1-1 to conduct, a switch K1-2 to conduct and a switch K1-3 to conduct, the frequency of a single frequency multiplication pulse at the position where the fault exists is controlled to be changed respectively, the time delay control cycle superposition compensation and the controllable time delay of a reset control pulse delay circuit are controlled, when no pulse signal exists, a capacitor C5 discharges, the switch K1-1, the switch K1-2 and the switch K1-3 are turned off, the NAND gate Y4 outputs a high level, and the single junction transistor T1 is triggered to conduct and the thyristor VT2 is triggered to conduct.
The invention has the beneficial effects that: the method comprises the steps that under the triggering of a fault early warning signal, an analog switch U1 acts, a normally open contact is opened, a normally closed contact is closed, the edge pulse is subjected to frequency multiplication through a frequency multiplication circuit and controlled to be delayed through a pulse delay circuit, the edge pulse is added to a pin A of an OR gate Y2, time delay of a pulse adjusting frequency at the position where a fault is located is controlled to be controlled, so that the pin A and the pin B of the OR gate Y2 are connected with signals synchronously, the pin B of the OR gate Y2 is connected with the pulse of the adjusted frequency at the position where the fault is located, the pin Y of the OR gate Y2 outputs superimposed compensation edge pulse, under the control of a pulse detection circuit, particularly, when the fault position pulse signal has a pulse signal, the edge pulse is fed back to a pin 1 of a NOT gate N4 through the non-gate N3, time delay is controlled to be compensated, the time delay control cycle superposition compensation is achieved, when the fault position pulse signal does not have the pulse signal, the conducted thyristor VT2 enters an oscilloscope, in order to achieve the purposes, when the fault early warning signal is in the presence, frequency multiplication sampling is set, the full-phase frequency multiplication sampling can be guaranteed, the fault position can be fully achieved, the fault position can be single, the frequency can be modulated, the local oscillation frequency can be increased, the local oscillation frequency can be stored, and the local oscillation frequency can be limited, and the local frequency can be stored.
Drawings
Fig. 1 is a schematic circuit diagram of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made more apparent and fully hereinafter with reference to the accompanying drawings, in which some, but not all embodiments of the invention are shown.
The following describes the present invention in further detail with reference to fig. 1 of the accompanying drawings.
The analog switch U1 with model MAX333 acts, the normally open contact is opened and the normally closed contact is closed under the triggering of the fault early warning signal, the edge pulse is buffered by the NOT gate N4 after the frequency multiplication, the time delay of the pulse delay circuit is controlled by the pin A of the OR gate Y2, the time delay of the position pulse adjusting frequency where the fault is carried out is controlled, so that the pin A and the pin B of the OR gate Y2 are kept synchronous, the pin B of the OR gate Y2 is connected with the pulse with the regulated frequency of the fault position output by the fault position pulse frequency modulation circuit, the pin Y of the OR gate Y2 outputs the superimposed and compensated edge pulse, under the control of the pulse detection circuit, particularly, when the fault position pulse signal has a pulse signal, the trigger switch K1-2 is closed after the delay of the NOT gate N2 and N3, the superimposed and compensated edge pulse is fed back to the pin 1 of the NOT gate N4, the delayed control cyclic superimposed and compensation is realized, when the fault position pulse signal has no pulse signal, the turned-on thyristor VT2 enters the oscilloscope, so that the implementation is realized, when the fault early warning signal exists, the frequency multiplication sampling is set, the enough sampling rate can be ensured, the full view of the signal is obtained, the oscillation frequency modulation is carried out on the single frequency multiplication pulse of the fault position point, the sampling frequency can be increased locally, the signal of interest is selected, and can meet the limit of storage depth;
the fault position pulse frequency modulation circuit receives a pulse detection circuit output signal, when a pulse signal exists, a trigger switch K1-1 is conducted, a frequency multiplication pulse at the position where a fault exists enters an oscillating circuit formed by a D trigger U2, a U3 and a crystal oscillator U3, so that the oscillating circuit oscillates at the rising edge and the falling edge of a pulse frequency signal, the frequency of a single frequency multiplication pulse at the position where the fault exists is changed, the frequency of the single frequency multiplication pulse 3 is set, namely the period of the single pulse is kept unchanged, the frequency is changed to be 3 times, the single frequency multiplication pulse enters a pin B of an OR gate Y2, the oscillating frequency modulation of the single frequency multiplication pulse at the fault position point is realized, the sampling frequency can be locally increased, the signal of interest is selected, and the limit of the storage depth can be met;
the pulse detection circuit receives fault position pulse signals, the fault position pulse signals are detected by a pulse detection circuit which is formed by taking NAND gates Y3 and Y4 as cores, when the pulse signals exist, the pulse is charged by a capacitor C4 and discharged by a resistor R7, the resistor R7 and the resistor R8 output voltage to trigger a switch K1-1 to be conducted, a switch K1-2 to be conducted in a delayed mode, and a switch K1-3 to be conducted, the frequency of single frequency multiplication pulse after the position of the fault is changed, the delay control cycle superposition compensation and the controllable delay of a reset control pulse delay circuit are respectively controlled, when no pulse signals exist, the capacitor C5 discharges, the switch K1-1, the switch K1-2 and the switch K1-3 are cut off, the NAND gate Y4 outputs a high level, the single transistor T1 is triggered to be conducted, the thyristor VT2 is conducted, and the edge pulse enters the oscilloscope after cathode output compensation of the thyristor VT 2.
In the above technical solution, the edge pulse compensation circuit receives preset edge pulses, under the triggering of a fault early warning signal (specifically, triggered by the high voltage and the low voltage output by the photoelectric coupler of the analog circuit fault diagnosis circuit), the analog switch U1 with model MAX333 is opened, the normally open contact is closed, the edge pulses are multiplied by the frequency multiplication circuit formed by the NOT gate N1, the NOT gate Y1, the resistor R2, the capacitors C1 and C2 and the varactor DC1, after the frequency multiplication, the edge pulses are buffered by the NOT gate N4, and then are controllably delayed by the pulse delay circuit formed by the NOT gate YF1, the NOT gate YF2, the resistor R4, the resistor R5, the capacitor C3, the electrolytic capacitor E1 and the varactor DC2, and applied to the pin a of the OR gate Y2, specifically, when the pulse signal is in the fault position, the switch K1-3 is closed, the reset circuit composed of the resistor R2, the resistor R3 and the switch K1-3 outputs a voltage division voltage, the voltage division voltage is reversely added to the cathode of the varactor DC2 through the resistor R5 and the electrolytic capacitor E1, the time delay of the pulse adjusting frequency at the position where the fault is located is controlled, so that the access signals of the pin A and the pin B of the OR gate Y2 are kept synchronous, the pin B of the OR gate Y2 is accessed to the pulse of the adjusting frequency at the position where the fault is located, which is output by the fault position pulse frequency modulation circuit, the pin Y of the OR gate Y2 outputs the superimposed compensation back edge pulse, under the control of the pulse detection circuit, in particular, when the fault position pulse signal has the pulse signal, the switch K1-2 is triggered by the time delay of the NOT gate N2 and N3, the superimposed compensation back edge pulse is fed back to the pin 1 of the NOT gate N4, the time delay control circulation superimposed compensation is realized, when the fault position pulse signal has no pulse signal, the turned on thyristor VT2 enters the oscilloscope, in this way, when a fault early warning signal exists, frequency multiplication sampling is set, enough sampling rate can be ensured, the overall appearance of the signal is obtained, oscillation frequency modulation is carried out on single frequency multiplication pulse at a fault position point, sampling frequency can be locally increased, a signal of interest is selected, and the limitation of storage depth can be met, the fault early warning signal detection circuit comprises an analog switch U1, a pin 3 of the analog switch U1 is connected with an edge pulse, a pin 1 of the analog switch U1 is connected with the fault early warning signal, a pin 2 of the analog switch U1 is respectively connected with one end of a capacitor C1 and a pin 1 of a NOT gate N1, the other end of the capacitor C1 is respectively connected with one end of a resistor R1 and the negative electrode of a varactor DC1, the positive electrode of the varactor DC1 is connected with a pin A of a NOT gate N1, the other end of the capacitor C2 is respectively connected with one end of a resistor R2 and a pin B of a NOT gate Y1, the other end of the resistor R1 and the other end of the resistor R2 are connected with a power supply +5V, a pin Y of the NOT gate Y1 is respectively connected with the lower end of the switch K1-2 and a pin 1 of the NOT gate N4, a pin 2 of the NOT gate N4 is connected with a pin A of the NOT gate YF1, a pin B of the NOT gate YF1 is respectively connected with one end of the grounding resistor R4 and one end of the capacitor C3, the other end of the capacitor C3 is respectively connected with the negative electrode of the varactor DC2, one end of the resistor R5 and the positive electrode of the grounding electrolytic capacitor E1, the other end of the resistor R5 is connected with the right end of the switch K1-3, a pin Y of the NOT gate YF1 is connected with pins A and B of the NOT gate YF2, a pin Y of the NOT gate YF2 is respectively connected with the positive electrode of the varactor DC2 and the pin A of the NOT gate Y2, a pin B of the NOT gate Y2 is connected with the Q end of the D trigger U4, a pin Y of the NOT gate Y2 is respectively connected with the upper end of the switch K1-2 and the positive electrode of the thyristor VT2, the cathode output of the thyristor VT2 compensates for the post-edge pulse.
In the above technical scheme, the fault location pulse frequency modulation circuit receives the output signal of the pulse detection circuit, when the pulse signal exists, the trigger switch K1-1 is turned on, the pulse after frequency multiplication at the location of the fault enters the oscillation circuit formed by the D trigger U2, the U3 and the crystal oscillator U3, the oscillation circuit oscillates at the rising edge and the falling edge of the pulse frequency signal, the frequency of the single frequency multiplication at the location of the fault is changed, the single frequency multiplication pulse 3 is set, namely the period of the single pulse is kept unchanged, the frequency becomes 3 times, the pulse enters the pin B of the OR gate Y2, the oscillation frequency modulation of the single frequency multiplication at the fault location point is realized, the sampling frequency can be locally increased, the limit of the storage depth can be met, the limit of the storage depth is met, the three-phase oscillation circuit comprises the D trigger U2, the D end of the D trigger U2 is connected with the negative electrode of the diode D2, the positive electrode of the diode D2 is connected with the power +5V, the CP end of the D trigger U2 is connected with the left end of the switch K1-1, the right end of the switch K1-1 is connected with the pin of the non-gate N4, namely the single pulse period is kept unchanged, the frequency is 3 times, the pin B is connected with the pin B of the end of the non-gate N4 is connected with the inductor U2, the end of the inductor C1 is connected with the end of the U2C 2 is connected with the end of the inductor C3, and one end of the C4 is connected with the end of the inductor C4 is connected with the C2, and the end of C4 is connected with the end of the C3 is connected with the end of the capacitor C3, and the C4 of the end of C3 is connected with the C3, and the C3 is connected with the C3.
In the above technical solution, the pulse detection circuit receives a fault location pulse signal (specifically, may be an analog circuit fault diagnosis circuit, a modulation pulse output by a first multiplier or a second multiplier), the pulse detection circuit is formed by taking a nand gate Y3 and Y4 as a core, when there is a pulse signal, the pulse is charged by a capacitor C4 and discharged through a resistor R7, the resistor R7 and the resistor R8 output voltage trigger a switch K1-1 to conduct, the switch K1-2 is delayed to conduct, the switch K1-3 is conducted, the frequency of a single frequency multiplication pulse after changing the position of the fault is controlled respectively, the delay control cycle superimposes compensation, the reset control pulse delay circuit is controlled to delay, when there is no pulse signal, the capacitor C5 discharges, the switch K1-1, the switch K1-2, the switch K1-3 is turned off, the nand gate Y4 outputs a high level, the single transistor T1 is triggered to conduct, the thyristor VT2 is turned on, the cathode output compensated edge pulse of the thyristor VT2 enters an oscilloscope, one end of the capacitor C4 is connected with the fault location pulse signal, the other end of the capacitor C4 is connected with a pin a terminal of the nand gate Y3 and a terminal of the resistor B6, the other end of the resistor B6 is connected with the other end of the resistor B1-B4, the other end of the resistor B2 is connected with the resistor B1-B1 is connected with the other end of the resistor B2, the other end of the resistor B1 is connected with the resistor B1-C2, the other end of the resistor B2 is connected with the resistor B1 is connected with the other end of the resistor C1 is connected with the resistor C1, the right end of the switch K1-3 is respectively connected with one end of the grounding resistor R3 and the other end of the resistor R5, the pin 2 of the NOT gate N2 is connected with the pin 1 of the NOT gate N3, the pin 2 of the NOT gate N3 is connected with the control end of the switch K1-2, the pin Y of the NOT gate Y4 is respectively connected with the emitter of the single junction tube T1, one end of the resistor R11 and the positive electrode of the electrolytic capacitor E2, the first base electrode of the single junction tube T1 is connected with one end of the resistor R12, the other end of the resistor R11 and the other end of the resistor R12 are connected with the power supply +12V, the negative electrode of the electrolytic capacitor E2 is connected with the ground, and the second base electrode of the single junction tube T1 is respectively connected with the control electrode of the thyristor VT2 and one end of the grounding resistor R10.
The invention is particularly used, the invention comprises an oscilloscope, the oscilloscope captures an analog circuit detection signal under the triggering of an edge pulse, so as to detect and diagnose a fault point, the edge pulse of the oscilloscope is generated by an edge pulse compensation circuit, a fault position pulse frequency modulation circuit and a pulse detection circuit, the edge pulse compensation circuit receives a preset edge pulse, under the triggering of a fault early warning signal, an analog switch U1 acts, a normally open contact is opened, a normally closed contact is closed, the edge pulse is multiplied by a frequency multiplication circuit, the edge pulse is buffered by an NOT gate N4 after being multiplied by the frequency multiplication circuit, the controllable delay is carried out by a pulse delay circuit, the time delay of a pulse regulation frequency at the position where a fault is positioned is controlled, a pin B of the OR gate Y2 is connected with a pulse of the regulated frequency at the position where the fault position pulse frequency modulation circuit outputs, specifically, the fault position pulse frequency modulation circuit receives the output signal of the pulse detection circuit, when the pulse signal exists, the trigger switch K1-1 is conducted, the frequency multiplication pulse at the position of the fault enters the oscillation circuit formed by the D trigger U2, the U3 and the crystal oscillator U3, the oscillation circuit oscillates at the rising edge and the falling edge of the pulse frequency signal, the frequency of the single frequency multiplication pulse at the position of the fault is changed, the frequency of the single frequency multiplication pulse 3 is set, namely the period of the single pulse is kept unchanged, the frequency is changed to be 3 times, the single frequency multiplication pulse enters the pin B of the OR gate Y2, the oscillation frequency modulation of the single frequency multiplication pulse at the fault position point is realized, the sampling frequency can be locally increased, the signal of interest is selected, the limit of the storage depth can be met, the pin Y of the OR gate Y2 outputs the superposition compensation edge pulse under the control of the pulse detection circuit, when the fault position pulse signal has a pulse signal, the trigger switch K1-2 is closed through the delay of the NOT gates N2 and N3, the edge pulse after superposition compensation is fed back to the pin 1 of the NOT gate N4, the delay control cyclic superposition compensation is realized, when the fault position pulse signal has no pulse signal, the fault position pulse signal enters the oscilloscope through the conducting thyristor VT2, so that the fault position pulse signal is realized, when the fault early warning signal exists, the frequency multiplication sampling is set, the enough sampling rate can be ensured, the full view of the signal is obtained, the oscillation frequency modulation is carried out on the single frequency multiplication pulse of the fault position point, the sampling frequency can be locally increased, the signal of interest is selected, and the limitation of the storage depth can be met.
Claims (4)
1. The analog circuit diagnosis detection device comprises an oscilloscope, wherein the oscilloscope captures an analog circuit detection signal under the triggering of an edge pulse, so as to detect and diagnose a fault point, and the analog circuit diagnosis detection device is characterized in that the edge pulse of the oscilloscope is generated by an edge pulse compensation circuit, a fault position pulse frequency modulation circuit and a pulse detection circuit, the edge pulse compensation circuit receives a preset edge pulse, under the triggering of a fault early warning signal, an analog switch U1 acts, the edge pulse is multiplied by a frequency multiplication circuit, the pulse is controllably delayed by a pulse delay circuit after being multiplied, the pulse is added to a pin A of an OR gate Y2, a pin B of the OR gate Y2 is connected with a pulse with an adjusted frequency at the position where the fault is output by the fault position pulse frequency modulation circuit, the pin Y of the OR gate Y2 outputs an overlapped and compensated edge pulse, and under the control of the pulse detection circuit, the delay control is circularly overlapped and compensated, and the conducted thyristor VT2 enters the oscilloscope;
the fault position pulse frequency modulation circuit receives an output signal of the pulse detection circuit, the pulse signal triggers the switch K1-1 to be conducted, and after frequency multiplication of the position where the fault is located, the pulse enters an oscillating circuit formed by the D trigger U2, the U3 and the crystal oscillator U3, so that the oscillating circuit oscillates at the rising edge and the falling edge of a pulse frequency signal, the frequency of a single frequency multiplication pulse at the position where the fault is located is changed, and the single frequency multiplication pulse enters a pin B of the OR gate Y2;
the pulse detection circuit receives a fault position pulse signal, is detected by a pulse detection circuit consisting of NAND gates Y3 and Y4 as cores, when the pulse signal exists, the lower end of a resistor R7 discharges, an output voltage triggers a switch K1-1 to conduct, a switch K1-2 to conduct and a switch K1-3 to conduct, the frequency of a single frequency multiplication pulse at the position where the fault exists is controlled to be changed respectively, the time delay control cycle superposition compensation and the controllable time delay of a reset control pulse delay circuit are controlled, when no pulse signal exists, a capacitor C5 discharges, the switch K1-1, the switch K1-2 and the switch K1-3 are turned off, the NAND gate Y4 outputs a high level, and the single junction transistor T1 is triggered to conduct and the thyristor VT2 is triggered to conduct.
2. The diagnostic test device for analog circuit according to claim 1, wherein the edge pulse compensation circuit comprises an analog switch U1, a pin 3 of the analog switch U1 is connected to an edge pulse, a pin 1 of the analog switch U1 is connected to a fault pre-warning signal, a pin 2 of the analog switch U1 is connected to one end of a capacitor C1 and a pin 1 of a not gate N1, the other end of the capacitor C1 is connected to one end of a resistor R1 and a negative electrode of a varactor DC1, an anode of the varactor DC1 is connected to a pin a of a nand gate Y1, a pin 2 of the not gate N1 is connected to one end of a capacitor C2, the other end of the capacitor C2 is connected to one end of a resistor R2 and a pin B of the nand gate Y1, the other end of the resistor R1 and the other end of the resistor R2 are connected to a power source +5v, the pin Y of the NOT gate Y1 is respectively connected with the lower end of the switch K1-2 and the pin 1 of the NOT gate N4, the pin 2 of the NOT gate N4 is connected with the pin A of the NOT gate YF1, the pin B of the NOT gate YF1 is respectively connected with one end of the grounding resistor R4 and one end of the capacitor C3, the other end of the capacitor C3 is respectively connected with the cathode of the varactor DC2, one end of the resistor R5 and the anode of the grounding electrolytic capacitor E1, the other end of the resistor R5 is connected with the right end of the switch K1-3, the pin Y of the NOT gate YF1 is connected with the pins A and B of the NOT gate YF2, the pin Y of the NOT gate YF2 is respectively connected with the anode of the varactor DC2 and the pin A of the NOT gate Y2, the pin B of the NOT gate Y2 is connected with the Q end of the D trigger U4, the pin Y of the NOT gate Y2 is respectively connected with the upper end of the switch K1-2 and the anode of the thyristor VT2, and the cathode output of the thyristor VT2 is compensated edge pulse.
3. The diagnostic test device for analog circuit according to claim 1, wherein the fault location pulse frequency modulation circuit comprises a D trigger U2, a D end of the D trigger U2 is connected to a cathode of a diode D2, an anode of the diode D2 is connected to a power +5v, a CP end of the D trigger U2 is connected to a left end of a switch K1-1, a right end of the switch K1-1 is connected to a pin 1 of a not gate N4, a Q end of the D trigger U2 is connected to one end of an inductor L1 and one end of a resistor R9, another end of the inductor L1 is connected to one end of a pin 1 and a pin 4 of a crystal oscillator U3, one end of a ground capacitor C6, a pin 2 of the crystal oscillator U3 is connected to one end of a ground capacitor C7, a pin 3 of the crystal oscillator U3 is connected to one end of a capacitor C8, another end of the capacitor C8 is connected to a CP end of the D trigger U4, and the D and Q ends of the D trigger U4 are connected to a pin B of the or gate Y2.
4. The diagnostic test device for analog circuit according to claim 1, wherein the pulse test circuit comprises a capacitor C4, one end of the capacitor C4 is connected with the fault location pulse signal, the other end of the capacitor C4 is connected with a pin A and a pin B of a NAND gate Y3, one end of a resistor R6 respectively, the other end of the resistor R6 is connected with a power +5V, a pin Y of the NAND gate Y3 is connected with the positive electrode of a diode D1, the negative electrode of the diode D1 is connected with one end of a grounding capacitor C5, one end of a resistor R7, a pin A and a pin B of a NAND gate Y4 respectively, the other end of the resistor R7 is connected with one end of a grounding resistor R8, a control end of a switch K1-1, a control end of a switch K1-3, and a pin 1 of a NOT gate N2 respectively, the left end of the switch K1-3 is connected with one end of the resistor R2, the other end of the resistor R2 is connected with a power supply +5V, the right end of the switch K1-3 is respectively connected with one end of the grounding resistor R3 and the other end of the resistor R5, the pin 2 of the NOT gate N2 is connected with the pin 1 of the NOT gate N3, the pin 2 of the NOT gate N3 is connected with the control end of the switch K1-2, the pin Y of the NOT gate Y4 is respectively connected with the emitter of the single junction tube T1, one end of the resistor R11 and the positive electrode of the electrolytic capacitor E2, the first base electrode of the single junction tube T1 is connected with one end of the resistor R12, the other end of the resistor R11 and the other end of the resistor R12 are connected with the power supply +12V, the negative electrode of the electrolytic capacitor E2 is connected with the ground, and the second base electrode of the single junction tube T1 is respectively connected with the control electrode of the thyristor VT2 and one end of the grounding resistor R10.
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0842439A1 (en) * | 1995-08-01 | 1998-05-20 | Teradyne, Inc. | Low cost cmos tester |
| CN106324330A (en) * | 2015-07-06 | 2017-01-11 | 兰州工业学院 | Parameter measuring system and method of analog circuit |
| CN108693464A (en) * | 2017-04-01 | 2018-10-23 | 亚德诺半导体集团 | Analog input circuit for fault detect senses |
| CN108845247A (en) * | 2018-06-29 | 2018-11-20 | 哈尔滨工业大学 | A kind of analog module method for diagnosing faults |
| CN110233780A (en) * | 2019-07-30 | 2019-09-13 | 漯河医学高等专科学校 | A kind of computer network signal supervisory instrument |
| CN112924762A (en) * | 2021-01-27 | 2021-06-08 | 杭州瑞盟科技有限公司 | Pulse width detection circuit |
Family Cites Families (1)
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- 2022-06-30 CN CN202210758358.5A patent/CN115078977B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0842439A1 (en) * | 1995-08-01 | 1998-05-20 | Teradyne, Inc. | Low cost cmos tester |
| CN106324330A (en) * | 2015-07-06 | 2017-01-11 | 兰州工业学院 | Parameter measuring system and method of analog circuit |
| CN108693464A (en) * | 2017-04-01 | 2018-10-23 | 亚德诺半导体集团 | Analog input circuit for fault detect senses |
| CN108845247A (en) * | 2018-06-29 | 2018-11-20 | 哈尔滨工业大学 | A kind of analog module method for diagnosing faults |
| CN110233780A (en) * | 2019-07-30 | 2019-09-13 | 漯河医学高等专科学校 | A kind of computer network signal supervisory instrument |
| CN112924762A (en) * | 2021-01-27 | 2021-06-08 | 杭州瑞盟科技有限公司 | Pulse width detection circuit |
Non-Patent Citations (1)
| Title |
|---|
| 基于CBAM-CNN的模拟电路故障诊断;杜先君等;《控制与决策》;第1-9页 * |
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