CN115078977A - Diagnosis and detection device for analog circuit - Google Patents
Diagnosis and detection device for analog circuit Download PDFInfo
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- CN115078977A CN115078977A CN202210758358.5A CN202210758358A CN115078977A CN 115078977 A CN115078977 A CN 115078977A CN 202210758358 A CN202210758358 A CN 202210758358A CN 115078977 A CN115078977 A CN 115078977A
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- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/316—Testing of analog circuits
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- Y04S10/50—Systems or methods supporting the power network operation or management, involving a certain degree of interaction with the load-side end user applications
- Y04S10/52—Outage or fault management, e.g. fault detection or location
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Abstract
The invention is used for the analog circuit diagnosis detection device, the edge pulse compensating circuit receives the preset edge pulse, under the trigger of the fault early warning signal, the edge pulse is added to the pin A of the OR gate Y2 through frequency doubling and controllable delay, or the pin B of the gate Y2 is connected with the pulse with the regulated frequency at the position of the fault, the fault position pulse frequency modulation circuit receives the output signal of the pulse detecting circuit, when the pulse signal exists, the frequency of the single frequency-doubled pulse at the position of the fault is changed by the oscillation circuit after the frequency doubling at the position of the fault, or the gate Y2 outputs the superposed compensated edge pulse, under the control of the pulse detecting circuit, the pulse signal exists, the superposed compensated edge pulse is closed through the delay trigger switch K1-2, the superposed compensation is realized, the delayed control cycle superposed compensation is realized, when the pulse signal does not exist, the superposed edge pulse enters the oscilloscope through the conducting thyristor VT2, the method can ensure enough sampling rate, obtain the overall appearance of the signal, locally increase the sampling frequency, meet the storage depth and select the interested signal.
Description
Technical Field
The invention belongs to the technical field of diagnosis and detection, and particularly relates to a diagnosis and detection device for an analog circuit.
Background
Because of the inherent characteristics of continuous variation of analog circuit element parameters, tolerance influence of element parameters, nonlinearity of circuit response and the like, the analog circuit fault diagnosis method is slow to develop, the conventional analog circuit fault diagnosis adopts an oscilloscope to acquire analog circuit test point signals, then fault diagnosis and fault positioning are carried out according to experience or a constructed mathematical model, the oscilloscope accurately acquires the analog circuit test point signals to obtain the overall picture of the signals, particularly the accurate restoration of the fault point signals is vital, proper edge pulses are required to be set to ensure sufficient sampling rate, simultaneously, the capture and storage signals are triggered, the limitation of storage depth is met, the interested signals are selected, therefore, it is desirable to provide a diagnostic test device for analog circuits, which can ensure a sufficient sampling rate to obtain a complete picture of signals, and can satisfy the storage depth to select the signals of interest.
Disclosure of Invention
In order to overcome the defects of the prior art, the invention provides the analog circuit diagnosis and detection device, which sets frequency doubling sampling when a fault early warning signal is generated, and performs oscillation frequency modulation on single frequency-doubled pulse at a fault position point, so that the sufficient sampling rate can be ensured, the overall appearance of the signal can be obtained, the sampling frequency can be locally increased, the storage depth can be met, and the interested signal can be selected.
The technical proposal is that the device comprises an oscilloscope, the oscilloscope captures the detection signal of an analog circuit under the triggering of the edge pulse, the fault point is detected and diagnosed, the edge pulse of the oscilloscope is generated by an edge pulse compensation circuit, a fault position pulse frequency modulation circuit and a pulse detection circuit, the edge pulse compensation circuit receives the preset edge pulse, under the trigger of the fault early warning signal, the analog switch U1 acts, the edge pulse is frequency-doubled by the frequency doubling circuit, the frequency-doubled pulse is time-delayed controllably by the pulse delay circuit and is added to the pin A of the OR gate Y2, the pin B of the OR gate Y2 is connected with the pulse with the adjusted frequency of the position of the fault output by the fault position pulse frequency modulation circuit, the pin Y of the OR gate Y2 outputs the superposition compensation back edge pulse, under the control of the pulse detection circuit, the delay control loop is superposed and compensated, and enters an oscilloscope through the conducted thyristor VT 2;
the fault position pulse frequency modulation circuit receives an output signal of the pulse detection circuit, the pulse signal triggers the switch K1-1 to be switched on, the frequency-doubled pulse at the fault position enters an oscillation circuit consisting of the D trigger U2, the U3 and the crystal oscillator U3, so that the oscillation circuit oscillates on the rising edge and the falling edge of the pulse frequency signal, the frequency of the single frequency-doubled pulse at the fault position is changed, and the single frequency-doubled pulse enters the pin B of the OR gate Y2;
the pulse detection circuit receives a fault position pulse signal, and is detected by a pulse detection circuit which is composed of NAND gates Y3 and Y4 as cores, when the pulse signal exists, the lower end of a resistor R7 discharges, an output voltage triggers a switch K1-1 to be conducted, a switch K1-2 to be conducted and a switch K1-3 to be conducted, the frequency of a single frequency-doubled pulse at the position of the fault is respectively controlled and changed, delay control loop superposition compensation and reset control pulse delay circuit controllable delay are controlled, when the pulse signal does not exist, a capacitor C5 discharges, the switch K1-1, the switch K1-2 and the switch K1-3 are cut off, the NAND gate Y4 outputs a high level, and a single junction transistor T1 and a thyristor VT2 are triggered to be conducted.
The invention has the beneficial effects that: the preset edge pulse is triggered by a fault early warning signal, an analog switch U1 acts, a normally open contact is opened, a normally closed contact is closed, the edge pulse is subjected to frequency multiplication by a frequency multiplication circuit and is added to a pin A of an OR gate Y2 through controllable delay of a pulse delay circuit, time delay of frequency adjustment of a position pulse of a fault is controlled, so that the connection signals of the pin A and the pin B of the OR gate Y2 are kept synchronous, the pin B of the gate Y2 is connected to a pulse of the position of the fault output by a fault position pulse frequency modulation circuit, the pulse of the adjusted frequency is output by the pin B of the gate Y2, the edge pulse after superposition compensation is output by the pin Y of the gate Y2, under the control of a pulse detection circuit, specifically, when the pulse signal of the fault position has the pulse signal, the edge pulse is delayed by NOT-gate N2 and N3, a trigger switch K1-2 is closed, the edge pulse after superposition compensation is fed back to a pin 1 of the NOT-gate N4, so that the superposition compensation of the delay control loop superposition compensation is realized, when the pulse signal at the fault position has no pulse signal, the pulse signal enters the oscilloscope through the conducted thyristor VT2, so that the method is realized, when the fault early warning signal has a fault, frequency doubling sampling is set, the sufficient sampling rate can be ensured, the overall appearance of the signal is obtained, single frequency-doubled pulse at the fault position is subjected to oscillation frequency modulation, the sampling frequency can be locally increased, the signal of interest is selected, and the limitation of the storage depth can be met.
Drawings
Fig. 1 is a schematic diagram of the circuit of the present invention.
Detailed Description
The technical solutions of the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings, and it is to be understood that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments.
The following description will explain embodiments of the present invention in further detail with reference to fig. 1 of the specification.
The device is used for diagnosing and detecting the analog circuit and comprises an oscilloscope, the oscilloscope captures the detection signal of the analog circuit under the trigger of an edge pulse so as to detect and diagnose a fault point, the edge pulse of the oscilloscope is generated by an edge pulse compensation circuit, a fault position pulse frequency modulation circuit and a pulse detection circuit, the edge pulse compensation circuit receives the preset edge pulse, under the trigger of a fault early warning signal, an analog switch U1 with the model of MAX333 acts, a normally open contact is opened, a normally closed contact is closed, the edge pulse is subjected to frequency multiplication by a frequency multiplication circuit, after the frequency multiplication is carried out, the edge pulse is buffered by a NOT gate N4, the controllable time delay is carried out by a pulse delay circuit and is added to a pin A of an OR gate Y2, the time delay of the adjustment frequency of the position pulse at which the fault is carried out is controlled, so that the access signals of a pin A and a pin B of the OR gate Y2 are kept synchronous, or the pin B of the gate Y2 is accessed to the pulse with the adjusted frequency of the position at which is output by the fault position pulse frequency modulation circuit, a pin Y of an OR gate Y2 outputs a superposition compensation rear edge pulse, under the control of a pulse detection circuit, specifically, when a pulse signal exists at a fault position, the delay control loop superposition compensation is realized by delaying the time of a NOT gate N2 and N3, a trigger switch K1-2 is closed, the superposition compensation rear edge pulse is fed back to a pin 1 of the NOT gate N4, when the pulse signal does not exist at the fault position, the pulse signal enters an oscilloscope through a conducted thyristor VT2, so that the realization is realized, when a fault early warning signal exists, frequency doubling sampling is set, enough sampling rate can be ensured, the full appearance of the signal is obtained, single frequency doubling rear pulse at the fault position is subjected to oscillation frequency modulation, the sampling frequency can be locally increased, an interested signal is selected, and the limitation of storage depth can be met;
the fault position pulse frequency modulation circuit receives a pulse detection circuit output signal, when a pulse signal exists, the trigger switch K1-1 is switched on, the frequency-doubled pulse at the fault position enters an oscillation circuit consisting of a D trigger U2, a U3 and a crystal oscillator U3, so that the oscillation circuit oscillates on the rising edge and the falling edge of the pulse frequency signal, the frequency of the single frequency-doubled pulse at the fault position is changed, the frequency doubling of the single frequency-doubled pulse 3 is set, namely the period of the single pulse is kept unchanged, the frequency is changed to 3 times, and the single frequency-doubled pulse enters a pin B of an OR gate Y2, so that the oscillation frequency modulation of the single frequency-doubled pulse at the fault position point is realized, the sampling frequency can be locally increased, an interested signal is selected, and the limitation of storage depth can be met;
the pulse detection circuit receives a pulse signal of a fault position, the pulse signal is detected by a pulse detection circuit which is composed of NAND gates Y3 and Y4 as cores, when the pulse signal exists, the pulse is charged through a capacitor C4 and is discharged through a resistor R7, the resistor R7 and the resistor R8 output voltage to trigger a switch K1-1 to be switched on, a switch K1-2 to be switched on in a delayed mode and a switch K1-3 to be switched on, the frequency of a single frequency-doubled pulse at the position of the fault is respectively controlled to change, cyclic superposition compensation is controlled in a delayed mode, a pulse delay circuit is controlled to reset and control the delay time to be delayed, when the pulse signal does not exist, the capacitor C5 discharges, the switch K1-1, the switch K1-2 and the switch K1-3 are switched off, the Y4 outputs a high level VT 56, the unijunction transistor T1 is triggered to be switched on, the thyristor VT2 is switched on, and the cathode of the thyristor 2 outputs compensation along the pulse and enters an oscilloscope.
In the above technical solution, the edge pulse compensation circuit receives a preset edge pulse, under the trigger of a fault early warning signal (specifically, the fault early warning signal may be triggered by a high-low voltage output by a photocoupler of an analog circuit fault diagnosis circuit), an analog switch U1 with a model of MAX333 is operated, a normally open contact is opened, a normally closed contact is closed, the edge pulse is frequency-doubled by a frequency doubling circuit composed of a not gate N1, a nand gate Y1, a resistor R1, a resistor R2, capacitors C1 and C2, and a varactor DC1, after the frequency-doubled edge pulse is buffered by a not gate N4, the frequency-doubled edge pulse is controlled to be delayed by a pulse delay circuit composed of a nand gate YF1, a nand gate YF2, a resistor R4, a resistor R5, a capacitor C3, an electrolytic capacitor E1, and a varactor DC2, and is added to a pin a of an or gate Y2, specifically, when a fault position pulse signal has a pulse signal, the switch K1-3 is closed, and the resistor R2, and the resistor R3 are closed, A reset circuit consisting of a switch K1-3 outputs a divided voltage which is reversely added to the cathode of a variable capacitance diode DC2 through a resistor R5 and an electrolytic capacitor E1, the time delay of the pulse regulation frequency of the position where the fault is located is controlled, so that the access signals of a pin A and a pin B of an OR gate Y2 are kept synchronous, the pin B of the OR gate Y2 is accessed to the pulse of the position where the fault is located and the frequency of the pulse is regulated, which is output by a fault position pulse frequency modulation circuit, or the pin Y of a gate Y2 outputs an edge pulse after superposition compensation, under the control of a pulse detection circuit, specifically, when the pulse signal of the fault position has the pulse signal, the switch K1-2 is triggered to be closed through the time delays of NOT gates N2 and N3, the edge pulse after the superposition compensation is fed back to a pin 1 of the NOT gate N4, the superposition compensation of the delay control cycle is realized, and when the pulse signal of the fault position has no pulse signal, the voltage enters an oscilloscope through a conductive thyristor 2, the method is realized by setting frequency multiplication sampling when a fault early warning signal occurs, so that enough sampling rate can be ensured, a signal complete picture can be obtained, oscillation frequency modulation can be performed on single frequency multiplication rear pulse of a fault position point, the sampling frequency can be locally increased, an interested signal can be selected, and the limitation of storage depth can be met, and the method comprises an analog switch U1, wherein a pin 3 of the analog switch U1 is connected with an edge pulse, a pin 1 of an analog switch U1 is connected with the fault early warning signal, a pin 2 of the analog switch U1 is respectively connected with one end of a capacitor C1 and a pin 1 of a NOT gate N1, the other end of the capacitor C1 is respectively connected with one end of a resistor R1, a cathode of a varactor DC1, an anode of the varactor DC1 is connected with a pin A of a NAND gate Y1, a pin 2 of the NOT gate N1 is connected with one end of a capacitor C2, the other end of the capacitor C2 is respectively connected with one end of a resistor R2, a pin B of a NAND gate Y1, and the other end of a resistor R1, The other end of the resistor R2 is connected with a power supply +5V, a pin Y of the NOT gate Y1 is respectively connected with the lower end of the switch K1-2 and a pin 1 of the NOT gate N4, a pin 2 of the NOT gate N4 is connected with a pin A of the NAND gate YF1, a pin B of the NAND gate YF1 is respectively connected with one end of a grounding resistor R4 and one end of a capacitor C3, the other end of the capacitor C3 is respectively connected with the cathode of a variable capacitance diode DC2, one end of a resistor R5 and the anode of a grounding electrolytic capacitor E1, the other end of the resistor R5 is connected with the right end of a switch K1-3, the pin Y of the NAND gate YF1 is connected with the pins A and B of the NAND gate YF2, the pin Y of the NAND gate YF2 is respectively connected with the anode of the varactor DC2 and the pin A of the OR gate Y2, pin B of the OR gate Y2 is connected with the Q end of the D trigger U4, pin Y of the OR gate Y2 is respectively connected with the upper end of the switch K1-2 and the anode of the thyristor VT2, and the cathode of the thyristor VT2 outputs the compensated trailing edge pulse.
In the technical scheme, the fault position pulse frequency modulation circuit receives a pulse detection circuit output signal, when a pulse signal exists, the trigger switch K1-1 is switched on, the frequency-doubled pulse at the fault position enters an oscillation circuit consisting of a D trigger U2, a U3 and a crystal oscillator U3, the oscillation circuit oscillates on the rising edge and the falling edge of the pulse frequency signal, the frequency of the single frequency-doubled pulse at the fault position is changed, 3 frequency doubling of the single frequency-doubled pulse is set, namely the period of the single pulse is kept unchanged, the frequency is changed into 3 times, the single frequency-doubled pulse enters a pin B of an OR gate Y2, the oscillation frequency modulation of the single frequency-doubled pulse at the fault position point is realized, the sampling frequency can be locally increased, an interested signal is selected, and the limitation of the storage depth can be met, the D trigger U2 is included, the D end of a D trigger U2 is connected with the cathode of a diode D2, the anode of the diode D2 is connected with +5V of a power supply, the CP end of the D trigger U2 is connected with the left end of the switch K1-1, the right end of the switch K1-1 is connected with the pin 1 of the NOT gate N4, the Q end of the D trigger U2 is connected with one end of an inductor L1 and one end of a resistor R9, the other end of the inductor L1 is connected with the pin 1 and the pin 4 of the crystal oscillator U3 and one end of a grounding capacitor C6, the pin 2 of the crystal oscillator U3 is connected with one end of the grounding capacitor C7, the pin 3 of the crystal oscillator U3 is connected with one end of the capacitor C8, the other end of the capacitor C8 is connected with the CP end of the D trigger U4, and the D end and the Q end of the D trigger U4 are connected with the pin B of the OR gate Y2.
In the above technical solution, the pulse detection circuit receives a pulse signal at a fault location (specifically, the pulse detection circuit may be an analog circuit fault diagnosis circuit, a modulation pulse output by a first multiplier or a second multiplier), and the pulse signal is detected by a pulse detection circuit composed of nand gates Y3 and Y4 as cores, when the pulse signal is present, the pulse is charged by a capacitor C4 and discharged by a resistor R7, the resistor R7 and the resistor R8 output voltages to trigger the switch K1-1 to be turned on, the switch K1-2 to be turned on in a delayed manner, and the switch K1-3 to be turned on, so as to respectively control the frequency of a single pulse after frequency multiplication at the fault location, delay control cyclic superposition compensation, and reset control the controllable delay of the pulse delay circuit, when no pulse signal is present, the capacitor C5 is discharged, the switch K1-1, the switch K1-2, the switch K nand gate 1-3 is turned off, and the Y4 outputs a high level to trigger the single junction transistor T1 to be turned on, a single junction transistor T1 is turned on, and a single junction is turned on when no pulse signal is generated, The thyristor VT2 is turned on, the cathode of the thyristor VT2 is output and compensated and then enters the oscilloscope along pulses, the oscilloscope comprises a capacitor C4, one end of the capacitor C4 is connected with a fault position pulse signal, the other end of the capacitor C4 is respectively connected with a pin A and a pin B of a NAND gate Y3 and one end of a resistor R6, the other end of the resistor R6 is connected with a power supply +5V, a pin Y of a NAND gate Y3 is connected with the anode of a diode D1, the cathode of the diode D1 is respectively connected with one end of a grounded capacitor C5, one end of a resistor R7, a pin A and a pin B of a NAND gate Y4, the other end of the resistor R7 is respectively connected with one end of a grounded resistor R8, a control end of a switch K1-1, a control end of a switch K1-3 and a pin 1 of a NOT gate N2, the left end of a switch K1-3 is connected with one end of a resistor R2, the other end of a resistor R2 is connected with the power supply +5V, and the right end of a switch 1-3 is respectively connected with a ground resistor R3, The other end of the resistor R5, a pin 2 of the NOT gate N2 is connected with a pin 1 of the NOT gate N3, a pin 2 of the NOT gate N3 is connected with a control end of the switch K1-2, a pin Y of the NAND gate Y4 is respectively connected with an emitter of the unijunction transistor T1, one end of the resistor R11 and the anode of the electrolytic capacitor E2, a first base of the unijunction transistor T1 is connected with one end of the resistor R12, the other end of the resistor R11 and the other end of the resistor R12 are connected with a power supply +12V, a cathode of the electrolytic capacitor E2 is connected with the ground, and a second base of the unijunction transistor T1 is respectively connected with a control electrode of the thyristor VT2 and one end of the ground resistor R10.
When the invention is used, the oscilloscope captures the detection signal of the analog circuit under the trigger of the edge pulse, so as to detect and diagnose the fault point, the edge pulse of the oscilloscope is generated by the edge pulse compensation circuit, the fault position pulse frequency modulation circuit and the pulse detection circuit, concretely, the edge pulse compensation circuit receives the preset edge pulse, under the trigger of the fault early warning signal, the analog switch U1 acts, the normally open contact is opened, the normally closed contact is closed, the edge pulse is frequency-multiplied by the frequency multiplication circuit, after the frequency multiplication, the edge pulse is buffered by the inverter N4, the time delay is controlled by the pulse delay circuit and is added to the pin A of the OR gate Y2, the time delay of the position pulse adjustment frequency of the fault position is controlled, or the pin B of the gate Y2 is connected to the pulse with the adjusted frequency of the fault position output by the fault position pulse frequency modulation circuit, concretely, the fault position pulse frequency modulation circuit receives a pulse detection circuit output signal, when a pulse signal exists, a trigger switch K1-1 is conducted, a frequency-doubled pulse at the position of the fault enters an oscillation circuit consisting of a D trigger U2, a D trigger U3 and a crystal oscillator U3, the oscillation circuit oscillates on the rising edge and the falling edge of a pulse frequency signal, the frequency of a single frequency-doubled pulse at the position of the fault is changed, frequency doubling of the single frequency-doubled pulse 3 is set, namely the period of the single pulse is kept unchanged, the frequency is changed into 3 times, the single frequency-doubled pulse enters a pin B of an OR gate Y2, oscillation frequency modulation of the single frequency-doubled pulse at the fault position point is realized, the sampling frequency can be locally increased, an interested signal is selected, the limitation of the storage depth can be met, or the pin Y of the gate Y2 outputs a superposed compensated edge pulse, and under the control of the pulse detection circuit, specifically, when the fault position pulse signal exists, the trigger switch K1-2 is closed after time delay of the NOT gate N2 and N3, edge pulse after superposition compensation is fed back to a pin 1 of the NOT gate N4, the time delay control loop superposition compensation is realized, when a pulse signal at a fault position has no pulse signal, the edge pulse enters an oscilloscope through a conducted thyristor VT2, and therefore, when a fault early warning signal occurs, frequency doubling sampling is set, sufficient sampling rate can be guaranteed, the complete picture of the signal is obtained, single frequency doubling pulse at the fault position is subjected to oscillation frequency modulation, the sampling frequency can be locally increased, the signal of interest is selected, and the limitation of storage depth can be met.
Claims (4)
1. The device is used for diagnosing and detecting the analog circuit and comprises an oscilloscope, the oscilloscope captures the detection signal of the analog circuit under the trigger of the edge pulse so as to detect and diagnose the fault point, and the device is characterized in that the edge pulse of the oscilloscope is generated by an edge pulse compensation circuit, a fault position pulse frequency modulation circuit and a pulse detection circuit, the edge pulse compensation circuit receives the preset edge pulse, under the trigger of a fault early warning signal, an analog switch U1 acts, the edge pulse is frequency-multiplied by a frequency multiplication circuit, the time delay is controlled by a pulse delay circuit after the frequency multiplication, the pulse is added to a pin A of an OR gate Y2 or a pin B of a gate Y2 is connected with a pulse with the regulated frequency at the position of the fault output by the fault position pulse frequency modulation circuit, or the pin Y of the gate Y2 outputs the edge pulse after superposition compensation, and under the control of the pulse detection circuit, the cyclic superposition compensation is controlled by the time delay, entering an oscilloscope through the conducted thyristor VT 2;
the fault position pulse frequency modulation circuit receives an output signal of the pulse detection circuit, the pulse signal triggers the switch K1-1 to be switched on, the frequency-doubled pulse at the fault position enters an oscillation circuit consisting of the D trigger U2, the U3 and the crystal oscillator U3, so that the oscillation circuit oscillates on the rising edge and the falling edge of the pulse frequency signal, the frequency of the single frequency-doubled pulse at the fault position is changed, and the single frequency-doubled pulse enters the pin B of the OR gate Y2;
the pulse detection circuit receives a fault position pulse signal, and is detected by a pulse detection circuit which is composed of NAND gates Y3 and Y4 as cores, when the pulse signal exists, the lower end of a resistor R7 discharges, an output voltage triggers a switch K1-1 to be conducted, a switch K1-2 to be conducted and a switch K1-3 to be conducted, the frequency of a single frequency-doubled pulse at the position of the fault is respectively controlled and changed, delay control loop superposition compensation and reset control pulse delay circuit controllable delay are controlled, when the pulse signal does not exist, a capacitor C5 discharges, the switch K1-1, the switch K1-2 and the switch K1-3 are cut off, the NAND gate Y4 outputs a high level, and a single junction transistor T1 and a thyristor VT2 are triggered to be conducted.
2. The analog circuit diagnosis and detection device as claimed in claim 1, wherein the edge pulse compensation circuit comprises an analog switch U1, a pin 3 of the analog switch U1 is connected with the edge pulse, a pin 1 of the analog switch U1 is connected with the fault pre-warning signal, a pin 2 of the analog switch U1 is respectively connected with one end of a capacitor C1 and a pin 1 of a not-gate N1, the other end of the capacitor C1 is respectively connected with one end of a resistor R1 and the cathode of a varactor DC1, the anode of the varactor DC1 is connected with a pin A of a NAND-gate Y1, a pin 2 of the not-gate N1 is connected with one end of a capacitor C2, the other end of the capacitor C2 is respectively connected with one end of a resistor R2 and a pin B of a NAND-gate Y1, the other end of the resistor R5 and the other end of the resistor R2 are connected with a power supply +5V, a pin Y of the not-gate Y1 is respectively connected with the lower end of a switch K1-2, a pin 1 of a not-gate N4 and a pin 573 2 of a pin 686 9, a pin B of the NAND gate YF1 is respectively connected with one end of a grounding resistor R4 and one end of a capacitor C3, the other end of the capacitor C3 is respectively connected with the negative electrode of the varactor DC2, one end of a resistor R5 and the positive electrode of a grounding electrolytic capacitor E1, the other end of the resistor R5 is connected with the right end of a switch K1-3, a pin Y of the NAND gate YF1 is connected with pins A and B of the NAND gate YF2, a pin Y of the NAND gate YF2 is respectively connected with the positive electrode of the varactor DC2 or a pin A of the gate Y2, a pin B of the gate Y2 is connected with a Q end of a D flip-flop U4, a pin Y of the gate Y2 is respectively connected with the upper end of the switch K1-2 and the anode of the thyristor VT2, and the cathode of the thyristor VT2 outputs a compensated back edge pulse.
3. The diagnostic test device for analog circuits according to claim 1, the fault position pulse frequency modulation circuit comprises a D trigger U2, the D end of a D trigger U2 is connected with the cathode of a diode D2, the anode of the diode D2 is connected with +5V, the CP end of the D trigger U2 is connected with the left end of a switch K1-1, the right end of the switch K1-1 is connected with a pin 1 of a NOT gate N4, the Q end of the D trigger U2 is respectively connected with one end of an inductor L1 and one end of a resistor R9, the other end of the inductor L1 is respectively connected with a pin 1 and a pin 4 of a crystal oscillator U3 and one end of a grounding capacitor C6, a pin 2 of the crystal oscillator U3 is connected with one end of a grounding capacitor C7, a pin 3 of the crystal oscillator U3 is connected with one end of a capacitor C8, the other end of the capacitor C8 is connected with the CP end of a D trigger U4, and the D end and the Q end of a D trigger U4 are connected with a pin B of a gate Y2.
4. The apparatus as claimed in claim 1, wherein the pulse detection circuit comprises a capacitor C4, one end of the capacitor C4 is connected to the fault location pulse signal, the other end of the capacitor C4 is connected to the pin a and pin B of the nand gate Y3 and one end of the resistor R6, the other end of the resistor R6 is connected to +5V, the pin Y of the nand gate Y3 is connected to the anode of the diode D1, the cathode of the diode D1 is connected to one end of the grounded capacitor C5, one end of the resistor R7, the pin a and pin B of the nand gate Y4, the other end of the resistor R7 is connected to one end of the grounded resistor R8, the control end of the switch K1-1, the control end of the switch K1-3, the pin 1 of the not gate N2, the left end of the switch K1-3 is connected to one end of the resistor R2, the other end of the resistor R2 is connected to +5V, and the right end of the switch K1-3 is connected to one end of the ground resistor R3, The other end of the resistor R5, a pin 2 of the NOT gate N2 is connected with a pin 1 of the NOT gate N3, a pin 2 of the NOT gate N3 is connected with a control end of the switch K1-2, a pin Y of the NAND gate Y4 is respectively connected with an emitter of the unijunction transistor T1, one end of the resistor R11 and the anode of the electrolytic capacitor E2, a first base of the unijunction transistor T1 is connected with one end of the resistor R12, the other end of the resistor R11 and the other end of the resistor R12 are connected with a power supply +12V, a cathode of the electrolytic capacitor E2 is connected with the ground, and a second base of the unijunction transistor T1 is respectively connected with a control electrode of the thyristor VT2 and one end of the ground resistor R10.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210758358.5A CN115078977B (en) | 2022-06-30 | 2022-06-30 | Diagnostic test device for analog circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210758358.5A CN115078977B (en) | 2022-06-30 | 2022-06-30 | Diagnostic test device for analog circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN115078977A true CN115078977A (en) | 2022-09-20 |
| CN115078977B CN115078977B (en) | 2023-06-02 |
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| CN106324330A (en) * | 2015-07-06 | 2017-01-11 | 兰州工业学院 | Parameter measuring system and method of analog circuit |
| CN108693464A (en) * | 2017-04-01 | 2018-10-23 | 亚德诺半导体集团 | Analog input circuit for fault detect senses |
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| CN110233780A (en) * | 2019-07-30 | 2019-09-13 | 漯河医学高等专科学校 | A kind of computer network signal supervisory instrument |
| CN112924762A (en) * | 2021-01-27 | 2021-06-08 | 杭州瑞盟科技有限公司 | Pulse width detection circuit |
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| CN106324330A (en) * | 2015-07-06 | 2017-01-11 | 兰州工业学院 | Parameter measuring system and method of analog circuit |
| CN108693464A (en) * | 2017-04-01 | 2018-10-23 | 亚德诺半导体集团 | Analog input circuit for fault detect senses |
| CN108845247A (en) * | 2018-06-29 | 2018-11-20 | 哈尔滨工业大学 | A kind of analog module method for diagnosing faults |
| CN110233780A (en) * | 2019-07-30 | 2019-09-13 | 漯河医学高等专科学校 | A kind of computer network signal supervisory instrument |
| CN112924762A (en) * | 2021-01-27 | 2021-06-08 | 杭州瑞盟科技有限公司 | Pulse width detection circuit |
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